Add the low pass audio clock controller device nodes.
Signed-off-by: Taniya Das <[email protected]>
---
* Fix unwanted extra spaces in reg property.
* Fix lpass_aon node clock phandle <&lpasscc> to <&lpasscore>
arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 937c2e0e93eb..0d8a0d9d0f89 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -8,6 +8,8 @@
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
+#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
+#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7280.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
@@ -1744,6 +1746,47 @@
#clock-cells = <1>;
};
+ lpass_audiocc: clock-controller@3300000 {
+ compatible = "qcom,sc7280-lpassaudiocc";
+ reg = <0 0x03300000 0 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
+ clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
+ power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ lpass_aon: clock-controller@3380000 {
+ compatible = "qcom,sc7280-lpassaoncc";
+ reg = <0 0x03380000 0 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&lpasscore LPASS_CORE_CC_CORE_CLK>;
+ clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ lpasscore: clock-controller@3900000 {
+ compatible = "qcom,sc7280-lpasscorecc";
+ reg = <0 0x03900000 0 0x50000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+ lpass_hm: clock-controller@3c00000 {
+ compatible = "qcom,sc7280-lpasshm";
+ reg = <0 0x3c00000 0 0x28>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "bi_tcxo";
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
lpass_ag_noc: interconnect@3c40000 {
reg = <0 0x03c40000 0 0xf080>;
compatible = "qcom,sc7280-lpass-ag-noc";
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
Quoting Taniya Das (2022-02-01 21:32:07)
> Add the low pass audio clock controller device nodes.
>
> Signed-off-by: Taniya Das <[email protected]>
> ---
Reviewed-by: Stephen Boyd <[email protected]>
Quoting Taniya Das (2022-02-01 21:32:07)
> Add the low pass audio clock controller device nodes.
>
> Signed-off-by: Taniya Das <[email protected]>
> ---
> * Fix unwanted extra spaces in reg property.
> * Fix lpass_aon node clock phandle <&lpasscc> to <&lpasscore>
>
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 937c2e0e93eb..0d8a0d9d0f89 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1744,6 +1746,47 @@
> #clock-cells = <1>;
> };
>
> + lpass_audiocc: clock-controller@3300000 {
> + compatible = "qcom,sc7280-lpassaudiocc";
> + reg = <0 0x03300000 0 0x30000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
> + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
> + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + lpass_aon: clock-controller@3380000 {
> + compatible = "qcom,sc7280-lpassaoncc";
> + reg = <0 0x03380000 0 0x30000>;
I see that this region overlaps with the third region of lpasscc@3000000
in this file. That means the driver for this clk controller doesn't
probe. I don't know what the correct fix is, but it's either remove this
node and move the driver contents to lpasscc or remove the region from
lpasscc and provide those clks from this node.
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&lpasscore LPASS_CORE_CC_CORE_CLK>;
> + clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
Thanks & Regards,
Taniya Das.
-----Original Message-----
From: Stephen Boyd <[email protected]>
Sent: Saturday, April 16, 2022 1:54 AM
To: [email protected]; Rob Herring <[email protected]>; Taniya Das (QUIC) <[email protected]>
Cc: Douglas Anderson <[email protected]>; Andy Gross <[email protected]>; [email protected]; [email protected]; [email protected]; Taniya Das <[email protected]>
Subject: Re: [PATCH v3] arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers
Quoting Taniya Das (2022-02-01 21:32:07)
> Add the low pass audio clock controller device nodes.
>
> Signed-off-by: Taniya Das <[email protected]>
> ---
> * Fix unwanted extra spaces in reg property.
> * Fix lpass_aon node clock phandle <&lpasscc> to <&lpasscore>
>
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 43
> ++++++++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 937c2e0e93eb..0d8a0d9d0f89 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1744,6 +1746,47 @@
> #clock-cells = <1>;
> };
>
> + lpass_audiocc: clock-controller@3300000 {
> + compatible = "qcom,sc7280-lpassaudiocc";
> + reg = <0 0x03300000 0 0x30000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>;
> + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
> + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
> + #clock-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> + lpass_aon: clock-controller@3380000 {
> + compatible = "qcom,sc7280-lpassaoncc";
> + reg = <0 0x03380000 0 0x30000>;
I see that this region overlaps with the third region of lpasscc@3000000 in this file. That means the driver for this clk controller doesn't probe. I don't know what the correct fix is, but it's either remove this node and move the driver contents to lpasscc or remove the region from lpasscc and provide those clks from this node.
[Taniya Das] Sure, I can remove the node which should be the cleaner way.
> + clocks = <&rpmhcc RPMH_CXO_CLK>,
> + <&rpmhcc RPMH_CXO_CLK_A>,
> + <&lpasscore LPASS_CORE_CC_CORE_CLK>;
> + clock-names = "bi_tcxo", "bi_tcxo_ao",
> + "iface";
Quoting Taniya Das (QUIC) (2022-04-21 10:40:28)
>
> [Taniya Das] Sure, I can remove the node which should be the cleaner way.
If the node is removed then the driver should be removed as well? Did
you send a patch to do this?