This series attempts to introduce Adreno 700 support (with A730 and A740
found on SM8450 and SM8550 respectively), reusing much of the existing
A6xx code. This submission largely lays the groundwork for expansion and
more or less gives us feature parity (on the kernel side, that is) with
existing A6xx parts.
On top of introducing a very messy set of three (!) separate and
obfuscated deivce identifiers for each 7xx part, this generation
introduces very sophisticated hardware multi-threading and (on some SKUs)
hardware ray-tracing (not supported yet).
After this series, a long-overdue cleanup of drm/msm/adreno is planned
in preparation for adding more features and removing some hardcoding.
The last patch is a hack that may or may not be necessary depending
on your board's humour.. eh.. :/
Developed atop (and hence depends on) [1]
The corresponding devicetree patches are initially available at [2] and
will be posted after this series gets merged. To test it, you'll also need
firmware that you need to obtain from your board (there's none with a
redistributable license, sorry..). Most likely it will be in one of
these directories on your stock android installation:
* /vendor/firmware
* /vendor/firmware_mnt
* /system
..but some vendors make it hard and you have to do some grepping ;)
Requires [3] to work on the userspace side. You'll almost cerainly want
to test it alongside Zink with a lot of debug flags (early impl), like:
TU_DEBUG=sysmem,nolrz,flushall,noubwc MESA_LOADER_DRIVER_OVERRIDE=zink kmscube
[1] https://lore.kernel.org/linux-arm-msm/[email protected]/
[2] https://github.com/SoMainline/linux/commits/topic/a7xx_dt
[3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217
Signed-off-by: Konrad Dybcio <[email protected]>
---
Changes in v2:
- Rebase on chipid changes
- Reuse existing description for qcom,aoss in patch 2
- Pick up tags
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Konrad Dybcio (14):
dt-bindings: display/msm/gmu: Add Adreno 7[34]0 GMU
dt-bindings: display/msm/gmu: Allow passing QMP handle
dt-bindings: display/msm/gpu: Allow A7xx SKUs
drm/msm/a6xx: Add missing regs for A7XX
drm/msm/a6xx: Introduce a6xx_llc_read
drm/msm/a6xx: Move LLC accessors to the common header
drm/msm/a6xx: Bail out early if setting GPU OOB fails
drm/msm/a6xx: Add skeleton A7xx support
drm/msm/a6xx: Send ACD state to QMP at GMU resume
drm/msm/a6xx: Mostly implement A7xx gpu_state
drm/msm/a6xx: Add A730 support
drm/msm/a6xx: Add A740 support
drm/msm/a6xx: Vastly increase HFI timeout
drm/msm/a6xx: Poll for GBIF unhalt status in hw_init
.../devicetree/bindings/display/msm/gmu.yaml | 47 +-
.../devicetree/bindings/display/msm/gpu.yaml | 4 +-
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 204 +++++--
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 8 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 667 ++++++++++++++++++---
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 +
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 61 +-
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 90 ++-
drivers/gpu/drm/msm/adreno/adreno_device.c | 30 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 7 +-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 28 +-
drivers/gpu/drm/msm/msm_ringbuffer.h | 2 +
15 files changed, 1094 insertions(+), 133 deletions(-)
---
base-commit: b30de2c05cf2166f4e2c68850efc8dcea1c89780
change-id: 20230628-topic-a7xx_drmmsm-123f30d76cf7
Best regards,
--
Konrad Dybcio <[email protected]>
Move these wrappers in preparation for use in a6xx_gmu.c
Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD
Tested-by: Dmitry Baryshkov <[email protected]> # sm8450
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ---------------
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 +++++++++++++++
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 0fef92f71c4e..6dd6d72bcd86 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1735,21 +1735,6 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
return IRQ_HANDLED;
}
-static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
-{
- return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
-}
-
-static u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
-{
- return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
-}
-
-static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
-{
- msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
-}
-
static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
{
llcc_slice_deactivate(a6xx_gpu->llc_slice);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index ab66d281828c..34822b080759 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -62,6 +62,21 @@ static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
return true;
}
+static inline void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
+{
+ return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
+}
+
+static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
+{
+ return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
+}
+
+static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
+{
+ msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
+}
+
#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
((_ring)->id * sizeof(uint32_t)))
--
2.41.0
Add some missing definitions required for A7 support.
This may be substituted with a mesa header sync.
Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD
Tested-by: Dmitry Baryshkov <[email protected]> # sm8450
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +++++++++
drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
index 1c051535fd4a..863b5e3b0e67 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -1114,6 +1114,12 @@ enum a6xx_tex_type {
#define REG_A6XX_CP_MISC_CNTL 0x00000840
#define REG_A6XX_CP_APRIV_CNTL 0x00000844
+#define A6XX_CP_APRIV_CNTL_CDWRITE 0x00000040
+#define A6XX_CP_APRIV_CNTL_CDREAD 0x00000020
+#define A6XX_CP_APRIV_CNTL_RBRPWB 0x00000008
+#define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL 0x00000004
+#define A6XX_CP_APRIV_CNTL_RBFETCH 0x00000002
+#define A6XX_CP_APRIV_CNTL_ICACHE 0x00000001
#define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0
@@ -1939,6 +1945,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00
#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
+#define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f
+
#define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
@@ -8252,5 +8260,6 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val)
#define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002
+#define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039
#endif /* A6XX_XML */
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
index fcd9eb53baf8..5b66efafc901 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h
@@ -360,6 +360,12 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
#define REG_A6XX_GMU_GENERAL_7 0x000051cc
+#define REG_A6XX_GMU_GENERAL_8 0x000051cd
+
+#define REG_A6XX_GMU_GENERAL_9 0x000051ce
+
+#define REG_A6XX_GMU_GENERAL_10 0x000051cf
+
#define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d
#define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920
@@ -471,6 +477,8 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101
+#define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x00000154
+
#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180
#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346
--
2.41.0
Add a helper that does exactly what it says on the can, it'll be
required for A7xx.
Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD
Tested-by: Dmitry Baryshkov <[email protected]> # sm8450
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 1ed202c4e497..0fef92f71c4e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1740,6 +1740,11 @@ static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
}
+static u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
+{
+ return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
+}
+
static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
{
msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
--
2.41.0
On Tue, Aug 8, 2023 at 2:02 PM Konrad Dybcio <[email protected]> wrote:
>
> This series attempts to introduce Adreno 700 support (with A730 and A740
> found on SM8450 and SM8550 respectively), reusing much of the existing
> A6xx code. This submission largely lays the groundwork for expansion and
> more or less gives us feature parity (on the kernel side, that is) with
> existing A6xx parts.
>
> On top of introducing a very messy set of three (!) separate and
> obfuscated deivce identifiers for each 7xx part, this generation
> introduces very sophisticated hardware multi-threading and (on some SKUs)
> hardware ray-tracing (not supported yet).
tbf most of this para above is describing choices kgsl made, and not
really relevant upstream.. really the only thing that matters for the
upstream kernel is that chip-id becomes "just a number" ;-)
If you want to mention why we align chip-id with kgsl, it is (a) mesa
needs to deal with both upstream and kgsl, and (b) future things we'll
read this from hw/fw
BR,
-R
> After this series, a long-overdue cleanup of drm/msm/adreno is planned
> in preparation for adding more features and removing some hardcoding.
>
> The last patch is a hack that may or may not be necessary depending
> on your board's humour.. eh.. :/
>
> Developed atop (and hence depends on) [1]
>
> The corresponding devicetree patches are initially available at [2] and
> will be posted after this series gets merged. To test it, you'll also need
> firmware that you need to obtain from your board (there's none with a
> redistributable license, sorry..). Most likely it will be in one of
> these directories on your stock android installation:
>
> * /vendor/firmware
> * /vendor/firmware_mnt
> * /system
>
> ..but some vendors make it hard and you have to do some grepping ;)
>
> Requires [3] to work on the userspace side. You'll almost cerainly want
> to test it alongside Zink with a lot of debug flags (early impl), like:
>
> TU_DEBUG=sysmem,nolrz,flushall,noubwc MESA_LOADER_DRIVER_OVERRIDE=zink kmscube
>
> [1] https://lore.kernel.org/linux-arm-msm/[email protected]/
> [2] https://github.com/SoMainline/linux/commits/topic/a7xx_dt
> [3] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217
>
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> Changes in v2:
> - Rebase on chipid changes
> - Reuse existing description for qcom,aoss in patch 2
> - Pick up tags
> - Link to v1: https://lore.kernel.org/r/[email protected]
>
> ---
> Konrad Dybcio (14):
> dt-bindings: display/msm/gmu: Add Adreno 7[34]0 GMU
> dt-bindings: display/msm/gmu: Allow passing QMP handle
> dt-bindings: display/msm/gpu: Allow A7xx SKUs
> drm/msm/a6xx: Add missing regs for A7XX
> drm/msm/a6xx: Introduce a6xx_llc_read
> drm/msm/a6xx: Move LLC accessors to the common header
> drm/msm/a6xx: Bail out early if setting GPU OOB fails
> drm/msm/a6xx: Add skeleton A7xx support
> drm/msm/a6xx: Send ACD state to QMP at GMU resume
> drm/msm/a6xx: Mostly implement A7xx gpu_state
> drm/msm/a6xx: Add A730 support
> drm/msm/a6xx: Add A740 support
> drm/msm/a6xx: Vastly increase HFI timeout
> drm/msm/a6xx: Poll for GBIF unhalt status in hw_init
>
> .../devicetree/bindings/display/msm/gmu.yaml | 47 +-
> .../devicetree/bindings/display/msm/gpu.yaml | 4 +-
> drivers/gpu/drm/msm/adreno/a6xx.xml.h | 9 +
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 204 +++++--
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +
> drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h | 8 +
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 667 ++++++++++++++++++---
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 15 +
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 52 +-
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 61 +-
> drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 90 ++-
> drivers/gpu/drm/msm/adreno/adreno_device.c | 30 +
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 7 +-
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 28 +-
> drivers/gpu/drm/msm/msm_ringbuffer.h | 2 +
> 15 files changed, 1094 insertions(+), 133 deletions(-)
> ---
> base-commit: b30de2c05cf2166f4e2c68850efc8dcea1c89780
> change-id: 20230628-topic-a7xx_drmmsm-123f30d76cf7
>
> Best regards,
> --
> Konrad Dybcio <[email protected]>
>