Hi Anand,
On Mon, May 3, 2021 at 5:29 PM Anand Moon <[email protected]> wrote:
[...]
> > > +static struct meson_ee_pwrc_mem_domain meson_pwrc_mem_hdmi[] = {
> > > + { HHI_MEM_PD_REG0, GENMASK(15, 8) },
> > > +};
> > > +
> > the VPU power domain already includes:
> > VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
> > whereas VPU_HHI_MEMPD is bits[15:8]
> >
> > Having two power domains which are managing the same registers sounds
> > like it'll be causing some trouble
> > So for now this is (as I am not even sure what the goal here is):
> > NACKed-by: Martin Blumenstingl <[email protected]>
> >
>
> Ok, thanks. On the line of Ethernet PD, I tried to add this accordingly.
From what I understand the VPU power domain is special because the
display pipeline consists of multiple components (HDMI, VPU, ...)
that's why the handling currently is special
> whenever I try something new it fails. Please ignore this series.
if the VPU and HDMI power domains were separate (from hardware
perspective, not from driver perspective) then your change is a good
step forward.
in that case VPU_HHI_MEMPD would need to be removed from wherever it's
currently used -> that means we need to also decide if we want to
break compatibility with older (before this series) .dtbs
Best regards,
Martin
hi Martin
On Mon, 3 May 2021 at 21:05, Martin Blumenstingl
<[email protected]> wrote:
>
> Hi Anand,
>
> On Mon, May 3, 2021 at 5:29 PM Anand Moon <[email protected]> wrote:
> [...]
> > > > +static struct meson_ee_pwrc_mem_domain meson_pwrc_mem_hdmi[] = {
> > > > + { HHI_MEM_PD_REG0, GENMASK(15, 8) },
> > > > +};
> > > > +
> > > the VPU power domain already includes:
> > > VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
> > > whereas VPU_HHI_MEMPD is bits[15:8]
> > >
> > > Having two power domains which are managing the same registers sounds
> > > like it'll be causing some trouble
> > > So for now this is (as I am not even sure what the goal here is):
> > > NACKed-by: Martin Blumenstingl <[email protected]>
> > >
> >
> > Ok, thanks. On the line of Ethernet PD, I tried to add this accordingly.
> From what I understand the VPU power domain is special because the
> display pipeline consists of multiple components (HDMI, VPU, ...)
> that's why the handling currently is special
>
> > whenever I try something new it fails. Please ignore this series.
> if the VPU and HDMI power domains were separate (from hardware
> perspective, not from driver perspective) then your change is a good
> step forward.
> in that case VPU_HHI_MEMPD would need to be removed from wherever it's
> currently used -> that means we need to also decide if we want to
> break compatibility with older (before this series) .dtbs
>
>
As per the datasheet S922X Datasheet, HDMI and VPU are different
reg controller and they are independent of each other.
*HHI_MEM_PD_REG0 0x40*
17~16 R/W 0x3 DDR memory PD
*15~8 R/W 0xFF HDMI memory PD*
7~6 R/W 0x3 Reserved
5~4 R/W 0x3 Audio mem PD
3~2 R/W 0x3 Ethernet memory PD
1~0 R/W 0x3 resved
Note: HDMI and AUDIO and Ethernet are also independent of each other.
*HHI_VPU_MEM_PD_REG0 0x41 *
31~30 R/W 0x3 sharp
29~28 R/W 0x3 Deinterlacer – di_post: 11 = power down. 00 = normal operation
27~26 R/W 0x3 Deinterlacer – di_pre 25~24 R/W 0x3 Vi_di_scaler
23~22 R/W 0x3 afbc_dec1
21~20 R/W 0x3 Srscl super scaler
19~18 R/W 0x3 Vdin1 memory
17~16 R/W 0x3 Vdin0 memory
15~14 R/W 0x3 Osd_scaler memory
13~12 R/W 0x3 Scaler memory
11~10 R/W 0x3 Vpp output fifo
9~8 R/W 0x3 Color management module
7~6 R/W 0x3 Vd2 memory
5~4 R/W 0x3 Vd1 memory
3~2 R/W 0x3 Osd2 memory
1~0 R/W 0x3 Osd1 memory
Below is the output on Odroid N2.
[alarm@archl-on2 ~]$ sudo cat /sys/kernel/debug/pm_genpd/pm_genpd_summary
domain status children
performance
/device runtime status
----------------------------------------------------------------------------------------------
HDMI on
0
/devices/platform/soc/ff600000.bus/ff600000.hdmi-tx unsupported
0
AUDIO on
0
/devices/platform/sound unsupported
0
ETH on
0
/devices/platform/soc/ff3f0000.ethernet active
0
VPU on
0
/devices/platform/soc/ff900000.vpu unsupported
0
HDMI power domain is ON.
Audio is wrongly mapped.
> Best regards,
> Martin
-Anand