This series applies on top of my other fix "pwm: meson: fix scheduling
while atomic issue" from [0]
The first patch fixes an issue where the maximum possible pre-divider
(128) could not be used because there was an off-by-one error in the
code. I discovered this while testing with the longest supported period
(349514407ns) when running from XTAL. This is verified to work on my
Meson8b Odroid-C1 board using "pwm_b" on GPIOX_11.
The second patch was suggested by Uwe Kleine-König but was actually
implemented much earlier (back in mid 2018) by Bichao Zheng from
Amlogic. This patch fixes changing the duty cycle by relying on the
hardware to re-start the PWM output (instead of adding an artificial
"constant LOW" of about 20ms - as measured by Bichao Zheng when
stopping and re-starting the PWM output from within the driver). I
tested this fix on my Meson8b Odroid-C1 board which uses a PWM driven
CPU regulator (DVFS with all supported OPPs is still working fine for
me, although I couldn't observe any issues before this patch).
I also have some code-improvements queued which I'll send in the next
days, see [1]
[0] https://patchwork.kernel.org/cover/10880419/
[1] https://github.com/xdarklight/linux/commits/meson-pwm-for-5.2-v1
Bichao Zheng (1):
pwm: meson: don't disable pwm when setting duty repeatedly
Martin Blumenstingl (1):
pwm: meson: consider 128 a valid pre-divider
drivers/pwm/pwm-meson.c | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
--
2.21.0
The pre-divider allows configuring longer PWM periods compared to using
the input clock directly. The pre-divider is 7 bit wide, meaning it's
maximum value is 128 (the register value is off-by-one: 0x7f or 127).
Change the loop to also allow for the maximum possible value to be
considered valid.
Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller")
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/pwm/pwm-meson.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index f6e738ad7bd9..4b708c1fcb1d 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -188,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
do_div(fin_ps, fin_freq);
/* Calc pre_div with the period */
- for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
+ for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
fin_ps * (pre_div + 1));
dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
@@ -197,7 +197,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
break;
}
- if (pre_div == MISC_CLK_DIV_MASK) {
+ if (pre_div > MISC_CLK_DIV_MASK) {
dev_err(meson->chip.dev, "unable to get period pre_div\n");
return -EINVAL;
}
--
2.21.0
From: Bichao Zheng <[email protected]>
There is an abnormally low about 20ms,when setting duty repeatedly.
Because setting the duty will disable pwm and then enable. Delete
this operation now.
Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller")
Signed-off-by: Bichao Zheng <[email protected]>
[ Dropped code instead of hiding it behind a comment ]
Signed-off-by: Martin Blumenstingl <[email protected]>
---
drivers/pwm/pwm-meson.c | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 4b708c1fcb1d..e247ab632530 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -325,11 +325,6 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
if (state->period != channel->state.period ||
state->duty_cycle != channel->state.duty_cycle ||
state->polarity != channel->state.polarity) {
- if (channel->state.enabled) {
- meson_pwm_disable(meson, pwm->hwpwm);
- channel->state.enabled = false;
- }
-
if (state->polarity != channel->state.polarity) {
if (state->polarity == PWM_POLARITY_NORMAL)
meson->inverter_mask |= BIT(pwm->hwpwm);
--
2.21.0
Hello Martin,
On Mon, Apr 01, 2019 at 08:18:16PM +0200, Martin Blumenstingl wrote:
> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> index f6e738ad7bd9..4b708c1fcb1d 100644
> --- a/drivers/pwm/pwm-meson.c
> +++ b/drivers/pwm/pwm-meson.c
> @@ -188,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
> do_div(fin_ps, fin_freq);
>
> /* Calc pre_div with the period */
> - for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
> + for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
> cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
> fin_ps * (pre_div + 1));
> dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
You could even calculate pre_div without the loop.
Something like:
u64 pre_div = (u64)period * rate;
do_div_round_up(pre_div, NSEC_PER_SEC * 0xffff);
pre_div--;
(I didn't check rounding and maybe its off by one and ...) This would
also get rid of the strange 1000 that is currently used in the
calculation without a real benefit (unless I missed something).
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Hello Uwe,
On Mon, Apr 1, 2019 at 8:38 PM Uwe Kleine-König
<[email protected]> wrote:
>
> Hello Martin,
>
> On Mon, Apr 01, 2019 at 08:18:16PM +0200, Martin Blumenstingl wrote:
> > diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> > index f6e738ad7bd9..4b708c1fcb1d 100644
> > --- a/drivers/pwm/pwm-meson.c
> > +++ b/drivers/pwm/pwm-meson.c
> > @@ -188,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
> > do_div(fin_ps, fin_freq);
> >
> > /* Calc pre_div with the period */
> > - for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
> > + for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
> > cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
> > fin_ps * (pre_div + 1));
> > dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
>
> You could even calculate pre_div without the loop.
>
> Something like:
>
> u64 pre_div = (u64)period * rate;
> do_div_round_up(pre_div, NSEC_PER_SEC * 0xffff);
> pre_div--;
>
> (I didn't check rounding and maybe its off by one and ...) This would
> also get rid of the strange 1000 that is currently used in the
> calculation without a real benefit (unless I missed something).
personally I prefer using this simple patch applied first as it is
easy to review and (due to the Fixes tag) may get backported to stable
kernels.
I'm not saying I don't like your suggestion, I propose to postpone
implementing this cleanup. I need to have a closer look at the
calculation because three values are derived from the input clock rate
(pre_div, cnt, duty_cnt) and I don't want to mess up the cases that
are already working as of today.
Please let me know what you think.
Regards
Martin
On Tue, Apr 02, 2019 at 09:22:55PM +0200, Martin Blumenstingl wrote:
> Hello Uwe,
>
> On Mon, Apr 1, 2019 at 8:38 PM Uwe Kleine-K?nig
> <[email protected]> wrote:
> >
> > Hello Martin,
> >
> > On Mon, Apr 01, 2019 at 08:18:16PM +0200, Martin Blumenstingl wrote:
> > > diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> > > index f6e738ad7bd9..4b708c1fcb1d 100644
> > > --- a/drivers/pwm/pwm-meson.c
> > > +++ b/drivers/pwm/pwm-meson.c
> > > @@ -188,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
> > > do_div(fin_ps, fin_freq);
> > >
> > > /* Calc pre_div with the period */
> > > - for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
> > > + for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
> > > cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
> > > fin_ps * (pre_div + 1));
> > > dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
> >
> > You could even calculate pre_div without the loop.
> >
> > Something like:
> >
> > u64 pre_div = (u64)period * rate;
> > do_div_round_up(pre_div, NSEC_PER_SEC * 0xffff);
> > pre_div--;
> >
> > (I didn't check rounding and maybe its off by one and ...) This would
> > also get rid of the strange 1000 that is currently used in the
> > calculation without a real benefit (unless I missed something).
> personally I prefer using this simple patch applied first as it is
> easy to review and (due to the Fixes tag) may get backported to stable
> kernels.
> I'm not saying I don't like your suggestion, I propose to postpone
> implementing this cleanup. I need to have a closer look at the
> calculation because three values are derived from the input clock rate
> (pre_div, cnt, duty_cnt) and I don't want to mess up the cases that
> are already working as of today.
>
> Please let me know what you think.
That's also ok for me. In this case take my
Acked-by: Uwe Kleine-K?nig <[email protected]>
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
On 01/04/2019 20:18, Martin Blumenstingl wrote:
> From: Bichao Zheng <[email protected]>
>
> There is an abnormally low about 20ms,when setting duty repeatedly.
> Because setting the duty will disable pwm and then enable. Delete
> this operation now.
>
> Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller")
> Signed-off-by: Bichao Zheng <[email protected]>
> [ Dropped code instead of hiding it behind a comment ]
> Signed-off-by: Martin Blumenstingl <[email protected]>
> ---
> drivers/pwm/pwm-meson.c | 5 -----
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> index 4b708c1fcb1d..e247ab632530 100644
> --- a/drivers/pwm/pwm-meson.c
> +++ b/drivers/pwm/pwm-meson.c
> @@ -325,11 +325,6 @@ static int meson_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
> if (state->period != channel->state.period ||
> state->duty_cycle != channel->state.duty_cycle ||
> state->polarity != channel->state.polarity) {
> - if (channel->state.enabled) {
> - meson_pwm_disable(meson, pwm->hwpwm);
> - channel->state.enabled = false;
> - }
> -
> if (state->polarity != channel->state.polarity) {
> if (state->polarity == PWM_POLARITY_NORMAL)
> meson->inverter_mask |= BIT(pwm->hwpwm);
>
Reviewed-by: Neil Armstrong <[email protected]>
On 01/04/2019 20:18, Martin Blumenstingl wrote:
> The pre-divider allows configuring longer PWM periods compared to using
> the input clock directly. The pre-divider is 7 bit wide, meaning it's
> maximum value is 128 (the register value is off-by-one: 0x7f or 127).
>
> Change the loop to also allow for the maximum possible value to be
> considered valid.
>
> Fixes: 211ed630753d2f ("pwm: Add support for Meson PWM Controller")
> Signed-off-by: Martin Blumenstingl <[email protected]>
> ---
> drivers/pwm/pwm-meson.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
> index f6e738ad7bd9..4b708c1fcb1d 100644
> --- a/drivers/pwm/pwm-meson.c
> +++ b/drivers/pwm/pwm-meson.c
> @@ -188,7 +188,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
> do_div(fin_ps, fin_freq);
>
> /* Calc pre_div with the period */
> - for (pre_div = 0; pre_div < MISC_CLK_DIV_MASK; pre_div++) {
> + for (pre_div = 0; pre_div <= MISC_CLK_DIV_MASK; pre_div++) {
> cnt = DIV_ROUND_CLOSEST_ULL((u64)period * 1000,
> fin_ps * (pre_div + 1));
> dev_dbg(meson->chip.dev, "fin_ps=%llu pre_div=%u cnt=%u\n",
> @@ -197,7 +197,7 @@ static int meson_pwm_calc(struct meson_pwm *meson,
> break;
> }
>
> - if (pre_div == MISC_CLK_DIV_MASK) {
> + if (pre_div > MISC_CLK_DIV_MASK) {
> dev_err(meson->chip.dev, "unable to get period pre_div\n");
> return -EINVAL;
> }
>
Reviewed-by: Neil Armstrong <[email protected]>
On Mon, Apr 01, 2019 at 08:18:15PM +0200, Martin Blumenstingl wrote:
> This series applies on top of my other fix "pwm: meson: fix scheduling
> while atomic issue" from [0]
>
> The first patch fixes an issue where the maximum possible pre-divider
> (128) could not be used because there was an off-by-one error in the
> code. I discovered this while testing with the longest supported period
> (349514407ns) when running from XTAL. This is verified to work on my
> Meson8b Odroid-C1 board using "pwm_b" on GPIOX_11.
>
> The second patch was suggested by Uwe Kleine-König but was actually
> implemented much earlier (back in mid 2018) by Bichao Zheng from
> Amlogic. This patch fixes changing the duty cycle by relying on the
> hardware to re-start the PWM output (instead of adding an artificial
> "constant LOW" of about 20ms - as measured by Bichao Zheng when
> stopping and re-starting the PWM output from within the driver). I
> tested this fix on my Meson8b Odroid-C1 board which uses a PWM driven
> CPU regulator (DVFS with all supported OPPs is still working fine for
> me, although I couldn't observe any issues before this patch).
>
> I also have some code-improvements queued which I'll send in the next
> days, see [1]
>
>
> [0] https://patchwork.kernel.org/cover/10880419/
> [1] https://github.com/xdarklight/linux/commits/meson-pwm-for-5.2-v1
>
>
> Bichao Zheng (1):
> pwm: meson: don't disable pwm when setting duty repeatedly
>
> Martin Blumenstingl (1):
> pwm: meson: consider 128 a valid pre-divider
>
> drivers/pwm/pwm-meson.c | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
Both patches applied, thanks.
Thierry