Addressed patches from:
Arnd Bergmann: https://www.spinics.net/lists/arm-kernel/msg639250.html
https://www.spinics.net/lists/arm-kernel/msg639249.html
Modify the NPCM and NPCM7XX configuration and enable L2 cache in
the DT_MACHINE_START.
Tomer Maimon (2):
arm: npcm: modify configuration for the NPCM7xx BMC.
arm: npcm: Enable L2 Cache in NPCM7xx
arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
arch/arm/mach-npcm/Makefile | 4 +++-
arch/arm/mach-npcm/npcm7xx.c | 2 ++
3 files changed, 16 insertions(+), 30 deletions(-)
--
2.14.1
Modify configuration and MakeFile
for the Nuvoton NPCM and NPCM7xx BMC.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
arch/arm/mach-npcm/Makefile | 4 +++-
2 files changed, 14 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
index 6ff9df2636be..684c9c9a32bd 100644
--- a/arch/arm/mach-npcm/Kconfig
+++ b/arch/arm/mach-npcm/Kconfig
@@ -1,48 +1,30 @@
menuconfig ARCH_NPCM
bool "Nuvoton NPCM Architecture"
- select ARCH_REQUIRE_GPIOLIB
- select USE_OF
+ depends on ARCH_MULTI_V7
select PINCTRL
- select PINCTRL_NPCM7XX
if ARCH_NPCM
-comment "NPCM7XX CPU type"
-
-config ARCH_NPCM750
- depends on ARCH_NPCM && ARCH_MULTI_V7
- bool "Support for NPCM750 BMC CPU (Poleg)"
+config ARCH_NPCM7XX
+ bool "Support for NPCM7xx BMC (Poleg)"
+ depends on ARCH_MULTI_V7
+ select PINCTRL_NPCM7XX
+ select NPCM7XX_TIMER
+ select ARCH_REQUIRE_GPIOLIB
select CACHE_L2X0
- select CPU_V7
select ARM_GIC
- select HAVE_SMP
- select SMP
- select SMP_ON_UP
- select HAVE_ARM_SCU
select HAVE_ARM_TWD if SMP
+ select HAVE_ARM_SCU if SMP
+ select ARM_ERRATA_764369 if SMP
select ARM_ERRATA_720789
select ARM_ERRATA_754322
- select ARM_ERRATA_764369
select ARM_ERRATA_794072
select PL310_ERRATA_588369
select PL310_ERRATA_727915
- select USB_EHCI_ROOT_HUB_TT
- select USB_ARCH_HAS_HCD
- select USB_ARCH_HAS_EHCI
- select USB_EHCI_HCD
- select USB_ARCH_HAS_OHCI
- select USB_OHCI_HCD
- select USB
- select FIQ
- select CPU_USE_DOMAINS
- select GENERIC_CLOCKEVENTS
- select CLKDEV_LOOKUP
- select COMMON_CLK if OF
- select NPCM750_TIMER
select MFD_SYSCON
help
- Support for NPCM750 BMC CPU (Poleg).
+ General support for NPCM7xx BMC (Poleg).
- Nuvoton NPCM750 BMC based on the Cortex A9.
+ Nuvoton NPCM7xx BMC based on the Cortex A9.
endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
index c7a1316d27c1..0839e8926a84 100644
--- a/arch/arm/mach-npcm/Makefile
+++ b/arch/arm/mach-npcm/Makefile
@@ -1,3 +1,5 @@
AFLAGS_headsmp.o += -march=armv7-a
-obj-$(CONFIG_ARCH_NPCM750) += npcm7xx.o platsmp.o headsmp.o
+obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
+
--
2.14.1
Enable L2 Cache in Nuvoton NPCM7xx BMC.
Signed-off-by: Tomer Maimon <[email protected]>
---
arch/arm/mach-npcm/npcm7xx.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
index 5f7cd88103ef..c5f77d854c4f 100644
--- a/arch/arm/mach-npcm/npcm7xx.c
+++ b/arch/arm/mach-npcm/npcm7xx.c
@@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
.atag_offset = 0x100,
.dt_compat = npcm7xx_dt_match,
+ .l2c_aux_val = 0x0,
+ .l2c_aux_mask = ~0x0,
MACHINE_END
--
2.14.1
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <[email protected]> wrote:
> Enable L2 Cache in Nuvoton NPCM7xx BMC.
> Signed-off-by: Tomer Maimon <[email protected]>
> ---
> arch/arm/mach-npcm/npcm7xx.c | 2 ++
> 1 file changed, 2 insertions(+)
> diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
> index 5f7cd88103ef..c5f77d854c4f 100644
> --- a/arch/arm/mach-npcm/npcm7xx.c
> +++ b/arch/arm/mach-npcm/npcm7xx.c
> @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
> DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
> .atag_offset = 0x100,
> .dt_compat = npcm7xx_dt_match,
> + .l2c_aux_val = 0x0,
> + .l2c_aux_mask = ~0x0,
You need to limit this to the specific bit(s) you want to set and verify
that
the l2c driver does not already manage that bit appropriately and that it
can
not be specified via the dtsi.
We discussed this a little while ago with Rob here:
https://www.spinics.net/lists/arm-kernel/msg613372.html
> MACHINE_END
> --
> 2.14.1
Cheers
On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <[email protected]> wrote:
> Modify configuration and MakeFile
> for the Nuvoton NPCM and NPCM7xx BMC.
> Signed-off-by: Tomer Maimon <[email protected]>
> ---
> arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
> arch/arm/mach-npcm/Makefile | 4 +++-
> 2 files changed, 14 insertions(+), 30 deletions(-)
<snip>
Reviewed-by: Brendan Higgins <[email protected]>
On Fri, Mar 16, 2018 at 6:56 AM, Brendan Higgins
<[email protected]> wrote:
> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <[email protected]> wrote:
>
>> Modify configuration and MakeFile
>> for the Nuvoton NPCM and NPCM7xx BMC.
>
>> Signed-off-by: Tomer Maimon <[email protected]>
>> ---
>> arch/arm/mach-npcm/Kconfig | 40 +++++++++++-----------------------------
>> arch/arm/mach-npcm/Makefile | 4 +++-
>> 2 files changed, 14 insertions(+), 30 deletions(-)
>
> <snip>
>
> Reviewed-by: Brendan Higgins <[email protected]>
Sorry for missing this earlier, I did ask for the rework but then
didn't see it as it
wasn't in my [email protected] inbox.
Tomer, please make sure that all patches you want to have included in
the kernel are sent to that address, while patches you want to have reviewed
are not sent to it.
Normally I don't apply patches during the merge window, but this one fixes
some build problems, so I've decided to take it.
Arnd
On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <[email protected]> wrote:
>
>
> On 16 March 2018 at 07:52, Brendan Higgins <[email protected]>
> wrote:
>>
>> On Thu, Mar 15, 2018 at 4:16 PM Tomer Maimon <[email protected]> wrote:
>>
>> > Enable L2 Cache in Nuvoton NPCM7xx BMC.
>>
>> > Signed-off-by: Tomer Maimon <[email protected]>
>> > ---
>> > arch/arm/mach-npcm/npcm7xx.c | 2 ++
>> > 1 file changed, 2 insertions(+)
>>
>> > diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c
>> > index 5f7cd88103ef..c5f77d854c4f 100644
>> > --- a/arch/arm/mach-npcm/npcm7xx.c
>> > +++ b/arch/arm/mach-npcm/npcm7xx.c
>> > @@ -17,4 +17,6 @@ static const char *const npcm7xx_dt_match[] = {
>> > DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family")
>> > .atag_offset = 0x100,
>> > .dt_compat = npcm7xx_dt_match,
>> > + .l2c_aux_val = 0x0,
>> > + .l2c_aux_mask = ~0x0,
>>
>> You need to limit this to the specific bit(s) you want to set and verify
>> that
>> the l2c driver does not already manage that bit appropriately and that it
>> can
>> not be specified via the dtsi.
>
>
> Do you mean that I need to specify it the same as been done in V7?
> because when I run with the above l2c_aux_val and l2c_aux_mask parameters I
> get the same result.
>
> Also if I am not adding the l2c_aux_val and l2c_aux_mask parameters to the
> DT_MACHINE_START
> the L2C cache does not initialize.
>>
>>
>> We discussed this a little while ago with Rob here:
>> https://www.spinics.net/lists/arm-kernel/msg613372.html
>
>
> Sorry in this link I see only Russel king comment regarding the L2C
I'm not sure what the outcome is, and the patch changelog doesn't
explain what the patch is for, so I've not applied it. If you need the
patch for correct operation, please resend it with a proper changelog
comment explaining why it's needed and why you ended up not setting
any of the bits.
The last email in that thread mentions
L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
Arnd
On Thu, Apr 5, 2018 at 6:56 PM, Tomer Maimon <[email protected]> wrote:
> On 5 April 2018 at 15:54, Arnd Bergmann <[email protected]> wrote:
>> On Fri, Mar 16, 2018 at 10:51 PM, Tomer Maimon <[email protected]> wrote:
>
> It seems that I have to add l2c_aux_val, l2c_aux_mask parameters to the
> DT_MACHINE_START
> to enable the L2 Cache.
>>
>>
>> The last email in that thread mentions
>> L310_AUX_CTRL_CACHE_REPLACE_RR, is that required after all?
>
>
> No it is not require this is why I added:
> .l2c_aux_val = 0x0,
> .l2c_aux_mask = ~0x0,
>
> Can I resend it on Sunday?
Yes, please resend it as soon as you have the time to improve the changelog,
no need to wait if you can do it right away. We can always merge bugfixes,
but doing it earlier rather than later is better.
Arnd