Based on 'next' branch of Kishon's phy tree (linux-phy).
Tested on 'usb-next' of Greg's usb tree.
Changes from v4:
1) Separated out the device tree related arch patches from this patch series.
Shall be posting these below mentioned patches (which were part of
V4 version of this series) in a separate patch series based on
Kgene's next branch.
[PATCH v4 2/5]dt: exynos5420: Enable support for USB 3.0 PHY controller
[PATCH v4 3/5]dt: exynos5420: Enable support for DWC3 controller
[PATCH v4 4/5]dt: exynos5250: Enable support for generic USB DRD phy
[PATCH v4 5/5]usb-phy: samsung-usb3: Remove older phy-samsung-usb3 driver
2) Also clubbed the reworked VBUS patch for usb3-drd phy, which was earlier
sent as a separate patch:
[PATCH] phy: exynos5-usbdrd: Add facility to toggle vbus gpio on/off.
https://lkml.org/lkml/2014/4/9/186
1) Removed the mention of separate sclk_usbphy30*, instead this clock
will be used as 'ref' phy reference clock while adding the device
nodes.
2) Reading the PHYCLKRST register to restore any previous settings,
instead of using a separate variable for saving/restoring purpose.
3) Renamed 'samsung,syscon-phandle' property to 'samsung,pmu-syscon'.
4) Removed unnecessary check for of_node property at the starting of
driver probe, since this is exclusively DT enabled driver.
Changes from V3:
1) Separated out the phy init sequences for utmi and pipe3 phys.
2) Changed the nomenclature across the phy to 'usbdrd-phy' to
indicate USB 3.0 DRD PHY controller; and thereby changed the names
of functions correspondingly, including specific functions for
utmi and pipe3 phys.
3) Modified the DT nodes for the updated nomenclature.
4) Using BIT macro for single bit definitions.
5) Keeping track of reference clock after getting till the removal of
phy, and getting the ref clock using devm_clk_get() api.
6) Removed aliases for mutiple channel PHYs, and instead using
'samsung,pmu-offset' property for PHY power control register offset.
7) Keeping the phy_init() and phy_power_on() separately in order to
align with phy handling in the consumer (DWC3).
Changes from v2:
1) Added support for multiple PHYs (UTMI+ and PIPE3) and
related changes in the driver structuring.
2) Added a xlate function to get the required phy out of
number of PHYs in mutiple PHY scenerio.
3) Changed the names of few structures and variables to
have a clearer meaning.
4) Added 'usb3phy_config' structure to take care of mutiple
phys for a SoC having 'exynos5_usb3phy_drv_data' driver data.
5) Not deleting support for old driver 'phy-samsung-usb3' until
required support for generic phy is added to DWC3.
Changes from RFC patch-set:
1) fixes in documentation file
- added provision for syscon interface for using PMU register.
- added clock names and description
- modified description style for 'compatible property'
- made usb30_sclk as additional clock rather then making it optional, since
it is actually an additional clock for Exynos5420 Soc.
2) fixes in phy-exynos5-usb3 driver file
- removed unnecessary #ifndef around KHZ and MHZ definitions
- removed 'samsung_cpu_type', 'usb3phy_state' enums; and merged necessary
necessary from 'usb3phy_instance' structure to 'usb3phy_driver'.
- changed name 'sclk_usbphy30' to 'usb30_sclk_100m' since this is the name
indicated as input to the PHY block; and also added (!IS_ERR()) check for
using usb30_sclk.
- removed unnecessary 'state' check code.
- moved 'of_device_id' structure definitions before 'probe()' to avoid
unnecessary declaration.
- added (pdev->dev.of_node == NULL) check at the starting of probe()
- moved 'devm_of_phy_provider_register()' call to end of the probe().
- removed 'label' for usb3drd phy.
- corrected macros definition 'PHYCLKRST_MPLL_MULTIPLIER_50M_REF' from
0x02 to 0x32 after confirming same from PHY's data sheet.
- replaced pmu register handling, used for power-isolation, with syscon
interface api's.
- added '.init' and '.exit' callbacks and using them for one time
PHY-initialization and deinitialization.
- Filtering out the PHY 'power-on' and 'power-off' sequence to '.power_on"
and ".power_off" callbacks.
- Removed drivers/usb/phy/phy-samsung-usb3.c driver and related code.
3) fixes in dt files
- added reference for 'samsung,syscon-phandle' to used for PMU register.
- removed second register field which was earlier used for PMU.
Vivek Gautam (2):
phy: Add new Exynos5 USB 3.0 PHY driver
phy: exynos5-usbdrd: Add facility for VBUS supply
.../devicetree/bindings/phy/samsung-phy.txt | 40 ++
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-exynos5-usbdrd.c | 663 ++++++++++++++++++++
4 files changed, 715 insertions(+)
create mode 100644 drivers/phy/phy-exynos5-usbdrd.c
--
1.7.10.4
Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
The new driver uses the generic PHY framework and will interact
with DWC3 controller present on Exynos5 series of SoCs.
Thereby, removing old phy-samsung-usb3 driver and related code
used untill now which was based on usb/phy framework.
Signed-off-by: Vivek Gautam <[email protected]>
---
.../devicetree/bindings/phy/samsung-phy.txt | 40 ++
drivers/phy/Kconfig | 11 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-exynos5-usbdrd.c | 629 ++++++++++++++++++++
4 files changed, 681 insertions(+)
create mode 100644 drivers/phy/phy-exynos5-usbdrd.c
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index b422e38..51efe4c 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -114,3 +114,43 @@ Example:
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
+
+Samsung Exynos5 SoC series USB DRD PHY controller
+--------------------------------------------------
+
+Required properties:
+- compatible : Should be set to one of the following supported values:
+ - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
+ - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
+- reg : Register offset and length of USB DRD PHY register set;
+- clocks: Clock IDs array as required by the controller
+- clock-names: names of clocks correseponding to IDs in the clock property;
+ Required clocks:
+ - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
+ used for register access.
+ - ref: PHY's reference clock (usually crystal clock), used for
+ PHY operations, associated by phy name. It is used to
+ determine bit values for clock settings register.
+ For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
+- samsung,pmu-syscon: phandle for PMU system controller interface, used to
+ control pmu registers for power isolation.
+- samsung,pmu-offset: phy power control register offset to pmu-system-controller
+ base.
+- #phy-cells : from the generic PHY bindings, must be 1;
+
+For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
+compatible PHYs, the second cell in the PHY specifier identifies the
+PHY id, which is interpreted as follows:
+ 0 - UTMI+ type phy,
+ 1 - PIPE3 type phy,
+
+Example:
+ usb3_phy: usbphy@12100000 {
+ compatible = "samsung,exynos5250-usbdrd-phy";
+ reg = <0x12100000 0x100>;
+ clocks = <&clock 286>, <&clock 1>;
+ clock-names = "phy", "ref";
+ samsung,pmu-syscon = <&pmu_system_controller>;
+ samsung,pmu-offset = <0x704>;
+ #phy-cells = <1>;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 3bb05f1..8a5d2b4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -166,4 +166,15 @@ config PHY_XGENE
help
This option enables support for APM X-Gene SoC multi-purpose PHY.
+config PHY_EXYNOS5_USBDRD
+ tristate "Exynos5 SoC series USB DRD PHY driver"
+ depends on ARCH_EXYNOS5 && OF
+ depends on HAS_IOMEM
+ select GENERIC_PHY
+ select MFD_SYSCON
+ help
+ Enable USB DRD PHY support for Exynos 5 SoC series.
+ This driver provides PHY interface for USB 3.0 DRD controller
+ present on Exynos5 SoC series.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 2faf78e..31baa0c 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
+obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
new file mode 100644
index 0000000..89d7ae8
--- /dev/null
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -0,0 +1,629 @@
+/*
+ * Samsung EXYNOS5 SoC series USB DRD PHY driver
+ *
+ * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
+ *
+ * Copyright (C) 2014 Samsung Electronics Co., Ltd.
+ * Author: Vivek Gautam <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+
+/* Exynos USB PHY registers */
+#define EXYNOS5_FSEL_9MHZ6 0x0
+#define EXYNOS5_FSEL_10MHZ 0x1
+#define EXYNOS5_FSEL_12MHZ 0x2
+#define EXYNOS5_FSEL_19MHZ2 0x3
+#define EXYNOS5_FSEL_20MHZ 0x4
+#define EXYNOS5_FSEL_24MHZ 0x5
+#define EXYNOS5_FSEL_50MHZ 0x7
+
+/* EXYNOS5: USB 3.0 DRD PHY registers */
+#define EXYNOS5_DRD_LINKSYSTEM 0x04
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
+
+#define EXYNOS5_DRD_PHYUTMI 0x08
+
+#define PHYUTMI_OTGDISABLE BIT(6)
+#define PHYUTMI_FORCESUSPEND BIT(1)
+#define PHYUTMI_FORCESLEEP BIT(0)
+
+#define EXYNOS5_DRD_PHYPIPE 0x0c
+
+#define EXYNOS5_DRD_PHYCLKRST 0x10
+
+#define PHYCLKRST_EN_UTMISUSPEND BIT(31)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN BIT(20)
+#define PHYCLKRST_REF_SSP_EN BIT(19)
+#define PHYCLKRST_REF_CLKDIV2 BIT(18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
+#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN BIT(4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET BIT(1)
+#define PHYCLKRST_COMMONONN BIT(0)
+
+#define EXYNOS5_DRD_PHYREG0 0x14
+#define EXYNOS5_DRD_PHYREG1 0x18
+
+#define EXYNOS5_DRD_PHYPARAM0 0x1c
+
+#define PHYPARAM0_REF_USE_PAD BIT(31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define EXYNOS5_DRD_PHYPARAM1 0x20
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define EXYNOS5_DRD_PHYTERM 0x24
+
+#define EXYNOS5_DRD_PHYTEST 0x28
+
+#define PHYTEST_POWERDOWN_SSP BIT(3)
+#define PHYTEST_POWERDOWN_HSP BIT(2)
+
+#define EXYNOS5_DRD_PHYADP 0x2c
+
+#define EXYNOS5_DRD_PHYUTMICLKSEL 0x30
+
+#define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2)
+
+#define EXYNOS5_DRD_PHYRESUME 0x34
+#define EXYNOS5_DRD_LINKPORT 0x44
+
+/* Power isolation defined in power management unit */
+#define EXYNOS5_USBDRD_PMU_ISOL BIT(0)
+
+#define KHZ 1000
+#define MHZ (KHZ * KHZ)
+
+enum exynos5_usbdrd_phy_id {
+ EXYNOS5_DRDPHY_UTMI,
+ EXYNOS5_DRDPHY_PIPE3,
+ EXYNOS5_DRDPHYS_NUM,
+};
+
+struct phy_usb_instance;
+struct exynos5_usbdrd_phy;
+
+struct usbdrd_phy_config {
+ u32 id;
+ void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
+ void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
+ unsigned int (*set_refclk)(struct phy_usb_instance *inst);
+};
+
+struct exynos5_usbdrd_phy_drvdata {
+ bool has_usb30_sclk;
+ const struct usbdrd_phy_config *phy_cfg;
+};
+
+/**
+ * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
+ * @dev: pointer to device instance of this platform device
+ * @reg_phy: usb phy controller register memory base
+ * @clk: phy clock for register access
+ * @drv_data: pointer to SoC level driver data structure
+ * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
+ * instances each with its 'phy' and 'phy_cfg'.
+ * @extrefclk: frequency select settings when using 'separate
+ * reference clocks' for SS and HS operations
+ * @ref_clk: reference clock to PHY block from which PHY's
+ * operational clocks are derived
+ * @ref_rate: rate of above reference clock
+ */
+struct exynos5_usbdrd_phy {
+ struct device *dev;
+ void __iomem *reg_phy;
+ struct clk *clk;
+ const struct exynos5_usbdrd_phy_drvdata *drv_data;
+ struct phy_usb_instance {
+ struct phy *phy;
+ u32 index;
+ struct regmap *reg_pmu;
+ u32 pmu_offset;
+ const struct usbdrd_phy_config *phy_cfg;
+ } phys[EXYNOS5_DRDPHYS_NUM];
+ unsigned int extrefclk;
+ struct clk *ref_clk;
+ unsigned long ref_rate;
+};
+
+#define to_usbdrd_phy(inst) \
+ container_of((inst), struct exynos5_usbdrd_phy, \
+ phys[(inst)->index]);
+
+/*
+ * exynos5_rate_to_clk() converts the supplied clock rate to the value that
+ * can be written to the phy register.
+ */
+static unsigned int exynos5_rate_to_clk(unsigned long rate)
+{
+ unsigned int clksel;
+
+ /* EXYNOS5_FSEL_MASK */
+
+ switch (rate) {
+ case 9600 * KHZ:
+ clksel = EXYNOS5_FSEL_9MHZ6;
+ break;
+ case 10 * MHZ:
+ clksel = EXYNOS5_FSEL_10MHZ;
+ break;
+ case 12 * MHZ:
+ clksel = EXYNOS5_FSEL_12MHZ;
+ break;
+ case 19200 * KHZ:
+ clksel = EXYNOS5_FSEL_19MHZ2;
+ break;
+ case 20 * MHZ:
+ clksel = EXYNOS5_FSEL_20MHZ;
+ break;
+ case 24 * MHZ:
+ clksel = EXYNOS5_FSEL_24MHZ;
+ break;
+ case 50 * MHZ:
+ clksel = EXYNOS5_FSEL_50MHZ;
+ break;
+ default:
+ clksel = -EINVAL;
+ }
+
+ return clksel;
+}
+
+static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
+ unsigned int on)
+{
+ if (!inst->reg_pmu)
+ return;
+
+ regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
+ EXYNOS5_USBDRD_PMU_ISOL, ~on);
+}
+
+/*
+ * Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock
+ * from clock core. Further sets multiplier values and spread spectrum
+ * clock settings for SuperSpeed operations.
+ */
+static unsigned int
+exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
+{
+ static u32 reg;
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+
+ /* restore any previous reference clock settings */
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
+
+ /* Use EXTREFCLK as ref clock */
+ reg &= ~PHYCLKRST_REFCLKSEL_MASK;
+ reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
+
+ /* FSEL settings corresponding to reference clock */
+ reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
+ PHYCLKRST_MPLL_MULTIPLIER_MASK |
+ PHYCLKRST_SSC_REFCLKSEL_MASK;
+ switch (phy_drd->extrefclk) {
+ case EXYNOS5_FSEL_50MHZ:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case EXYNOS5_FSEL_24MHZ:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ case EXYNOS5_FSEL_20MHZ:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x00));
+ break;
+ case EXYNOS5_FSEL_19MHZ2:
+ reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
+ PHYCLKRST_SSC_REFCLKSEL(0x88));
+ break;
+ default:
+ dev_dbg(phy_drd->dev, "unsupported ref clk\n");
+ break;
+ }
+
+ return reg;
+}
+
+/*
+ * Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock
+ * from clock core. Further sets the FSEL values for HighSpeed operations.
+ */
+static unsigned int
+exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
+{
+ static u32 reg;
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+
+ /* restore any previous reference clock settings */
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
+
+ reg &= ~PHYCLKRST_REFCLKSEL_MASK;
+ reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
+
+ reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
+ PHYCLKRST_MPLL_MULTIPLIER_MASK |
+ PHYCLKRST_SSC_REFCLKSEL_MASK;
+ reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
+
+ return reg;
+}
+
+static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
+{
+ u32 reg;
+
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
+ /* Set Tx De-Emphasis level */
+ reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
+ reg |= PHYPARAM1_PCS_TXDEEMPH;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
+
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
+ reg &= ~PHYTEST_POWERDOWN_SSP;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
+}
+
+static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
+{
+ u32 reg;
+
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
+ /* Set Loss-of-Signal Detector sensitivity */
+ reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
+ reg |= PHYPARAM0_REF_LOSLEVEL;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
+
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
+ /* Set Tx De-Emphasis level */
+ reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
+ reg |= PHYPARAM1_PCS_TXDEEMPH;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
+
+ /* UTMI Power Control */
+ writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
+
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
+ reg &= ~PHYTEST_POWERDOWN_HSP;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
+}
+
+static int exynos5_usbdrd_phy_init(struct phy *phy)
+{
+ int ret;
+ u32 reg;
+ struct phy_usb_instance *inst = phy_get_drvdata(phy);
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+
+ ret = clk_prepare_enable(phy_drd->clk);
+ if (ret)
+ return ret;
+
+ phy_drd->extrefclk = exynos5_rate_to_clk(phy_drd->ref_rate);
+ if (phy_drd->extrefclk == -EINVAL) {
+ dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
+ phy_drd->ref_rate);
+ return -EINVAL;
+ }
+
+ /* Reset USB 3.0 PHY */
+ writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
+ writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
+
+ /*
+ * Setting the Frame length Adj value[6:1] to default 0x20
+ * See xHCI 1.0 spec, 5.2.4
+ */
+ reg = LINKSYSTEM_XHCI_VERSION_CONTROL |
+ LINKSYSTEM_FLADJ(0x20);
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
+
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
+ /* Select PHY CLK source */
+ reg &= ~PHYPARAM0_REF_USE_PAD;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
+
+ /* This bit must be set for both HS and SS operations */
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
+ reg |= PHYUTMICLKSEL_UTMI_CLKSEL;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
+
+ /* UTMI or PIPE3 specific init */
+ inst->phy_cfg->phy_init(phy_drd);
+
+ /* reference clock settings */
+ reg = inst->phy_cfg->set_refclk(inst);
+
+ /* Digital power supply in normal operating mode */
+ reg |= PHYCLKRST_RETENABLEN |
+ /* Enable ref clock for SS function */
+ PHYCLKRST_REF_SSP_EN |
+ /* Enable spread spectrum */
+ PHYCLKRST_SSC_EN |
+ /* Power down HS Bias and PLL blocks in suspend mode */
+ PHYCLKRST_COMMONONN |
+ /* Reset the port */
+ PHYCLKRST_PORTRESET;
+
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
+
+ udelay(10);
+
+ reg &= ~PHYCLKRST_PORTRESET;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
+
+ clk_disable_unprepare(phy_drd->clk);
+
+ return 0;
+}
+
+static int exynos5_usbdrd_phy_exit(struct phy *phy)
+{
+ int ret;
+ u32 reg;
+ struct phy_usb_instance *inst = phy_get_drvdata(phy);
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+
+ ret = clk_prepare_enable(phy_drd->clk);
+ if (ret)
+ return ret;
+
+ reg = PHYUTMI_OTGDISABLE |
+ PHYUTMI_FORCESUSPEND |
+ PHYUTMI_FORCESLEEP;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
+
+ /* Resetting the PHYCLKRST enable bits to reduce leakage current */
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
+ reg &= ~(PHYCLKRST_REF_SSP_EN |
+ PHYCLKRST_SSC_EN |
+ PHYCLKRST_COMMONONN);
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
+
+ /* Control PHYTEST to remove leakage current */
+ reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
+ reg |= PHYTEST_POWERDOWN_SSP |
+ PHYTEST_POWERDOWN_HSP;
+ writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
+
+ clk_disable_unprepare(phy_drd->clk);
+
+ return 0;
+}
+
+static int exynos5_usbdrd_phy_power_on(struct phy *phy)
+{
+ struct phy_usb_instance *inst = phy_get_drvdata(phy);
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+
+ dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
+
+ clk_prepare_enable(phy_drd->ref_clk);
+
+ /* Power-on PHY*/
+ inst->phy_cfg->phy_isol(inst, 0);
+
+ return 0;
+}
+
+static int exynos5_usbdrd_phy_power_off(struct phy *phy)
+{
+ struct phy_usb_instance *inst = phy_get_drvdata(phy);
+ struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
+
+ dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
+
+ /* Power-off the PHY */
+ inst->phy_cfg->phy_isol(inst, 1);
+
+ clk_disable_unprepare(phy_drd->ref_clk);
+
+ return 0;
+}
+
+static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
+
+ if (WARN_ON(args->args[0] > EXYNOS5_DRDPHYS_NUM))
+ return ERR_PTR(-ENODEV);
+
+ return phy_drd->phys[args->args[0]].phy;
+}
+
+static struct phy_ops exynos5_usbdrd_phy_ops = {
+ .init = exynos5_usbdrd_phy_init,
+ .exit = exynos5_usbdrd_phy_exit,
+ .power_on = exynos5_usbdrd_phy_power_on,
+ .power_off = exynos5_usbdrd_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+const struct usbdrd_phy_config exynos5_usbdrd_phy_cfg[] = {
+ {
+ .id = EXYNOS5_DRDPHY_UTMI,
+ .phy_isol = exynos5_usbdrd_phy_isol,
+ .phy_init = exynos5_usbdrd_utmi_init,
+ .set_refclk = exynos5_usbdrd_utmi_set_refclk,
+ },
+ {
+ .id = EXYNOS5_DRDPHY_PIPE3,
+ .phy_isol = exynos5_usbdrd_phy_isol,
+ .phy_init = exynos5_usbdrd_pipe3_init,
+ .set_refclk = exynos5_usbdrd_pipe3_set_refclk,
+ },
+ {},
+};
+
+const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
+ .has_usb30_sclk = true,
+ .phy_cfg = exynos5_usbdrd_phy_cfg,
+};
+
+const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
+ .has_usb30_sclk = false,
+ .phy_cfg = exynos5_usbdrd_phy_cfg,
+};
+
+static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
+ {
+ .compatible = "samsung,exynos5250-usbdrd-phy",
+ .data = &exynos5250_usbdrd_phy
+ }, {
+ .compatible = "samsung,exynos5420-usbdrd-phy",
+ .data = &exynos5420_usbdrd_phy
+ },
+ { },
+};
+
+static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct exynos5_usbdrd_phy *phy_drd;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ const struct of_device_id *match;
+ const struct exynos5_usbdrd_phy_drvdata *drv_data;
+ struct regmap *reg_pmu;
+ u32 pmu_offset;
+ int i;
+
+ phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
+ if (!phy_drd)
+ return -ENOMEM;
+
+ dev_set_drvdata(dev, phy_drd);
+ phy_drd->dev = dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ phy_drd->reg_phy = devm_ioremap_resource(dev, res);
+ if (IS_ERR(phy_drd->reg_phy))
+ return PTR_ERR(phy_drd->reg_phy);
+
+ match = of_match_node(exynos5_usbdrd_phy_of_match, pdev->dev.of_node);
+ if (!match) {
+ dev_err(dev, "of_match_node() failed\n");
+ return -EINVAL;
+ }
+ drv_data = match->data;
+
+ phy_drd->drv_data = drv_data;
+
+ phy_drd->clk = devm_clk_get(dev, "phy");
+ if (IS_ERR(phy_drd->clk)) {
+ dev_err(dev, "Failed to get clock of phy controller\n");
+ return PTR_ERR(phy_drd->clk);
+ }
+
+ phy_drd->ref_clk = devm_clk_get(dev, "ref");
+ if (IS_ERR(phy_drd->ref_clk)) {
+ dev_err(dev, "Failed to get reference clock of usbdrd_phy phy\n");
+ return PTR_ERR(phy_drd->ref_clk);
+ }
+ phy_drd->ref_rate = clk_get_rate(phy_drd->ref_clk);
+
+ reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node,
+ "samsung,pmu-syscon");
+ if (IS_ERR(reg_pmu)) {
+ dev_err(dev, "Failed to map PMU register (via syscon)\n");
+ return PTR_ERR(reg_pmu);
+ }
+
+ if (of_property_read_u32(node, "samsung,pmu-offset", &pmu_offset)) {
+ dev_err(dev, "Missing pmu-offset for phy isolation\n");
+ return -EINVAL;
+ }
+
+ dev_vdbg(dev, "Creating usbdrd_phy phy\n");
+
+ for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) {
+ struct phy *phy = devm_phy_create(dev, &exynos5_usbdrd_phy_ops,
+ NULL);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "Failed to create usbdrd_phy phy\n");
+ return PTR_ERR(phy);
+ }
+
+ phy_drd->phys[i].phy = phy;
+ phy_drd->phys[i].index = i;
+ phy_drd->phys[i].reg_pmu = reg_pmu;
+ phy_drd->phys[i].pmu_offset = pmu_offset;
+ phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
+ phy_set_drvdata(phy, &phy_drd->phys[i]);
+ }
+
+ phy_provider = devm_of_phy_provider_register(dev,
+ exynos5_usbdrd_phy_xlate);
+ if (IS_ERR(phy_provider)) {
+ dev_err(phy_drd->dev, "Failed to register phy provider\n");
+ return PTR_ERR(phy_provider);
+ }
+
+ return 0;
+}
+
+static struct platform_driver exynos5_usb3drd_phy = {
+ .probe = exynos5_usbdrd_phy_probe,
+ .driver = {
+ .of_match_table = exynos5_usbdrd_phy_of_match,
+ .name = "exynos5_usb3drd_phy",
+ .owner = THIS_MODULE,
+ }
+};
+
+module_platform_driver(exynos5_usb3drd_phy);
+MODULE_DESCRIPTION("Samsung EXYNOS5 SoCs USB 3.0 DRD controller PHY driver");
+MODULE_AUTHOR("Vivek Gautam <[email protected]>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:exynos5_usb3drd_phy");
--
1.7.10.4
Adding support to enable/disable VBUS controlled by a
regulator, to enable vbus supply on the port.
Signed-off-by: Vivek Gautam <[email protected]>
---
This is v2 version of patch:
[PATCH] phy: exynos5-usbdrd: Add facility to toggle vbus gpio on/off
https://lkml.org/lkml/2014/4/9/186
Changes from v1:
- Using regulator APIs instead of gpio to control VBUS.
drivers/phy/phy-exynos5-usbdrd.c | 36 +++++++++++++++++++++++++++++++++++-
1 file changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
index 89d7ae8..d7e3745 100644
--- a/drivers/phy/phy-exynos5-usbdrd.c
+++ b/drivers/phy/phy-exynos5-usbdrd.c
@@ -23,6 +23,7 @@
#include <linux/mutex.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
/* Exynos USB PHY registers */
#define EXYNOS5_FSEL_9MHZ6 0x0
@@ -172,6 +173,7 @@ struct exynos5_usbdrd_phy {
unsigned int extrefclk;
struct clk *ref_clk;
unsigned long ref_rate;
+ struct regulator *vbus;
};
#define to_usbdrd_phy(inst) \
@@ -442,6 +444,7 @@ static int exynos5_usbdrd_phy_exit(struct phy *phy)
static int exynos5_usbdrd_phy_power_on(struct phy *phy)
{
+ int ret;
struct phy_usb_instance *inst = phy_get_drvdata(phy);
struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
@@ -449,10 +452,26 @@ static int exynos5_usbdrd_phy_power_on(struct phy *phy)
clk_prepare_enable(phy_drd->ref_clk);
+ /* Enable VBUS supply */
+ if (phy_drd->vbus) {
+ ret = regulator_enable(phy_drd->vbus);
+ if (ret) {
+ dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
+ goto fail_vbus;
+ }
+ }
+
/* Power-on PHY*/
inst->phy_cfg->phy_isol(inst, 0);
return 0;
+
+fail_vbus:
+ clk_disable_unprepare(phy_drd->ref_clk);
+ if (!IS_ERR(phy_drd->usb30_sclk))
+ clk_disable_unprepare(phy_drd->usb30_sclk);
+
+ return ret;
}
static int exynos5_usbdrd_phy_power_off(struct phy *phy)
@@ -465,6 +484,10 @@ static int exynos5_usbdrd_phy_power_off(struct phy *phy)
/* Power-off the PHY */
inst->phy_cfg->phy_isol(inst, 1);
+ /* Disable VBUS supply */
+ if (phy_drd->vbus)
+ regulator_disable(phy_drd->vbus);
+
clk_disable_unprepare(phy_drd->ref_clk);
return 0;
@@ -537,7 +560,7 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
const struct exynos5_usbdrd_phy_drvdata *drv_data;
struct regmap *reg_pmu;
u32 pmu_offset;
- int i;
+ int i, ret;
phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
if (!phy_drd)
@@ -580,6 +603,17 @@ static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
return PTR_ERR(reg_pmu);
}
+ /* Get required GPIO for vbus */
+ phy_drd->vbus = devm_regulator_get(dev, "vbus");
+ if (IS_ERR(phy_drd->vbus)) {
+ ret = PTR_ERR(phy_drd->vbus);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+
+ dev_warn(dev, "Failed to get VBUS supply regulator\n");
+ phy_drd->vbus = NULL;
+ }
+
if (of_property_read_u32(node, "samsung,pmu-offset", &pmu_offset)) {
dev_err(dev, "Missing pmu-offset for phy isolation\n");
return -EINVAL;
--
1.7.10.4
Hi Vivek,
On 22.04.2014 10:03, Vivek Gautam wrote:
> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
> The new driver uses the generic PHY framework and will interact
> with DWC3 controller present on Exynos5 series of SoCs.
> Thereby, removing old phy-samsung-usb3 driver and related code
> used untill now which was based on usb/phy framework.
>
> Signed-off-by: Vivek Gautam <[email protected]>
> ---
> .../devicetree/bindings/phy/samsung-phy.txt | 40 ++
> drivers/phy/Kconfig | 11 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-exynos5-usbdrd.c | 629 ++++++++++++++++++++
> 4 files changed, 681 insertions(+)
> create mode 100644 drivers/phy/phy-exynos5-usbdrd.c
>
> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
> index b422e38..51efe4c 100644
> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
> @@ -114,3 +114,43 @@ Example:
> compatible = "samsung,exynos-sataphy-i2c";
> reg = <0x38>;
> };
> +
> +Samsung Exynos5 SoC series USB DRD PHY controller
> +--------------------------------------------------
> +
> +Required properties:
> +- compatible : Should be set to one of the following supported values:
> + - "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
> + - "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
> +- reg : Register offset and length of USB DRD PHY register set;
> +- clocks: Clock IDs array as required by the controller
> +- clock-names: names of clocks correseponding to IDs in the clock property;
> + Required clocks:
> + - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
> + used for register access.
> + - ref: PHY's reference clock (usually crystal clock), used for
> + PHY operations, associated by phy name. It is used to
> + determine bit values for clock settings register.
> + For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
> +- samsung,pmu-syscon: phandle for PMU system controller interface, used to
> + control pmu registers for power isolation.
> +- samsung,pmu-offset: phy power control register offset to pmu-system-controller
> + base.
> +- #phy-cells : from the generic PHY bindings, must be 1;
> +
> +For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
> +compatible PHYs, the second cell in the PHY specifier identifies the
> +PHY id, which is interpreted as follows:
> + 0 - UTMI+ type phy,
> + 1 - PIPE3 type phy,
> +
> +Example:
> + usb3_phy: usbphy@12100000 {
> + compatible = "samsung,exynos5250-usbdrd-phy";
> + reg = <0x12100000 0x100>;
> + clocks = <&clock 286>, <&clock 1>;
> + clock-names = "phy", "ref";
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + samsung,pmu-offset = <0x704>;
> + #phy-cells = <1>;
> + };
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 3bb05f1..8a5d2b4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -166,4 +166,15 @@ config PHY_XGENE
> help
> This option enables support for APM X-Gene SoC multi-purpose PHY.
>
> +config PHY_EXYNOS5_USBDRD
> + tristate "Exynos5 SoC series USB DRD PHY driver"
> + depends on ARCH_EXYNOS5 && OF
> + depends on HAS_IOMEM
> + select GENERIC_PHY
> + select MFD_SYSCON
> + help
> + Enable USB DRD PHY support for Exynos 5 SoC series.
> + This driver provides PHY interface for USB 3.0 DRD controller
> + present on Exynos5 SoC series.
> +
I think you should probably keep the entries sorted, so this one should
be somewhere around other EXYNOS PHYs.
> endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 2faf78e..31baa0c 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -18,3 +18,4 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
> +obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
Ditto.
> diff --git a/drivers/phy/phy-exynos5-usbdrd.c b/drivers/phy/phy-exynos5-usbdrd.c
> new file mode 100644
> index 0000000..89d7ae8
> --- /dev/null
> +++ b/drivers/phy/phy-exynos5-usbdrd.c
> @@ -0,0 +1,629 @@
> +/*
> + * Samsung EXYNOS5 SoC series USB DRD PHY driver
> + *
> + * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
> + *
> + * Copyright (C) 2014 Samsung Electronics Co., Ltd.
> + * Author: Vivek Gautam <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/mutex.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
> +
> +/* Exynos USB PHY registers */
> +#define EXYNOS5_FSEL_9MHZ6 0x0
> +#define EXYNOS5_FSEL_10MHZ 0x1
> +#define EXYNOS5_FSEL_12MHZ 0x2
> +#define EXYNOS5_FSEL_19MHZ2 0x3
> +#define EXYNOS5_FSEL_20MHZ 0x4
> +#define EXYNOS5_FSEL_24MHZ 0x5
> +#define EXYNOS5_FSEL_50MHZ 0x7
> +
> +/* EXYNOS5: USB 3.0 DRD PHY registers */
> +#define EXYNOS5_DRD_LINKSYSTEM 0x04
> +
> +#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
> +#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
> +#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27)
> +
> +#define EXYNOS5_DRD_PHYUTMI 0x08
> +
> +#define PHYUTMI_OTGDISABLE BIT(6)
> +#define PHYUTMI_FORCESUSPEND BIT(1)
> +#define PHYUTMI_FORCESLEEP BIT(0)
> +
> +#define EXYNOS5_DRD_PHYPIPE 0x0c
> +
> +#define EXYNOS5_DRD_PHYCLKRST 0x10
> +
> +#define PHYCLKRST_EN_UTMISUSPEND BIT(31)
> +
> +#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
> +#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
> +
> +#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
> +#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
> +
> +#define PHYCLKRST_SSC_EN BIT(20)
> +#define PHYCLKRST_REF_SSP_EN BIT(19)
> +#define PHYCLKRST_REF_CLKDIV2 BIT(18)
> +
> +#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x32 << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
> +#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
> +
> +#define PHYCLKRST_FSEL_UTMI_MASK (0x7 << 5)
> +#define PHYCLKRST_FSEL_PIPE_MASK (0x7 << 8)
> +#define PHYCLKRST_FSEL(_x) ((_x) << 5)
> +#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
> +#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
> +#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
> +#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
> +
> +#define PHYCLKRST_RETENABLEN BIT(4)
> +
> +#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
> +#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
> +#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
> +
> +#define PHYCLKRST_PORTRESET BIT(1)
> +#define PHYCLKRST_COMMONONN BIT(0)
> +
> +#define EXYNOS5_DRD_PHYREG0 0x14
> +#define EXYNOS5_DRD_PHYREG1 0x18
> +
> +#define EXYNOS5_DRD_PHYPARAM0 0x1c
> +
> +#define PHYPARAM0_REF_USE_PAD BIT(31)
> +#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
> +#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
> +
> +#define EXYNOS5_DRD_PHYPARAM1 0x20
> +
> +#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
> +#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
> +
> +#define EXYNOS5_DRD_PHYTERM 0x24
> +
> +#define EXYNOS5_DRD_PHYTEST 0x28
> +
> +#define PHYTEST_POWERDOWN_SSP BIT(3)
> +#define PHYTEST_POWERDOWN_HSP BIT(2)
> +
> +#define EXYNOS5_DRD_PHYADP 0x2c
> +
> +#define EXYNOS5_DRD_PHYUTMICLKSEL 0x30
> +
> +#define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2)
> +
> +#define EXYNOS5_DRD_PHYRESUME 0x34
> +#define EXYNOS5_DRD_LINKPORT 0x44
> +
> +/* Power isolation defined in power management unit */
> +#define EXYNOS5_USBDRD_PMU_ISOL BIT(0)
> +
> +#define KHZ 1000
> +#define MHZ (KHZ * KHZ)
> +
> +enum exynos5_usbdrd_phy_id {
> + EXYNOS5_DRDPHY_UTMI,
> + EXYNOS5_DRDPHY_PIPE3,
> + EXYNOS5_DRDPHYS_NUM,
> +};
> +
> +struct phy_usb_instance;
> +struct exynos5_usbdrd_phy;
> +
> +struct usbdrd_phy_config {
> + u32 id;
> + void (*phy_isol)(struct phy_usb_instance *inst, u32 on);
> + void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
> + unsigned int (*set_refclk)(struct phy_usb_instance *inst);
> +};
> +
> +struct exynos5_usbdrd_phy_drvdata {
> + bool has_usb30_sclk;
> + const struct usbdrd_phy_config *phy_cfg;
> +};
> +
> +/**
> + * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY
> + * @dev: pointer to device instance of this platform device
> + * @reg_phy: usb phy controller register memory base
> + * @clk: phy clock for register access
> + * @drv_data: pointer to SoC level driver data structure
> + * @phys[]: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY
> + * instances each with its 'phy' and 'phy_cfg'.
> + * @extrefclk: frequency select settings when using 'separate
> + * reference clocks' for SS and HS operations
> + * @ref_clk: reference clock to PHY block from which PHY's
> + * operational clocks are derived
> + * @ref_rate: rate of above reference clock
> + */
> +struct exynos5_usbdrd_phy {
> + struct device *dev;
> + void __iomem *reg_phy;
> + struct clk *clk;
> + const struct exynos5_usbdrd_phy_drvdata *drv_data;
> + struct phy_usb_instance {
> + struct phy *phy;
> + u32 index;
> + struct regmap *reg_pmu;
> + u32 pmu_offset;
> + const struct usbdrd_phy_config *phy_cfg;
> + } phys[EXYNOS5_DRDPHYS_NUM];
> + unsigned int extrefclk;
> + struct clk *ref_clk;
> + unsigned long ref_rate;
> +};
> +
> +#define to_usbdrd_phy(inst) \
> + container_of((inst), struct exynos5_usbdrd_phy, \
> + phys[(inst)->index]);
This should be made a static inline to enforce type checking.
> +
> +/*
> + * exynos5_rate_to_clk() converts the supplied clock rate to the value that
> + * can be written to the phy register.
> + */
> +static unsigned int exynos5_rate_to_clk(unsigned long rate)
> +{
> + unsigned int clksel;
> +
> + /* EXYNOS5_FSEL_MASK */
> +
> + switch (rate) {
> + case 9600 * KHZ:
> + clksel = EXYNOS5_FSEL_9MHZ6;
> + break;
> + case 10 * MHZ:
> + clksel = EXYNOS5_FSEL_10MHZ;
> + break;
> + case 12 * MHZ:
> + clksel = EXYNOS5_FSEL_12MHZ;
> + break;
> + case 19200 * KHZ:
> + clksel = EXYNOS5_FSEL_19MHZ2;
> + break;
> + case 20 * MHZ:
> + clksel = EXYNOS5_FSEL_20MHZ;
> + break;
> + case 24 * MHZ:
> + clksel = EXYNOS5_FSEL_24MHZ;
> + break;
> + case 50 * MHZ:
> + clksel = EXYNOS5_FSEL_50MHZ;
> + break;
> + default:
> + clksel = -EINVAL;
Based on clksel (and return value of this function) being unsigned I
don't think this is a good idea. You should probably adapt the approach
from Exynos USB 2 PHY, where a function like this return an integer
status code and returns the bitfield value through a pointer passed as
another argument.
> + }
> +
> + return clksel;
> +}
> +
> +static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
> + unsigned int on)
> +{
> + if (!inst->reg_pmu)
> + return;
> +
> + regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
> + EXYNOS5_USBDRD_PMU_ISOL, ~on);
I don't think ~on is correct here. Even if technically it produces the
correct value, because bit 0 is being changed here, this should be
fixed. If EXYNOS5_USBDRD_PMU_ISOL wasn't BIT(0), then always 1 would be
written, as on could be 0 or 1 and ~on respectively 0xffffffff or
0xfffffffe.
I'd suggest something like this:
unsigned int val = on ? 0 : EXYNOS5_USBDRD_PMU_ISOL;
> +}
> +
> +/*
> + * Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock
> + * from clock core. Further sets multiplier values and spread spectrum
> + * clock settings for SuperSpeed operations.
> + */
> +static unsigned int
> +exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst)
> +{
> + static u32 reg;
> + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> +
> + /* restore any previous reference clock settings */
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
> +
> + /* Use EXTREFCLK as ref clock */
> + reg &= ~PHYCLKRST_REFCLKSEL_MASK;
> + reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
> +
> + /* FSEL settings corresponding to reference clock */
> + reg &= ~PHYCLKRST_FSEL_PIPE_MASK |
> + PHYCLKRST_MPLL_MULTIPLIER_MASK |
> + PHYCLKRST_SSC_REFCLKSEL_MASK;
> + switch (phy_drd->extrefclk) {
> + case EXYNOS5_FSEL_50MHZ:
> + reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x00));
> + break;
> + case EXYNOS5_FSEL_24MHZ:
> + reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x88));
> + break;
> + case EXYNOS5_FSEL_20MHZ:
> + reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x00));
> + break;
> + case EXYNOS5_FSEL_19MHZ2:
> + reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF |
> + PHYCLKRST_SSC_REFCLKSEL(0x88));
> + break;
> + default:
> + dev_dbg(phy_drd->dev, "unsupported ref clk\n");
> + break;
> + }
> +
> + return reg;
> +}
> +
> +/*
> + * Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock
> + * from clock core. Further sets the FSEL values for HighSpeed operations.
> + */
> +static unsigned int
> +exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst)
> +{
> + static u32 reg;
> + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> +
> + /* restore any previous reference clock settings */
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
> +
> + reg &= ~PHYCLKRST_REFCLKSEL_MASK;
> + reg |= PHYCLKRST_REFCLKSEL_EXT_REFCLK;
> +
> + reg &= ~PHYCLKRST_FSEL_UTMI_MASK |
> + PHYCLKRST_MPLL_MULTIPLIER_MASK |
> + PHYCLKRST_SSC_REFCLKSEL_MASK;
> + reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
> +
> + return reg;
> +}
> +
> +static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
> +{
> + u32 reg;
> +
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
> + /* Set Tx De-Emphasis level */
> + reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
> + reg |= PHYPARAM1_PCS_TXDEEMPH;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
> +
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
> + reg &= ~PHYTEST_POWERDOWN_SSP;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
> +}
> +
> +static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
> +{
> + u32 reg;
> +
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
> + /* Set Loss-of-Signal Detector sensitivity */
> + reg &= ~PHYPARAM0_REF_LOSLEVEL_MASK;
> + reg |= PHYPARAM0_REF_LOSLEVEL;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
> +
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
> + /* Set Tx De-Emphasis level */
> + reg &= ~PHYPARAM1_PCS_TXDEEMPH_MASK;
> + reg |= PHYPARAM1_PCS_TXDEEMPH;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
> +
> + /* UTMI Power Control */
> + writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
> +
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
> + reg &= ~PHYTEST_POWERDOWN_HSP;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
> +}
> +
> +static int exynos5_usbdrd_phy_init(struct phy *phy)
> +{
> + int ret;
> + u32 reg;
> + struct phy_usb_instance *inst = phy_get_drvdata(phy);
> + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> +
> + ret = clk_prepare_enable(phy_drd->clk);
> + if (ret)
> + return ret;
> +
> + phy_drd->extrefclk = exynos5_rate_to_clk(phy_drd->ref_rate);
> + if (phy_drd->extrefclk == -EINVAL) {
> + dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
> + phy_drd->ref_rate);
> + return -EINVAL;
> + }
> +
> + /* Reset USB 3.0 PHY */
> + writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
> + writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
> +
> + /*
> + * Setting the Frame length Adj value[6:1] to default 0x20
> + * See xHCI 1.0 spec, 5.2.4
> + */
> + reg = LINKSYSTEM_XHCI_VERSION_CONTROL |
> + LINKSYSTEM_FLADJ(0x20);
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
> +
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
> + /* Select PHY CLK source */
> + reg &= ~PHYPARAM0_REF_USE_PAD;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
> +
> + /* This bit must be set for both HS and SS operations */
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
> + reg |= PHYUTMICLKSEL_UTMI_CLKSEL;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
> +
> + /* UTMI or PIPE3 specific init */
> + inst->phy_cfg->phy_init(phy_drd);
> +
> + /* reference clock settings */
> + reg = inst->phy_cfg->set_refclk(inst);
> +
> + /* Digital power supply in normal operating mode */
> + reg |= PHYCLKRST_RETENABLEN |
> + /* Enable ref clock for SS function */
> + PHYCLKRST_REF_SSP_EN |
> + /* Enable spread spectrum */
> + PHYCLKRST_SSC_EN |
> + /* Power down HS Bias and PLL blocks in suspend mode */
> + PHYCLKRST_COMMONONN |
> + /* Reset the port */
> + PHYCLKRST_PORTRESET;
> +
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
> +
> + udelay(10);
> +
> + reg &= ~PHYCLKRST_PORTRESET;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
> +
> + clk_disable_unprepare(phy_drd->clk);
> +
> + return 0;
> +}
> +
> +static int exynos5_usbdrd_phy_exit(struct phy *phy)
> +{
> + int ret;
> + u32 reg;
> + struct phy_usb_instance *inst = phy_get_drvdata(phy);
> + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> +
> + ret = clk_prepare_enable(phy_drd->clk);
> + if (ret)
> + return ret;
> +
> + reg = PHYUTMI_OTGDISABLE |
> + PHYUTMI_FORCESUSPEND |
> + PHYUTMI_FORCESLEEP;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
> +
> + /* Resetting the PHYCLKRST enable bits to reduce leakage current */
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
> + reg &= ~(PHYCLKRST_REF_SSP_EN |
> + PHYCLKRST_SSC_EN |
> + PHYCLKRST_COMMONONN);
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
> +
> + /* Control PHYTEST to remove leakage current */
> + reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
> + reg |= PHYTEST_POWERDOWN_SSP |
> + PHYTEST_POWERDOWN_HSP;
> + writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
> +
> + clk_disable_unprepare(phy_drd->clk);
> +
> + return 0;
> +}
> +
> +static int exynos5_usbdrd_phy_power_on(struct phy *phy)
> +{
> + struct phy_usb_instance *inst = phy_get_drvdata(phy);
> + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> +
> + dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
> +
> + clk_prepare_enable(phy_drd->ref_clk);
> +
> + /* Power-on PHY*/
> + inst->phy_cfg->phy_isol(inst, 0);
> +
> + return 0;
> +}
> +
> +static int exynos5_usbdrd_phy_power_off(struct phy *phy)
> +{
> + struct phy_usb_instance *inst = phy_get_drvdata(phy);
> + struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
> +
> + dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
> +
> + /* Power-off the PHY */
> + inst->phy_cfg->phy_isol(inst, 1);
> +
> + clk_disable_unprepare(phy_drd->ref_clk);
> +
> + return 0;
> +}
> +
> +static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev,
> + struct of_phandle_args *args)
> +{
> + struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
> +
> + if (WARN_ON(args->args[0] > EXYNOS5_DRDPHYS_NUM))
> + return ERR_PTR(-ENODEV);
> +
> + return phy_drd->phys[args->args[0]].phy;
> +}
> +
> +static struct phy_ops exynos5_usbdrd_phy_ops = {
> + .init = exynos5_usbdrd_phy_init,
> + .exit = exynos5_usbdrd_phy_exit,
> + .power_on = exynos5_usbdrd_phy_power_on,
> + .power_off = exynos5_usbdrd_phy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
> +const struct usbdrd_phy_config exynos5_usbdrd_phy_cfg[] = {
> + {
> + .id = EXYNOS5_DRDPHY_UTMI,
> + .phy_isol = exynos5_usbdrd_phy_isol,
> + .phy_init = exynos5_usbdrd_utmi_init,
> + .set_refclk = exynos5_usbdrd_utmi_set_refclk,
> + },
> + {
> + .id = EXYNOS5_DRDPHY_PIPE3,
> + .phy_isol = exynos5_usbdrd_phy_isol,
> + .phy_init = exynos5_usbdrd_pipe3_init,
> + .set_refclk = exynos5_usbdrd_pipe3_set_refclk,
> + },
> + {},
You seem to use a fixed number of PHYs. Do you still need this sentinel
entry?
> +};
> +
> +const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = {
> + .has_usb30_sclk = true,
> + .phy_cfg = exynos5_usbdrd_phy_cfg,
> +};
> +
> +const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = {
> + .has_usb30_sclk = false,
> + .phy_cfg = exynos5_usbdrd_phy_cfg,
> +};
> +
> +static const struct of_device_id exynos5_usbdrd_phy_of_match[] = {
> + {
> + .compatible = "samsung,exynos5250-usbdrd-phy",
> + .data = &exynos5250_usbdrd_phy
> + }, {
> + .compatible = "samsung,exynos5420-usbdrd-phy",
> + .data = &exynos5420_usbdrd_phy
> + },
> + { },
> +};
> +
> +static int exynos5_usbdrd_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->of_node;
> + struct exynos5_usbdrd_phy *phy_drd;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + const struct of_device_id *match;
> + const struct exynos5_usbdrd_phy_drvdata *drv_data;
> + struct regmap *reg_pmu;
> + u32 pmu_offset;
> + int i;
> +
> + phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
> + if (!phy_drd)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, phy_drd);
> + phy_drd->dev = dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + phy_drd->reg_phy = devm_ioremap_resource(dev, res);
> + if (IS_ERR(phy_drd->reg_phy))
> + return PTR_ERR(phy_drd->reg_phy);
> +
> + match = of_match_node(exynos5_usbdrd_phy_of_match, pdev->dev.of_node);
> + if (!match) {
This can't happen, otherwise probe() wouldn't be called at all.
Best regards,
Tomasz
Hi Tomasz,
On Sat, Apr 26, 2014 at 4:33 AM, Tomasz Figa <[email protected]> wrote:
> Hi Vivek,
>
>
> On 22.04.2014 10:03, Vivek Gautam wrote:
>>
>> Add a new driver for the USB 3.0 PHY on Exynos5 series of SoCs.
>> The new driver uses the generic PHY framework and will interact
>> with DWC3 controller present on Exynos5 series of SoCs.
>> Thereby, removing old phy-samsung-usb3 driver and related code
>> used untill now which was based on usb/phy framework.
>>
>> Signed-off-by: Vivek Gautam <[email protected]>
>> ---
>> .../devicetree/bindings/phy/samsung-phy.txt | 40 ++
>> drivers/phy/Kconfig | 11 +
>> drivers/phy/Makefile | 1 +
>> drivers/phy/phy-exynos5-usbdrd.c | 629
>> ++++++++++++++++++++
>> 4 files changed, 681 insertions(+)
>> create mode 100644 drivers/phy/phy-exynos5-usbdrd.c
>>
>> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> index b422e38..51efe4c 100644
>> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> @@ -114,3 +114,43 @@ Example:
>> compatible = "samsung,exynos-sataphy-i2c";
>> reg = <0x38>;
>> };
>> +
>> +Samsung Exynos5 SoC series USB DRD PHY controller
[snip]
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index 3bb05f1..8a5d2b4 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -166,4 +166,15 @@ config PHY_XGENE
>> help
>> This option enables support for APM X-Gene SoC multi-purpose
>> PHY.
>>
>> +config PHY_EXYNOS5_USBDRD
>> + tristate "Exynos5 SoC series USB DRD PHY driver"
>> + depends on ARCH_EXYNOS5 && OF
>> + depends on HAS_IOMEM
>> + select GENERIC_PHY
>> + select MFD_SYSCON
>> + help
>> + Enable USB DRD PHY support for Exynos 5 SoC series.
>> + This driver provides PHY interface for USB 3.0 DRD controller
>> + present on Exynos5 SoC series.
>> +
>
>
> I think you should probably keep the entries sorted, so this one should be
> somewhere around other EXYNOS PHYs.
Right, thanks for pointing this out.
Will move this along with other PHY_EXYNOS USB* configs.
>
>
>> endmenu
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 2faf78e..31baa0c 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -18,3 +18,4 @@ obj-$(CONFIG_PHY_EXYNOS4210_USB2) +=
>> phy-exynos4210-usb2.o
>> obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
>> obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
>> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
>> +obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
>
>
> Ditto.
Ok
>
>
>> diff --git a/drivers/phy/phy-exynos5-usbdrd.c
>> b/drivers/phy/phy-exynos5-usbdrd.c
>> new file mode 100644
>> index 0000000..89d7ae8
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos5-usbdrd.c
>> @@ -0,0 +1,629 @@
>> +/*
>> + * Samsung EXYNOS5 SoC series USB DRD PHY driver
>> + *
>> + * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series
>> + *
>> + * Copyright (C) 2014 Samsung Electronics Co., Ltd.
>> + * Author: Vivek Gautam <[email protected]>
>> + *
[snip]
>> + } phys[EXYNOS5_DRDPHYS_NUM];
>> + unsigned int extrefclk;
>> + struct clk *ref_clk;
>> + unsigned long ref_rate;
>> +};
>> +
>> +#define to_usbdrd_phy(inst) \
>> + container_of((inst), struct exynos5_usbdrd_phy, \
>> + phys[(inst)->index]);
>
>
> This should be made a static inline to enforce type checking.
Ok, will make this as static inline routine, so that compiler don't
skip type checking.
>
>
>> +
>> +/*
>> + * exynos5_rate_to_clk() converts the supplied clock rate to the value
>> that
>> + * can be written to the phy register.
>> + */
>> +static unsigned int exynos5_rate_to_clk(unsigned long rate)
>> +{
>> + unsigned int clksel;
>> +
>> + /* EXYNOS5_FSEL_MASK */
>> +
>> + switch (rate) {
>> + case 9600 * KHZ:
>> + clksel = EXYNOS5_FSEL_9MHZ6;
>> + break;
>> + case 10 * MHZ:
>> + clksel = EXYNOS5_FSEL_10MHZ;
>> + break;
>> + case 12 * MHZ:
>> + clksel = EXYNOS5_FSEL_12MHZ;
>> + break;
>> + case 19200 * KHZ:
>> + clksel = EXYNOS5_FSEL_19MHZ2;
>> + break;
>> + case 20 * MHZ:
>> + clksel = EXYNOS5_FSEL_20MHZ;
>> + break;
>> + case 24 * MHZ:
>> + clksel = EXYNOS5_FSEL_24MHZ;
>> + break;
>> + case 50 * MHZ:
>> + clksel = EXYNOS5_FSEL_50MHZ;
>> + break;
>> + default:
>> + clksel = -EINVAL;
>
>
> Based on clksel (and return value of this function) being unsigned I don't
> think this is a good idea. You should probably adapt the approach from
> Exynos USB 2 PHY, where a function like this return an integer status code
> and returns the bitfield value through a pointer passed as another argument.
Right, will amend this as suggested.
>
>
>> + }
>> +
>> + return clksel;
>> +}
>> +
>> +static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst,
>> + unsigned int on)
>> +{
>> + if (!inst->reg_pmu)
>> + return;
>> +
>> + regmap_update_bits(inst->reg_pmu, inst->pmu_offset,
>> + EXYNOS5_USBDRD_PMU_ISOL, ~on);
>
>
> I don't think ~on is correct here. Even if technically it produces the
> correct value, because bit 0 is being changed here, this should be fixed. If
> EXYNOS5_USBDRD_PMU_ISOL wasn't BIT(0), then always 1 would be written, as on
> could be 0 or 1 and ~on respectively 0xffffffff or 0xfffffffe.
>
> I'd suggest something like this:
>
> unsigned int val = on ? 0 : EXYNOS5_USBDRD_PMU_ISOL;
Sure will change this as suggested.
[snip]
>> +const struct usbdrd_phy_config exynos5_usbdrd_phy_cfg[] = {
>> + {
>> + .id = EXYNOS5_DRDPHY_UTMI,
>> + .phy_isol = exynos5_usbdrd_phy_isol,
>> + .phy_init = exynos5_usbdrd_utmi_init,
>> + .set_refclk = exynos5_usbdrd_utmi_set_refclk,
>> + },
>> + {
>> + .id = EXYNOS5_DRDPHY_PIPE3,
>> + .phy_isol = exynos5_usbdrd_phy_isol,
>> + .phy_init = exynos5_usbdrd_pipe3_init,
>> + .set_refclk = exynos5_usbdrd_pipe3_set_refclk,
>> + },
>> + {},
>
>
> You seem to use a fixed number of PHYs. Do you still need this sentinel
> entry?
Right, we don't need this sentinel entry since we have limited the
number of PHYs to EXYNOS5_DRDPHYS_NUM.
Will remove this.
>
>
>> +};
[snip]
>> +
>> + match = of_match_node(exynos5_usbdrd_phy_of_match,
>> pdev->dev.of_node);
>> + if (!match) {
>
>
> This can't happen, otherwise probe() wouldn't be called at all.
True, will remove this check.
--
Best Regards
Vivek Gautam
Samsung R&D Institute, Bangalore
India