LinuxLists.cc - [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

2021-11-26 20:42:17

Subject: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

2021-11-26 20:42:43

Subject: [PATCH 2/2] clk: samsung: exynos850: Add missing sysreg clocks

System Register is used to configure system behavior, like USI protocol,
etc. SYSREG clocks should be provided to corresponding syscon nodes, to
make it possible to modify SYSREG registers.

While at it, add also missing PMU and GPIO clocks, which looks necessary
and might be needed for corresponding Exynos850 features soon.

Signed-off-by: Sam Protsenko <[email protected]>
---
drivers/clk/samsung/clk-exynos850.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index 5d83388d8c8e..b644bc3d0de1 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -426,11 +426,14 @@ CLK_OF_DECLARE(exynos850_cmu_top, "samsung,exynos850-cmu-top",
#define CLK_CON_DIV_DIV_CLK_APM_I3C 0x1808
#define CLK_CON_GAT_CLKCMU_CMGP_BUS 0x2000
#define CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS 0x2014
+#define CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK 0x2018
+#define CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK 0x2020
#define CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK 0x2024
#define CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK 0x2028
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK 0x2034
#define CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK 0x2038
#define CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK 0x20bc
+#define CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK 0x20c0

static const unsigned long apm_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_APM_BUS_USER,
@@ -445,11 +448,14 @@ static const unsigned long apm_clk_regs[] __initconst = {
CLK_CON_DIV_DIV_CLK_APM_I3C,
CLK_CON_GAT_CLKCMU_CMGP_BUS,
CLK_CON_GAT_GATE_CLKCMU_CHUB_BUS,
+ CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
+ CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
CLK_CON_GAT_GOUT_APM_APBIF_RTC_PCLK,
CLK_CON_GAT_GOUT_APM_APBIF_TOP_RTC_PCLK,
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_PCLK,
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK,
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK,
+ CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK,
};

/* List of parent clocks for Muxes in CMU_APM */
@@ -512,6 +518,14 @@ static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_APM_I3C_APM_PMIC_I_SCLK, 21, 0, 0),
GATE(CLK_GOUT_SPEEDY_PCLK, "gout_speedy_pclk", "dout_apm_bus",
CLK_CON_GAT_GOUT_APM_SPEEDY_APM_PCLK, 21, 0, 0),
+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
+ GATE(CLK_GOUT_GPIO_ALIVE_PCLK, "gout_gpio_alive_pclk", "dout_apm_bus",
+ CLK_CON_GAT_GOUT_APM_APBIF_GPIO_ALIVE_PCLK, 21, CLK_IGNORE_UNUSED,
+ 0),
+ GATE(CLK_GOUT_PMU_ALIVE_PCLK, "gout_pmu_alive_pclk", "dout_apm_bus",
+ CLK_CON_GAT_GOUT_APM_APBIF_PMU_ALIVE_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_SYSREG_APM_PCLK, "gout_sysreg_apm_pclk", "dout_apm_bus",
+ CLK_CON_GAT_GOUT_APM_SYSREG_APM_PCLK, 21, 0, 0),
};

static const struct samsung_cmu_info apm_cmu_info __initconst = {
@@ -541,6 +555,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0 0x200c
#define CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1 0x2010
#define CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK 0x2018
+#define CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK 0x2040
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK 0x2044
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK 0x2048
#define CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK 0x204c
@@ -556,6 +571,7 @@ static const unsigned long cmgp_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S0,
CLK_CON_GAT_GOUT_CMGP_ADC_PCLK_S1,
CLK_CON_GAT_GOUT_CMGP_GPIO_PCLK,
+ CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK,
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_IPCLK,
CLK_CON_GAT_GOUT_CMGP_USI_CMGP0_PCLK,
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_IPCLK,
@@ -610,6 +626,9 @@ static const struct samsung_gate_clock cmgp_gate_clks[] __initconst = {
GATE(CLK_GOUT_CMGP_USI1_PCLK, "gout_cmgp_usi1_pclk",
"gout_clkcmu_cmgp_bus",
CLK_CON_GAT_GOUT_CMGP_USI_CMGP1_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_SYSREG_CMGP_PCLK, "gout_sysreg_cmgp_pclk",
+ "gout_clkcmu_cmgp_bus",
+ CLK_CON_GAT_GOUT_CMGP_SYSREG_CMGP_PCLK, 21, 0, 0),
};

static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
@@ -910,10 +929,12 @@ CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
#define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
#define CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK 0x2038
#define CLK_CON_GAT_GOUT_CORE_GIC_CLK 0x2040
+#define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK 0x2044
#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK 0x20e8
#define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
#define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK 0x2128
#define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK 0x212c
+#define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130

static const unsigned long core_clk_regs[] __initconst = {
PLL_CON0_MUX_CLKCMU_CORE_BUS_USER,
@@ -924,10 +945,12 @@ static const unsigned long core_clk_regs[] __initconst = {
CLK_CON_DIV_DIV_CLK_CORE_BUSP,
CLK_CON_GAT_GOUT_CORE_CCI_550_ACLK,
CLK_CON_GAT_GOUT_CORE_GIC_CLK,
+ CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
+ CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
};

/* List of parent clocks for Muxes in CMU_CORE */
@@ -972,6 +995,12 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = {
CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",
CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK, 21, 0, 0),
+ /* TODO: Should be enabled in GPIO driver (or made CLK_IS_CRITICAL) */
+ GATE(CLK_GOUT_GPIO_CORE_PCLK, "gout_gpio_core_pclk", "dout_core_busp",
+ CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_SYSREG_CORE_PCLK, "gout_sysreg_core_pclk",
+ "dout_core_busp",
+ CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK, 21, 0, 0),
};

static const struct samsung_cmu_info core_cmu_info __initconst = {
--
2.30.2

2021-11-27 13:20:45

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

On 26/11/2021 21:36, Sam Protsenko wrote:
> System Register is used to configure system behavior, like USI protocol,
> etc. SYSREG clocks should be provided to corresponding syscon nodes, to
> make it possible to modify SYSREG registers.
>
> While at it, add also missing PMU and GPIO clocks, which looks necessary
> and might be needed for corresponding Exynos850 features soon.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> include/dt-bindings/clock/exynos850.h | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>

Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2021-11-27 13:20:51

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH 2/2] clk: samsung: exynos850: Add missing sysreg clocks

On 26/11/2021 21:36, Sam Protsenko wrote:
> System Register is used to configure system behavior, like USI protocol,
> etc. SYSREG clocks should be provided to corresponding syscon nodes, to
> make it possible to modify SYSREG registers.
>
> While at it, add also missing PMU and GPIO clocks, which looks necessary
> and might be needed for corresponding Exynos850 features soon.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> drivers/clk/samsung/clk-exynos850.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>

Reviewed-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

2021-12-02 00:14:14

by Rob Herring

[permalink] [raw]

Subject: Re: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

On Fri, 26 Nov 2021 22:36:40 +0200, Sam Protsenko wrote:
> System Register is used to configure system behavior, like USI protocol,
> etc. SYSREG clocks should be provided to corresponding syscon nodes, to
> make it possible to modify SYSREG registers.
>
> While at it, add also missing PMU and GPIO clocks, which looks necessary
> and might be needed for corresponding Exynos850 features soon.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> include/dt-bindings/clock/exynos850.h | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>

Acked-by: Rob Herring <[email protected]>

2021-12-07 20:54:48

by Sam Protsenko

[permalink] [raw]

Subject: Re: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

On Thu, 2 Dec 2021 at 02:12, Rob Herring <[email protected]> wrote:
>
> On Fri, 26 Nov 2021 22:36:40 +0200, Sam Protsenko wrote:
> > System Register is used to configure system behavior, like USI protocol,
> > etc. SYSREG clocks should be provided to corresponding syscon nodes, to
> > make it possible to modify SYSREG registers.
> >
> > While at it, add also missing PMU and GPIO clocks, which looks necessary
> > and might be needed for corresponding Exynos850 features soon.
> >
> > Signed-off-by: Sam Protsenko <[email protected]>
> > ---
> > include/dt-bindings/clock/exynos850.h | 12 +++++++++---
> > 1 file changed, 9 insertions(+), 3 deletions(-)
> >
>
> Acked-by: Rob Herring <[email protected]>

Hi Sylwester,

Can you please review and apply this series, if it's ok?

Thanks!

2021-12-14 16:15:48

by Sam Protsenko

[permalink] [raw]

Subject: Re: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

On Tue, 7 Dec 2021 at 22:54, Sam Protsenko <[email protected]> wrote:
>
> On Thu, 2 Dec 2021 at 02:12, Rob Herring <[email protected]> wrote:
> >
> > On Fri, 26 Nov 2021 22:36:40 +0200, Sam Protsenko wrote:
> > > System Register is used to configure system behavior, like USI protocol,
> > > etc. SYSREG clocks should be provided to corresponding syscon nodes, to
> > > make it possible to modify SYSREG registers.
> > >
> > > While at it, add also missing PMU and GPIO clocks, which looks necessary
> > > and might be needed for corresponding Exynos850 features soon.
> > >
> > > Signed-off-by: Sam Protsenko <[email protected]>
> > > ---
> > > include/dt-bindings/clock/exynos850.h | 12 +++++++++---
> > > 1 file changed, 9 insertions(+), 3 deletions(-)
> > >
> >
> > Acked-by: Rob Herring <[email protected]>
>
> Hi Sylwester,
>
> Can you please review and apply this series, if it's ok?
>

Hi Krzysztof,

Do you think it's possible to take this series in your tree? Once it's
applied, I can send the board support (dts) series -- this is the only
remaining blocker for that right now.

Thanks!

> Thanks!

2021-12-14 16:21:00

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

On 14/12/2021 17:15, Sam Protsenko wrote:
> On Tue, 7 Dec 2021 at 22:54, Sam Protsenko <[email protected]> wrote:
>>
>> On Thu, 2 Dec 2021 at 02:12, Rob Herring <[email protected]> wrote:
>>>
>>> On Fri, 26 Nov 2021 22:36:40 +0200, Sam Protsenko wrote:
>>>> System Register is used to configure system behavior, like USI protocol,
>>>> etc. SYSREG clocks should be provided to corresponding syscon nodes, to
>>>> make it possible to modify SYSREG registers.
>>>>
>>>> While at it, add also missing PMU and GPIO clocks, which looks necessary
>>>> and might be needed for corresponding Exynos850 features soon.
>>>>
>>>> Signed-off-by: Sam Protsenko <[email protected]>
>>>> ---
>>>> include/dt-bindings/clock/exynos850.h | 12 +++++++++---
>>>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>>>
>>>
>>> Acked-by: Rob Herring <[email protected]>
>>
>> Hi Sylwester,
>>
>> Can you please review and apply this series, if it's ok?
>>
>
> Hi Krzysztof,
>
> Do you think it's possible to take this series in your tree? Once it's
> applied, I can send the board support (dts) series -- this is the only
> remaining blocker for that right now.

I would need an Ack from Sylwester anyway. If you have dependencies (the
DTS), you should send them together with it. Once Sylwester applies this
patch, the DTS either waits till next release or it has to be modified
to not depend on this patch.

Best regards,
Krzysztof

2021-12-18 10:50:56

by Krzysztof Kozlowski

[permalink] [raw]

Subject: Re: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

On 14/12/2021 17:20, Krzysztof Kozlowski wrote:
> On 14/12/2021 17:15, Sam Protsenko wrote:
>> On Tue, 7 Dec 2021 at 22:54, Sam Protsenko <[email protected]> wrote:
>>>
>>> On Thu, 2 Dec 2021 at 02:12, Rob Herring <[email protected]> wrote:
>>>>
>>>> On Fri, 26 Nov 2021 22:36:40 +0200, Sam Protsenko wrote:
>>>>> System Register is used to configure system behavior, like USI protocol,
>>>>> etc. SYSREG clocks should be provided to corresponding syscon nodes, to
>>>>> make it possible to modify SYSREG registers.
>>>>>
>>>>> While at it, add also missing PMU and GPIO clocks, which looks necessary
>>>>> and might be needed for corresponding Exynos850 features soon.
>>>>>
>>>>> Signed-off-by: Sam Protsenko <[email protected]>
>>>>> ---
>>>>> include/dt-bindings/clock/exynos850.h | 12 +++++++++---
>>>>> 1 file changed, 9 insertions(+), 3 deletions(-)
>>>>>
>>>>
>>>> Acked-by: Rob Herring <[email protected]>
>>>
>>> Hi Sylwester,
>>>
>>> Can you please review and apply this series, if it's ok?
>>>
>>
>> Hi Krzysztof,
>>
>> Do you think it's possible to take this series in your tree? Once it's
>> applied, I can send the board support (dts) series -- this is the only
>> remaining blocker for that right now.
>
> I would need an Ack from Sylwester anyway. If you have dependencies (the
> DTS), you should send them together with it. Once Sylwester applies this
> patch, the DTS either waits till next release or it has to be modified
> to not depend on this patch.

Sylwester,

We need decision from your side. The apply-window is slowly closing, so
at least take it so DTSI will be free to go next cycle.

Best regards,
Krzysztof

2021-12-19 11:18:28

by Alim Akhtar

[permalink] [raw]

Subject: Re: [PATCH 1/2] dt-bindings: clock: exynos850: Add bindings for Exynos850 sysreg clocks

On Mon, Nov 29, 2021 at 7:08 PM Sam Protsenko
<[email protected]> wrote:
>
> System Register is used to configure system behavior, like USI protocol,
> etc. SYSREG clocks should be provided to corresponding syscon nodes, to
> make it possible to modify SYSREG registers.
>
> While at it, add also missing PMU and GPIO clocks, which looks necessary
> and might be needed for corresponding Exynos850 features soon.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> include/dt-bindings/clock/exynos850.h | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
Looks good, feel free to add

Reviewed-by: Alim Akhtar <[email protected]>

> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index 8aa5e82af0d3..0b6a3c6a7c90 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -82,7 +82,10 @@
> #define CLK_GOUT_I3C_PCLK 19
> #define CLK_GOUT_I3C_SCLK 20
> #define CLK_GOUT_SPEEDY_PCLK 21
> -#define APM_NR_CLK 22
> +#define CLK_GOUT_GPIO_ALIVE_PCLK 22
> +#define CLK_GOUT_PMU_ALIVE_PCLK 23
> +#define CLK_GOUT_SYSREG_APM_PCLK 24
> +#define APM_NR_CLK 25
>
> /* CMU_CMGP */
> #define CLK_RCO_CMGP 1
> @@ -99,7 +102,8 @@
> #define CLK_GOUT_CMGP_USI0_PCLK 12
> #define CLK_GOUT_CMGP_USI1_IPCLK 13
> #define CLK_GOUT_CMGP_USI1_PCLK 14
> -#define CMGP_NR_CLK 15
> +#define CLK_GOUT_SYSREG_CMGP_PCLK 15
> +#define CMGP_NR_CLK 16
>
> /* CMU_HSI */
> #define CLK_MOUT_HSI_BUS_USER 1
> @@ -167,7 +171,9 @@
> #define CLK_GOUT_MMC_EMBD_SDCLKIN 10
> #define CLK_GOUT_SSS_ACLK 11
> #define CLK_GOUT_SSS_PCLK 12
> -#define CORE_NR_CLK 13
> +#define CLK_GOUT_GPIO_CORE_PCLK 13
> +#define CLK_GOUT_SYSREG_CORE_PCLK 14
> +#define CORE_NR_CLK 15
>
> /* CMU_DPU */
> #define CLK_MOUT_DPU_USER 1
> --
> 2.30.2
>

--
Regards,
Alim