Add support for a DSI output on VDOSYS0. Luckily, there is a new
feature to support dynamic selections of the output (connector).
Use it to add support for a DSI output.
Apart from that, this is pretty straghtforward by just adding new
compatibles and add the correct DSI nodes to the SoC dtsi.
This was tested with a Toshiba TC358775 DSI-to-LVDS bridge and
three different panels. Please note, that the driver for this
bridge doesn't work well and needs a more or less complete rework,
which will be posted on a separate series.
Michael Walle (4):
dt-bindings: display: mediatek: dsi: add compatible for MediaTek
MT8195
dt-bindings: phy: add compatible for Mediatek MT8195
arm64: dts: mediatek: mt8195: add DSI and MIPI DPHY nodes
drm/mediatek: support the DSI0 output on the MT8195 VDOSYS0
.../display/mediatek/mediatek,dsi.yaml | 4 ++
.../bindings/phy/mediatek,dsi-phy.yaml | 1 +
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 48 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +++-
4 files changed, 60 insertions(+), 1 deletion(-)
--
2.39.2
Add the compatible string for MediaTek MT8195 SoC, using the same MIPI
D-PHY block as the MT8183.
Signed-off-by: Michael Walle <[email protected]>
---
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
index 6703689fcdbe..f6e494d0d89b 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
@@ -31,6 +31,7 @@ properties:
- items:
- enum:
- mediatek,mt8188-mipi-tx
+ - mediatek,mt8195-mipi-tx
- mediatek,mt8365-mipi-tx
- const: mediatek,mt8183-mipi-tx
- const: mediatek,mt2701-mipi-tx
--
2.39.2
Add the compatible string for MediaTek MT8195 SoC, using the same DSI
block as the MT8183.
Signed-off-by: Michael Walle <[email protected]>
---
.../devicetree/bindings/display/mediatek/mediatek,dsi.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
index 537e5304b730..4a7a9ff21996 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.yaml
@@ -35,6 +35,10 @@ properties:
- enum:
- mediatek,mt6795-dsi
- const: mediatek,mt8173-dsi
+ - items:
+ - enum:
+ - mediatek,mt8195-dsi
+ - const: mediatek,mt8183-dsi
reg:
maxItems: 1
--
2.39.2
With the latest dynamic selection of the output component, we can now
support different outputs. Move current output component into the
dynamic routes array and add the new DSI0 output.
Signed-off-by: Michael Walle <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 2b0c35cacbc6..6fa88976376e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -222,7 +222,11 @@ static const unsigned int mt8195_mtk_ddp_main[] = {
DDP_COMPONENT_DITHER0,
DDP_COMPONENT_DSC0,
DDP_COMPONENT_MERGE0,
- DDP_COMPONENT_DP_INTF0,
+};
+
+static const struct mtk_drm_route mt8195_mtk_ddp_main_routes[] = {
+ { 0, DDP_COMPONENT_DP_INTF0 },
+ { 0, DDP_COMPONENT_DSI0 },
};
static const unsigned int mt8195_mtk_ddp_ext[] = {
@@ -308,6 +312,8 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
.main_path = mt8195_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+ .conn_routes = mt8195_mtk_ddp_main_routes,
+ .num_conn_routes = ARRAY_SIZE(mt8195_mtk_ddp_main_routes),
.mmsys_dev_num = 2,
};
--
2.39.2
Add the two DSI controller node and the associated DPHY nodes.
Individual boards have to enable them in the board device tree.
Signed-off-by: Michael Walle <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 48 ++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 54c674c45b49..0621bb461967 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1714,6 +1714,26 @@ u2port3: usb-phy@0 {
};
};
+ mipi_tx0: dsi-phy@11c80000 {
+ compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c80000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi_tx1: dsi-phy@11c90000 {
+ compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx";
+ reg = <0 0x11c90000 0 0x1000>;
+ clocks = <&clk26m>;
+ clock-output-names = "mipi_tx1_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
i2c5: i2c@11d00000 {
compatible = "mediatek,mt8195-i2c",
"mediatek,mt8192-i2c";
@@ -2737,6 +2757,20 @@ dither0: dither@1c007000 {
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
};
+ dsi0: dsi@1c008000 {
+ compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
+ reg = <0 0x1c008000 0 0x1000>;
+ interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSI0>,
+ <&vdosys0 CLK_VDO0_DSI0_DSI>,
+ <&mipi_tx0>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx0>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
dsc0: dsc@1c009000 {
compatible = "mediatek,mt8195-disp-dsc";
reg = <0 0x1c009000 0 0x1000>;
@@ -2746,6 +2780,20 @@ dsc0: dsc@1c009000 {
mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
};
+ dsi1: dsi@1c012000 {
+ compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi";
+ reg = <0 0x1c012000 0 0x1000>;
+ interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSI1>,
+ <&vdosys0 CLK_VDO0_DSI1_DSI>,
+ <&mipi_tx1>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx1>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
merge0: merge@1c014000 {
compatible = "mediatek,mt8195-disp-merge";
reg = <0 0x1c014000 0 0x1000>;
--
2.39.2
On Thu, Nov 23, 2023 at 02:37:46PM +0100, Michael Walle wrote:
> Add the compatible string for MediaTek MT8195 SoC, using the same DSI
> block as the MT8183.
>
> Signed-off-by: Michael Walle <[email protected]>
Acked-by: Conor Dooley <[email protected]>
On Thu, Nov 23, 2023 at 02:37:47PM +0100, Michael Walle wrote:
> Add the compatible string for MediaTek MT8195 SoC, using the same MIPI
> D-PHY block as the MT8183.
>
> Signed-off-by: Michael Walle <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Cheers,
Conor.
On Thu, Nov 23, 2023 at 9:38 PM Michael Walle <[email protected]> wrote:
>
> Add the two DSI controller node and the associated DPHY nodes.
> Individual boards have to enable them in the board device tree.
>
> Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
I checked all the address ranges and interrupt values and they are all
correct. The other bits seem to be correct, extrapolating from previous
chips such as MT8183 and MT8192.
On Thu, 23 Nov 2023 14:37:45 +0100, Michael Walle wrote:
> Add support for a DSI output on VDOSYS0. Luckily, there is a new
> feature to support dynamic selections of the output (connector).
> Use it to add support for a DSI output.
>
> Apart from that, this is pretty straghtforward by just adding new
> compatibles and add the correct DSI nodes to the SoC dtsi.
>
> [...]
Applied, thanks!
[2/4] dt-bindings: phy: add compatible for Mediatek MT8195
commit: fa50920b4f82993941e0aac349eb8081ce11e38f
Best regards,
--
~Vinod
Il 23/11/23 14:37, Michael Walle ha scritto:
> Add the compatible string for MediaTek MT8195 SoC, using the same DSI
> block as the MT8183.
>
> Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 23/11/23 14:37, Michael Walle ha scritto:
> With the latest dynamic selection of the output component, we can now
> support different outputs. Move current output component into the
> dynamic routes array and add the new DSI0 output.
>
> Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Il 23/11/23 14:37, Michael Walle ha scritto:
> Add the two DSI controller node and the associated DPHY nodes.
> Individual boards have to enable them in the board device tree.
>
> Signed-off-by: Michael Walle <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
> With the latest dynamic selection of the output component, we can now
> support different outputs. Move current output component into the
> dynamic routes array and add the new DSI0 output.
>
> Signed-off-by: Michael Walle <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 2b0c35cacbc6..6fa88976376e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -222,7 +222,11 @@ static const unsigned int mt8195_mtk_ddp_main[] =
> {
> DDP_COMPONENT_DITHER0,
> DDP_COMPONENT_DSC0,
> DDP_COMPONENT_MERGE0,
> - DDP_COMPONENT_DP_INTF0,
Please disregard this patch (the others are ok). There must gone
something
wrong during my testing. DDP_COMPONENT_MERGE0 won't work with
DDP_COMPONENT_DSI0. If anyone has more insights, I'm all ears.
-michael
> +};
> +
> +static const struct mtk_drm_route mt8195_mtk_ddp_main_routes[] = {
> + { 0, DDP_COMPONENT_DP_INTF0 },
> + { 0, DDP_COMPONENT_DSI0 },
> };
>
> static const unsigned int mt8195_mtk_ddp_ext[] = {
> @@ -308,6 +312,8 @@ static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
> static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data =
> {
> .main_path = mt8195_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> + .conn_routes = mt8195_mtk_ddp_main_routes,
> + .num_conn_routes = ARRAY_SIZE(mt8195_mtk_ddp_main_routes),
> .mmsys_dev_num = 2,
> };
Il 30/11/23 13:47, Michael Walle ha scritto:
>> With the latest dynamic selection of the output component, we can now
>> support different outputs. Move current output component into the
>> dynamic routes array and add the new DSI0 output.
>>
>> Signed-off-by: Michael Walle <[email protected]>
>> ---
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +++++++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> index 2b0c35cacbc6..6fa88976376e 100644
>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>> @@ -222,7 +222,11 @@ static const unsigned int mt8195_mtk_ddp_main[] = {
>> DDP_COMPONENT_DITHER0,
>> DDP_COMPONENT_DSC0,
>> DDP_COMPONENT_MERGE0,
>> - DDP_COMPONENT_DP_INTF0,
>
> Please disregard this patch (the others are ok). There must gone something
> wrong during my testing. DDP_COMPONENT_MERGE0 won't work with
> DDP_COMPONENT_DSI0. If anyone has more insights, I'm all ears.
>
I was *convinced* that the MERGE0 SOUT was connected to DSI0!!!
...but you're right, here, and thanks for catching that: there's no way to
get MERGE0 connected to DSI0; if you check in the datasheet for VDO_SEL_IN,
you can get data from MERGE0 only for DSI*1*, not 0.
The only way is to connect DSC_WRAP0 (DDP_COMPONENT_DSC0 in mtk_drm_drv btw)
directly to DSI0 (or dither to dsi0)... unless there is a way to change the
pinmux to invert the pins for DSI0/1?
You could assign the DSI1 controller to the one that is currently DSI0 for you.
That would solve the issue here.
Cheers!
Angelo
> -michael
>
>> +};
>> +
>> +static const struct mtk_drm_route mt8195_mtk_ddp_main_routes[] = {
>> + { 0, DDP_COMPONENT_DP_INTF0 },
>> + { 0, DDP_COMPONENT_DSI0 },
>> };
>>
>> static const unsigned int mt8195_mtk_ddp_ext[] = {
>> @@ -308,6 +312,8 @@ static const struct mtk_mmsys_driver_data
>> mt8192_mmsys_driver_data = {
>> static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
>> .main_path = mt8195_mtk_ddp_main,
>> .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
>> + .conn_routes = mt8195_mtk_ddp_main_routes,
>> + .num_conn_routes = ARRAY_SIZE(mt8195_mtk_ddp_main_routes),
>> .mmsys_dev_num = 2,
>> };