2020-03-10 17:47:59

by Chen-Yu Tsai

Subject: [PATCH 0/3] ARM: dts: sun8i: r40: fix SPI address and reorder nodes

From: Chen-Yu Tsai <[email protected]>

Hi,

Here are some fixes for the R40 device tree for v5.6. The base addresses
for SPI2 and SPI3 were incorrect and are fixed. I also found some nodes
were not added in the proper order, possibly because git matched the
incorrect place when applying the patch. These are fixed as well.

ChenYu

Chen-Yu Tsai (3):
ARM: dts: sun8i: r40: Move AHCI device node based on address order
ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3
ARM: dts: sun8i: r40: Move SPI device nodes based on address order

arch/arm/boot/dts/sun8i-r40.dtsi | 126 +++++++++++++++----------------
1 file changed, 63 insertions(+), 63 deletions(-)

--
2.25.1

2020-03-10 17:48:48

by Chen-Yu Tsai

Subject: [PATCH 3/3] ARM: dts: sun8i: r40: Move SPI device nodes based on address order

From: Chen-Yu Tsai <[email protected]>

When the SPI device nodes were added, they were added in the wrong
location in the device tree file. The device nodes should be sorted
by register address.

Move the devices node to their correct positions within the file.

Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
Signed-off-by: Chen-Yu Tsai <[email protected]>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 104 +++++++++++++++----------------
1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 81cc92ddc78b..f0ede4f52aa3 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -198,6 +198,32 @@ nmi_intc: interrupt-controller@1c00030 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};

+ spi0: spi@1c05000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c05000 0x1000>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@1c06000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c06000 0x1000>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
csi0: csi@1c09000 {
compatible = "allwinner,sun8i-r40-csi0",
"allwinner,sun7i-a20-csi0";
@@ -307,6 +333,19 @@ crypto: crypto@1c15000 {
resets = <&ccu RST_BUS_CE>;
};

+ spi2: spi@1c17000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c17000 0x1000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI2>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ahci: sata@1c18000 {
compatible = "allwinner,sun8i-r40-ahci";
reg = <0x01c18000 0x1000>;
@@ -364,6 +403,19 @@ ohci2: usb@1c1c400 {
status = "disabled";
};

+ spi3: spi@1c1f000 {
+ compatible = "allwinner,sun8i-r40-spi",
+ "allwinner,sun8i-h3-spi";
+ reg = <0x01c1f000 0x1000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_SPI3>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-r40-ccu";
reg = <0x01c20000 0x400>;
@@ -692,58 +744,6 @@ i2c4: i2c@1c2c000 {
#size-cells = <0>;
};

- spi0: spi@1c05000 {
- compatible = "allwinner,sun8i-r40-spi",
- "allwinner,sun8i-h3-spi";
- reg = <0x01c05000 0x1000>;
- interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
- clock-names = "ahb", "mod";
- resets = <&ccu RST_BUS_SPI0>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi1: spi@1c06000 {
- compatible = "allwinner,sun8i-r40-spi",
- "allwinner,sun8i-h3-spi";
- reg = <0x01c06000 0x1000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
- clock-names = "ahb", "mod";
- resets = <&ccu RST_BUS_SPI1>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi2: spi@1c17000 {
- compatible = "allwinner,sun8i-r40-spi",
- "allwinner,sun8i-h3-spi";
- reg = <0x01c17000 0x1000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
- clock-names = "ahb", "mod";
- resets = <&ccu RST_BUS_SPI2>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- spi3: spi@1c1f000 {
- compatible = "allwinner,sun8i-r40-spi",
- "allwinner,sun8i-h3-spi";
- reg = <0x01c1f000 0x1000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
- clock-names = "ahb", "mod";
- resets = <&ccu RST_BUS_SPI3>;
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
gmac: ethernet@1c50000 {
compatible = "allwinner,sun8i-r40-gmac";
syscon = <&ccu>;
--
2.25.1

2020-03-10 18:11:51

by Maxime Ripard

Subject: Re: [PATCH 0/3] ARM: dts: sun8i: r40: fix SPI address and reorder nodes

On Wed, Mar 11, 2020 at 01:47:06AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <[email protected]>
>
> Hi,
>
> Here are some fixes for the R40 device tree for v5.6. The base addresses
> for SPI2 and SPI3 were incorrect and are fixed. I also found some nodes
> were not added in the proper order, possibly because git matched the
> incorrect place when applying the patch. These are fixed as well.
>
> ChenYu

Acked-by: Maxime Ripard <[email protected]>

Thanks!
Maxime

2020-03-11 11:23:22

by Andre Przywara

Subject: Re: [PATCH 3/3] ARM: dts: sun8i: r40: Move SPI device nodes based on address order

On Wed, 11 Mar 2020 01:47:09 +0800
Chen-Yu Tsai <[email protected]> wrote:

> From: Chen-Yu Tsai <[email protected]>
>
> When the SPI device nodes were added, they were added in the wrong
> location in the device tree file. The device nodes should be sorted
> by register address.
>
> Move the devices node to their correct positions within the file.

Diffed the minus and plus lines, it's indeed a pure move:

Reviewed-by: Andre Przywara <[email protected]>

Cheers,
Andre

>
> Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
> Signed-off-by: Chen-Yu Tsai <[email protected]>
> ---
> arch/arm/boot/dts/sun8i-r40.dtsi | 104 +++++++++++++++----------------
> 1 file changed, 52 insertions(+), 52 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index 81cc92ddc78b..f0ede4f52aa3 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -198,6 +198,32 @@ nmi_intc: interrupt-controller@1c00030 {
> interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + spi0: spi@1c05000 {
> + compatible = "allwinner,sun8i-r40-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x01c05000 0x1000>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI0>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi@1c06000 {
> + compatible = "allwinner,sun8i-r40-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x01c06000 0x1000>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> csi0: csi@1c09000 {
> compatible = "allwinner,sun8i-r40-csi0",
> "allwinner,sun7i-a20-csi0";
> @@ -307,6 +333,19 @@ crypto: crypto@1c15000 {
> resets = <&ccu RST_BUS_CE>;
> };
>
> + spi2: spi@1c17000 {
> + compatible = "allwinner,sun8i-r40-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x01c17000 0x1000>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> ahci: sata@1c18000 {
> compatible = "allwinner,sun8i-r40-ahci";
> reg = <0x01c18000 0x1000>;
> @@ -364,6 +403,19 @@ ohci2: usb@1c1c400 {
> status = "disabled";
> };
>
> + spi3: spi@1c1f000 {
> + compatible = "allwinner,sun8i-r40-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x01c1f000 0x1000>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI3>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> ccu: clock@1c20000 {
> compatible = "allwinner,sun8i-r40-ccu";
> reg = <0x01c20000 0x400>;
> @@ -692,58 +744,6 @@ i2c4: i2c@1c2c000 {
> #size-cells = <0>;
> };
>
> - spi0: spi@1c05000 {
> - compatible = "allwinner,sun8i-r40-spi",
> - "allwinner,sun8i-h3-spi";
> - reg = <0x01c05000 0x1000>;
> - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> - clock-names = "ahb", "mod";
> - resets = <&ccu RST_BUS_SPI0>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - spi1: spi@1c06000 {
> - compatible = "allwinner,sun8i-r40-spi",
> - "allwinner,sun8i-h3-spi";
> - reg = <0x01c06000 0x1000>;
> - interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> - clock-names = "ahb", "mod";
> - resets = <&ccu RST_BUS_SPI1>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - spi2: spi@1c17000 {
> - compatible = "allwinner,sun8i-r40-spi",
> - "allwinner,sun8i-h3-spi";
> - reg = <0x01c17000 0x1000>;
> - interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
> - clock-names = "ahb", "mod";
> - resets = <&ccu RST_BUS_SPI2>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> - spi3: spi@1c1f000 {
> - compatible = "allwinner,sun8i-r40-spi",
> - "allwinner,sun8i-h3-spi";
> - reg = <0x01c1f000 0x1000>;
> - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
> - clock-names = "ahb", "mod";
> - resets = <&ccu RST_BUS_SPI3>;
> - status = "disabled";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - };
> -
> gmac: ethernet@1c50000 {
> compatible = "allwinner,sun8i-r40-gmac";
> syscon = <&ccu>;

2020-03-12 03:26:57

by Chen-Yu Tsai

Subject: Re: [PATCH 0/3] ARM: dts: sun8i: r40: fix SPI address and reorder nodes

On Wed, Mar 11, 2020 at 2:10 AM Maxime Ripard <[email protected]> wrote:
>
> On Wed, Mar 11, 2020 at 01:47:06AM +0800, Chen-Yu Tsai wrote:
> > From: Chen-Yu Tsai <[email protected]>
> >
> > Hi,
> >
> > Here are some fixes for the R40 device tree for v5.6. The base addresses
> > for SPI2 and SPI3 were incorrect and are fixed. I also found some nodes
> > were not added in the proper order, possibly because git matched the
> > incorrect place when applying the patch. These are fixed as well.
> >
> > ChenYu
>
> Acked-by: Maxime Ripard <[email protected]>

Merged all three for v5.6 with Andre's Reviewed-by and a reported-by
for the SPI address base patch.