From: Arnd Bergmann <[email protected]>
A few Arm platforms are getting removed in v5.12, this removes
the corresponding mmc drivers.
Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/T/
Arnd Bergmann (2):
mmc: remove dw_mmc-zx driver
mmc: remove sirf prima/atlas driver
.../devicetree/bindings/mmc/sdhci-sirf.txt | 18 --
.../devicetree/bindings/mmc/zx-dw-mshc.txt | 31 ---
drivers/mmc/host/Kconfig | 21 --
drivers/mmc/host/Makefile | 2 -
drivers/mmc/host/dw_mmc-zx.c | 234 -----------------
drivers/mmc/host/dw_mmc-zx.h | 32 ---
drivers/mmc/host/sdhci-sirf.c | 235 ------------------
7 files changed, 573 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sirf.txt
delete mode 100644 Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
delete mode 100644 drivers/mmc/host/dw_mmc-zx.c
delete mode 100644 drivers/mmc/host/dw_mmc-zx.h
delete mode 100644 drivers/mmc/host/sdhci-sirf.c
--
2.29.2
From: Arnd Bergmann <[email protected]>
The CSR SiRF prima2/atlas platforms are getting removed, so this driver
is no longer needed.
Cc: Barry Song <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
---
.../devicetree/bindings/mmc/sdhci-sirf.txt | 18 --
drivers/mmc/host/Kconfig | 12 -
drivers/mmc/host/Makefile | 1 -
drivers/mmc/host/sdhci-sirf.c | 235 ------------------
4 files changed, 266 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sirf.txt
delete mode 100644 drivers/mmc/host/sdhci-sirf.c
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt b/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt
deleted file mode 100644
index dd6ed464bcb8..000000000000
--- a/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-* SiRFprimII/marco/atlas6 SDHCI Controller
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the sdhci-sirf driver.
-
-Required properties:
-- compatible: sirf,prima2-sdhc
-
-Optional properties:
-- cd-gpios: card detect gpio, with zero flags.
-
-Example:
-
- sd0: sdhci@56000000 {
- compatible = "sirf,prima2-sdhc";
- reg = <0xcd000000 0x100000>;
- cd-gpios = <&gpio 6 0>;
- };
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 255d37e8bd3a..b67f6028b6f3 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -312,18 +312,6 @@ config MMC_SDHCI_S3C
If unsure, say N.
-config MMC_SDHCI_SIRF
- tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
- depends on ARCH_SIRF || COMPILE_TEST
- depends on MMC_SDHCI_PLTFM
- select MMC_SDHCI_IO_ACCESSORS
- help
- This selects the SDHCI support for SiRF System-on-Chip devices.
-
- If you have a controller with this interface, say Y or M here.
-
- If unsure, say N.
-
config MMC_SDHCI_PXAV3
tristate "Marvell MMP2 SD Host Controller support (PXAV3)"
depends on CLKDEV_LOOKUP
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 43136d382d5f..d2ec428cc808 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
-obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
obj-$(CONFIG_MMC_SDHCI_MILBEAUT) += sdhci-milbeaut.o
obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
deleted file mode 100644
index e9b347b3af7e..000000000000
--- a/drivers/mmc/host/sdhci-sirf.c
+++ /dev/null
@@ -1,235 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * SDHCI support for SiRF primaII and marco SoCs
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- */
-
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/mmc/host.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/mmc/slot-gpio.h>
-#include "sdhci-pltfm.h"
-
-#define SDHCI_CLK_DELAY_SETTING 0x4C
-#define SDHCI_SIRF_8BITBUS BIT(3)
-#define SIRF_TUNING_COUNT 16384
-
-static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
-{
- u8 ctrl;
-
- ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
- ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_SIRF_8BITBUS);
-
- /*
- * CSR atlas7 and prima2 SD host version is not 3.0
- * 8bit-width enable bit of CSR SD hosts is 3,
- * while stardard hosts use bit 5
- */
- if (width == MMC_BUS_WIDTH_8)
- ctrl |= SDHCI_SIRF_8BITBUS;
- else if (width == MMC_BUS_WIDTH_4)
- ctrl |= SDHCI_CTRL_4BITBUS;
-
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
-}
-
-static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
-{
- u32 val = readl(host->ioaddr + reg);
-
- if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
- (host->mmc->caps & MMC_CAP_UHS_SDR50))) {
- /* fake CAP_1 register */
- val = SDHCI_SUPPORT_DDR50 |
- SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
- }
-
- if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
- u32 prss = val;
- /* fake chips as V3.0 host conreoller */
- prss &= ~(0xFF << 16);
- val = prss | (SDHCI_SPEC_300 << 16);
- }
- return val;
-}
-
-static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
-{
- u16 ret = 0;
-
- ret = readw(host->ioaddr + reg);
-
- if (unlikely(reg == SDHCI_HOST_VERSION)) {
- ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
- ret |= SDHCI_SPEC_300;
- }
-
- return ret;
-}
-
-static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
-{
- int tuning_seq_cnt = 3;
- int phase;
- u8 tuned_phase_cnt = 0;
- int rc = 0, longest_range = 0;
- int start = -1, end = 0, tuning_value = -1, range = 0;
- u16 clock_setting;
- struct mmc_host *mmc = host->mmc;
-
- clock_setting = sdhci_readw(host, SDHCI_CLK_DELAY_SETTING);
- clock_setting &= ~0x3fff;
-
-retry:
- phase = 0;
- tuned_phase_cnt = 0;
- do {
- sdhci_writel(host,
- clock_setting | phase,
- SDHCI_CLK_DELAY_SETTING);
-
- if (!mmc_send_tuning(mmc, opcode, NULL)) {
- /* Tuning is successful at this tuning point */
- tuned_phase_cnt++;
- dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
- mmc_hostname(mmc), phase);
- if (start == -1)
- start = phase;
- end = phase;
- range++;
- if (phase == (SIRF_TUNING_COUNT - 1)
- && range > longest_range)
- tuning_value = (start + end) / 2;
- } else {
- dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n",
- mmc_hostname(mmc), phase);
- if (range > longest_range) {
- tuning_value = (start + end) / 2;
- longest_range = range;
- }
- start = -1;
- end = range = 0;
- }
- } while (++phase < SIRF_TUNING_COUNT);
-
- if (tuned_phase_cnt && tuning_value > 0) {
- /*
- * Finally set the selected phase in delay
- * line hw block.
- */
- phase = tuning_value;
- sdhci_writel(host,
- clock_setting | phase,
- SDHCI_CLK_DELAY_SETTING);
-
- dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
- mmc_hostname(mmc), phase);
- } else {
- if (--tuning_seq_cnt)
- goto retry;
- /* Tuning failed */
- dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
- mmc_hostname(mmc));
- rc = -EIO;
- }
-
- return rc;
-}
-
-static const struct sdhci_ops sdhci_sirf_ops = {
- .read_l = sdhci_sirf_readl_le,
- .read_w = sdhci_sirf_readw_le,
- .platform_execute_tuning = sdhci_sirf_execute_tuning,
- .set_clock = sdhci_set_clock,
- .get_max_clock = sdhci_pltfm_clk_get_max_clock,
- .set_bus_width = sdhci_sirf_set_bus_width,
- .reset = sdhci_reset,
- .set_uhs_signaling = sdhci_set_uhs_signaling,
-};
-
-static const struct sdhci_pltfm_data sdhci_sirf_pdata = {
- .ops = &sdhci_sirf_ops,
- .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
- SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
- SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
- SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
- .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
-};
-
-static int sdhci_sirf_probe(struct platform_device *pdev)
-{
- struct sdhci_host *host;
- struct sdhci_pltfm_host *pltfm_host;
- struct clk *clk;
- int ret;
-
- clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(clk)) {
- dev_err(&pdev->dev, "unable to get clock");
- return PTR_ERR(clk);
- }
-
- host = sdhci_pltfm_init(pdev, &sdhci_sirf_pdata, 0);
- if (IS_ERR(host))
- return PTR_ERR(host);
-
- pltfm_host = sdhci_priv(host);
- pltfm_host->clk = clk;
-
- sdhci_get_of_property(pdev);
-
- ret = clk_prepare_enable(pltfm_host->clk);
- if (ret)
- goto err_clk_prepare;
-
- ret = sdhci_add_host(host);
- if (ret)
- goto err_sdhci_add;
-
- /*
- * We must request the IRQ after sdhci_add_host(), as the tasklet only
- * gets setup in sdhci_add_host() and we oops.
- */
- ret = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0);
- if (ret == -EPROBE_DEFER)
- goto err_request_cd;
- if (!ret)
- mmc_gpiod_request_cd_irq(host->mmc);
-
- return 0;
-
-err_request_cd:
- sdhci_remove_host(host, 0);
-err_sdhci_add:
- clk_disable_unprepare(pltfm_host->clk);
-err_clk_prepare:
- sdhci_pltfm_free(pdev);
- return ret;
-}
-
-static const struct of_device_id sdhci_sirf_of_match[] = {
- { .compatible = "sirf,prima2-sdhc" },
- { }
-};
-MODULE_DEVICE_TABLE(of, sdhci_sirf_of_match);
-
-static struct platform_driver sdhci_sirf_driver = {
- .driver = {
- .name = "sdhci-sirf",
- .probe_type = PROBE_PREFER_ASYNCHRONOUS,
- .of_match_table = sdhci_sirf_of_match,
- .pm = &sdhci_pltfm_pmops,
- },
- .probe = sdhci_sirf_probe,
- .remove = sdhci_pltfm_unregister,
-};
-
-module_platform_driver(sdhci_sirf_driver);
-
-MODULE_DESCRIPTION("SDHCI driver for SiRFprimaII/SiRFmarco");
-MODULE_AUTHOR("Barry Song <[email protected]>");
-MODULE_LICENSE("GPL v2");
--
2.29.2
From: Arnd Bergmann <[email protected]>
The zte zx platform is getting removed, so this driver is no
longer needed.
Cc: Jun Nie <[email protected]>
Cc: Shawn Guo <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
---
.../devicetree/bindings/mmc/zx-dw-mshc.txt | 31 ---
drivers/mmc/host/Kconfig | 9 -
drivers/mmc/host/Makefile | 1 -
drivers/mmc/host/dw_mmc-zx.c | 234 ------------------
drivers/mmc/host/dw_mmc-zx.h | 32 ---
5 files changed, 307 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
delete mode 100644 drivers/mmc/host/dw_mmc-zx.c
delete mode 100644 drivers/mmc/host/dw_mmc-zx.h
diff --git a/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
deleted file mode 100644
index 0f59bd5361f5..000000000000
--- a/Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* ZTE specific extensions to the Synopsys Designware Mobile Storage
- Host Controller
-
-The Synopsys designware mobile storage host controller is used to interface
-a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
-differences between the core Synopsys dw mshc controller properties described
-by synopsys-dw-mshc.txt and the properties used by the ZTE specific
-extensions to the Synopsys Designware Mobile Storage Host Controller.
-
-Required Properties:
-
-* compatible: should be
- - "zte,zx296718-dw-mshc": for ZX SoCs
-
-Example:
-
- mmc1: mmc@1110000 {
- compatible = "zte,zx296718-dw-mshc";
- reg = <0x01110000 0x1000>;
- interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- fifo-depth = <32>;
- data-addr = <0x200>;
- fifo-watermark-aligned;
- bus-width = <4>;
- clock-frequency = <50000000>;
- clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
- clock-names = "biu", "ciu";
- max-frequency = <50000000>;
- cap-sdio-irq;
- cap-sd-highspeed;
- };
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 596f32637315..255d37e8bd3a 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -868,15 +868,6 @@ config MMC_DW_ROCKCHIP
Synopsys DesignWare Memory Card Interface driver. Select this option
for platforms based on RK3066, RK3188 and RK3288 SoC's.
-config MMC_DW_ZX
- tristate "ZTE specific extensions for Synopsys DW Memory Card Interface"
- depends on MMC_DW && ARCH_ZX
- select MMC_DW_PLTFM
- help
- This selects support for ZTE SoC specific extensions to the
- Synopsys DesignWare Memory Card Interface driver. Select this option
- for platforms based on ZX296718 SoC's.
-
config MMC_SH_MMCIF
tristate "SuperH Internal MMCIF support"
depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 451c25fc2c69..43136d382d5f 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -61,7 +61,6 @@ obj-$(CONFIG_MMC_DW_HI3798CV200) += dw_mmc-hi3798cv200.o
obj-$(CONFIG_MMC_DW_K3) += dw_mmc-k3.o
obj-$(CONFIG_MMC_DW_PCI) += dw_mmc-pci.o
obj-$(CONFIG_MMC_DW_ROCKCHIP) += dw_mmc-rockchip.o
-obj-$(CONFIG_MMC_DW_ZX) += dw_mmc-zx.o
obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
obj-$(CONFIG_MMC_VUB300) += vub300.o
diff --git a/drivers/mmc/host/dw_mmc-zx.c b/drivers/mmc/host/dw_mmc-zx.c
deleted file mode 100644
index 51bcc6332f3a..000000000000
--- a/drivers/mmc/host/dw_mmc-zx.c
+++ /dev/null
@@ -1,234 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * ZX Specific Extensions for Synopsys DW Multimedia Card Interface driver
- *
- * Copyright (C) 2016, Linaro Ltd.
- * Copyright (C) 2016, ZTE Corp.
- */
-
-#include <linux/clk.h>
-#include <linux/mfd/syscon.h>
-#include <linux/mmc/host.h>
-#include <linux/mmc/mmc.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/pm_runtime.h>
-#include <linux/regmap.h>
-#include <linux/slab.h>
-
-#include "dw_mmc.h"
-#include "dw_mmc-pltfm.h"
-#include "dw_mmc-zx.h"
-
-struct dw_mci_zx_priv_data {
- struct regmap *sysc_base;
-};
-
-enum delay_type {
- DELAY_TYPE_READ, /* read dqs delay */
- DELAY_TYPE_CLK, /* clk sample delay */
-};
-
-static int dw_mci_zx_emmc_set_delay(struct dw_mci *host, unsigned int delay,
- enum delay_type dflag)
-{
- struct dw_mci_zx_priv_data *priv = host->priv;
- struct regmap *sysc_base = priv->sysc_base;
- unsigned int clksel;
- unsigned int loop = 1000;
- int ret;
-
- if (!sysc_base)
- return -EINVAL;
-
- ret = regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
- PARA_HALF_CLK_MODE | PARA_DLL_BYPASS_MODE |
- PARA_PHASE_DET_SEL_MASK |
- PARA_DLL_LOCK_NUM_MASK |
- DLL_REG_SET | PARA_DLL_START_MASK,
- PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4));
- if (ret)
- return ret;
-
- ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG1, &clksel);
- if (ret)
- return ret;
-
- if (dflag == DELAY_TYPE_CLK) {
- clksel &= ~CLK_SAMP_DELAY_MASK;
- clksel |= CLK_SAMP_DELAY(delay);
- } else {
- clksel &= ~READ_DQS_DELAY_MASK;
- clksel |= READ_DQS_DELAY(delay);
- }
-
- regmap_write(sysc_base, LB_AON_EMMC_CFG_REG1, clksel);
- regmap_update_bits(sysc_base, LB_AON_EMMC_CFG_REG0,
- PARA_DLL_START_MASK | PARA_DLL_LOCK_NUM_MASK |
- DLL_REG_SET,
- PARA_DLL_START(4) | PARA_DLL_LOCK_NUM(4) |
- DLL_REG_SET);
-
- do {
- ret = regmap_read(sysc_base, LB_AON_EMMC_CFG_REG2, &clksel);
- if (ret)
- return ret;
-
- } while (--loop && !(clksel & ZX_DLL_LOCKED));
-
- if (!loop) {
- dev_err(host->dev, "Error: %s dll lock fail\n", __func__);
- return -EIO;
- }
-
- return 0;
-}
-
-static int dw_mci_zx_emmc_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
-{
- struct dw_mci *host = slot->host;
- struct mmc_host *mmc = slot->mmc;
- int ret, len = 0, start = 0, end = 0, delay, best = 0;
-
- for (delay = 1; delay < 128; delay++) {
- ret = dw_mci_zx_emmc_set_delay(host, delay, DELAY_TYPE_CLK);
- if (!ret && mmc_send_tuning(mmc, opcode, NULL)) {
- if (start >= 0) {
- end = delay - 1;
- /* check and update longest good range */
- if ((end - start) > len) {
- best = (start + end) >> 1;
- len = end - start;
- }
- }
- start = -1;
- end = 0;
- continue;
- }
- if (start < 0)
- start = delay;
- }
-
- if (start >= 0) {
- end = delay - 1;
- if ((end - start) > len) {
- best = (start + end) >> 1;
- len = end - start;
- }
- }
- if (best < 0)
- return -EIO;
-
- dev_info(host->dev, "%s best range: start %d end %d\n", __func__,
- start, end);
- return dw_mci_zx_emmc_set_delay(host, best, DELAY_TYPE_CLK);
-}
-
-static int dw_mci_zx_prepare_hs400_tuning(struct dw_mci *host,
- struct mmc_ios *ios)
-{
- int ret;
-
- /* config phase shift as 90 degree */
- ret = dw_mci_zx_emmc_set_delay(host, 32, DELAY_TYPE_READ);
- if (ret < 0)
- return -EIO;
-
- return 0;
-}
-
-static int dw_mci_zx_execute_tuning(struct dw_mci_slot *slot, u32 opcode)
-{
- struct dw_mci *host = slot->host;
-
- if (host->verid == 0x290a) /* only for emmc */
- return dw_mci_zx_emmc_execute_tuning(slot, opcode);
- /* TODO: Add 0x210a dedicated tuning for sd/sdio */
-
- return 0;
-}
-
-static int dw_mci_zx_parse_dt(struct dw_mci *host)
-{
- struct device_node *np = host->dev->of_node;
- struct device_node *node;
- struct dw_mci_zx_priv_data *priv;
- struct regmap *sysc_base;
-
- /* syscon is needed only by emmc */
- node = of_parse_phandle(np, "zte,aon-syscon", 0);
- if (node) {
- sysc_base = syscon_node_to_regmap(node);
- of_node_put(node);
-
- if (IS_ERR(sysc_base))
- return dev_err_probe(host->dev, PTR_ERR(sysc_base),
- "Can't get syscon\n");
- } else {
- return 0;
- }
-
- priv = devm_kzalloc(host->dev, sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
- priv->sysc_base = sysc_base;
- host->priv = priv;
-
- return 0;
-}
-
-static unsigned long zx_dwmmc_caps[3] = {
- MMC_CAP_CMD23,
- MMC_CAP_CMD23,
- MMC_CAP_CMD23,
-};
-
-static const struct dw_mci_drv_data zx_drv_data = {
- .caps = zx_dwmmc_caps,
- .num_caps = ARRAY_SIZE(zx_dwmmc_caps),
- .execute_tuning = dw_mci_zx_execute_tuning,
- .prepare_hs400_tuning = dw_mci_zx_prepare_hs400_tuning,
- .parse_dt = dw_mci_zx_parse_dt,
-};
-
-static const struct of_device_id dw_mci_zx_match[] = {
- { .compatible = "zte,zx296718-dw-mshc", .data = &zx_drv_data},
- {},
-};
-MODULE_DEVICE_TABLE(of, dw_mci_zx_match);
-
-static int dw_mci_zx_probe(struct platform_device *pdev)
-{
- const struct dw_mci_drv_data *drv_data;
- const struct of_device_id *match;
-
- match = of_match_node(dw_mci_zx_match, pdev->dev.of_node);
- drv_data = match->data;
-
- return dw_mci_pltfm_register(pdev, drv_data);
-}
-
-static const struct dev_pm_ops dw_mci_zx_dev_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
- pm_runtime_force_resume)
- SET_RUNTIME_PM_OPS(dw_mci_runtime_suspend,
- dw_mci_runtime_resume,
- NULL)
-};
-
-static struct platform_driver dw_mci_zx_pltfm_driver = {
- .probe = dw_mci_zx_probe,
- .remove = dw_mci_pltfm_remove,
- .driver = {
- .name = "dwmmc_zx",
- .probe_type = PROBE_PREFER_ASYNCHRONOUS,
- .of_match_table = dw_mci_zx_match,
- .pm = &dw_mci_zx_dev_pm_ops,
- },
-};
-
-module_platform_driver(dw_mci_zx_pltfm_driver);
-
-MODULE_DESCRIPTION("ZTE emmc/sd driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/dw_mmc-zx.h b/drivers/mmc/host/dw_mmc-zx.h
deleted file mode 100644
index 09ac52766f14..000000000000
--- a/drivers/mmc/host/dw_mmc-zx.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _DW_MMC_ZX_H_
-#define _DW_MMC_ZX_H_
-
-/* ZX296718 SoC specific DLL register offset. */
-#define LB_AON_EMMC_CFG_REG0 0x1B0
-#define LB_AON_EMMC_CFG_REG1 0x1B4
-#define LB_AON_EMMC_CFG_REG2 0x1B8
-
-/* LB_AON_EMMC_CFG_REG0 register defines */
-#define PARA_DLL_START(x) ((x) & 0xFF)
-#define PARA_DLL_START_MASK 0xFF
-#define DLL_REG_SET BIT(8)
-#define PARA_DLL_LOCK_NUM(x) (((x) & 7) << 16)
-#define PARA_DLL_LOCK_NUM_MASK (7 << 16)
-#define PARA_PHASE_DET_SEL(x) (((x) & 7) << 20)
-#define PARA_PHASE_DET_SEL_MASK (7 << 20)
-#define PARA_DLL_BYPASS_MODE BIT(23)
-#define PARA_HALF_CLK_MODE BIT(24)
-
-/* LB_AON_EMMC_CFG_REG1 register defines */
-#define READ_DQS_DELAY(x) ((x) & 0x7F)
-#define READ_DQS_DELAY_MASK (0x7F)
-#define READ_DQS_BYPASS_MODE BIT(7)
-#define CLK_SAMP_DELAY(x) (((x) & 0x7F) << 8)
-#define CLK_SAMP_DELAY_MASK (0x7F << 8)
-#define CLK_SAMP_BYPASS_MODE BIT(15)
-
-/* LB_AON_EMMC_CFG_REG2 register defines */
-#define ZX_DLL_LOCKED BIT(2)
-
-#endif /* _DW_MMC_ZX_H_ */
--
2.29.2
Arnd Bergmann <[email protected]> 于2021年1月21日周四 上午3:28写道：
>
> From: Arnd Bergmann <[email protected]>
>
> The CSR SiRF prima2/atlas platforms are getting removed, so this driver
> is no longer needed.
>
> Cc: Barry Song <[email protected]>
> Signed-off-by: Arnd Bergmann <[email protected]>
Acked-by: Barry Song <[email protected]>
> ---
> .../devicetree/bindings/mmc/sdhci-sirf.txt | 18 --
> drivers/mmc/host/Kconfig | 12 -
> drivers/mmc/host/Makefile | 1 -
> drivers/mmc/host/sdhci-sirf.c | 235 ------------------
> 4 files changed, 266 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sirf.txt
> delete mode 100644 drivers/mmc/host/sdhci-sirf.c
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt b/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt
> deleted file mode 100644
> index dd6ed464bcb8..000000000000
> --- a/Documentation/devicetree/bindings/mmc/sdhci-sirf.txt
> +++ /dev/null
> @@ -1,18 +0,0 @@
> -* SiRFprimII/marco/atlas6 SDHCI Controller
> -
> -This file documents differences between the core properties in mmc.txt
> -and the properties used by the sdhci-sirf driver.
> -
> -Required properties:
> -- compatible: sirf,prima2-sdhc
> -
> -Optional properties:
> -- cd-gpios: card detect gpio, with zero flags.
> -
> -Example:
> -
> - sd0: sdhci@56000000 {
> - compatible = "sirf,prima2-sdhc";
> - reg = <0xcd000000 0x100000>;
> - cd-gpios = <&gpio 6 0>;
> - };
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 255d37e8bd3a..b67f6028b6f3 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -312,18 +312,6 @@ config MMC_SDHCI_S3C
>
> If unsure, say N.
>
> -config MMC_SDHCI_SIRF
> - tristate "SDHCI support on CSR SiRFprimaII and SiRFmarco SoCs"
> - depends on ARCH_SIRF || COMPILE_TEST
> - depends on MMC_SDHCI_PLTFM
> - select MMC_SDHCI_IO_ACCESSORS
> - help
> - This selects the SDHCI support for SiRF System-on-Chip devices.
> -
> - If you have a controller with this interface, say Y or M here.
> -
> - If unsure, say N.
> -
> config MMC_SDHCI_PXAV3
> tristate "Marvell MMP2 SD Host Controller support (PXAV3)"
> depends on CLKDEV_LOOKUP
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 43136d382d5f..d2ec428cc808 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -19,7 +19,6 @@ obj-$(CONFIG_MMC_SDHCI_ACPI) += sdhci-acpi.o
> obj-$(CONFIG_MMC_SDHCI_PXAV3) += sdhci-pxav3.o
> obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
> obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
> -obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
> obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
> obj-$(CONFIG_MMC_SDHCI_MILBEAUT) += sdhci-milbeaut.o
> obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
> diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c
> deleted file mode 100644
> index e9b347b3af7e..000000000000
> --- a/drivers/mmc/host/sdhci-sirf.c
> +++ /dev/null
> @@ -1,235 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0-or-later
> -/*
> - * SDHCI support for SiRF primaII and marco SoCs
> - *
> - * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
> - */
> -
> -#include <linux/delay.h>
> -#include <linux/device.h>
> -#include <linux/mmc/host.h>
> -#include <linux/module.h>
> -#include <linux/of.h>
> -#include <linux/mmc/slot-gpio.h>
> -#include "sdhci-pltfm.h"
> -
> -#define SDHCI_CLK_DELAY_SETTING 0x4C
> -#define SDHCI_SIRF_8BITBUS BIT(3)
> -#define SIRF_TUNING_COUNT 16384
> -
> -static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width)
> -{
> - u8 ctrl;
> -
> - ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
> - ctrl &= ~(SDHCI_CTRL_4BITBUS | SDHCI_SIRF_8BITBUS);
> -
> - /*
> - * CSR atlas7 and prima2 SD host version is not 3.0
> - * 8bit-width enable bit of CSR SD hosts is 3,
> - * while stardard hosts use bit 5
> - */
> - if (width == MMC_BUS_WIDTH_8)
> - ctrl |= SDHCI_SIRF_8BITBUS;
> - else if (width == MMC_BUS_WIDTH_4)
> - ctrl |= SDHCI_CTRL_4BITBUS;
> -
> - sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
> -}
> -
> -static u32 sdhci_sirf_readl_le(struct sdhci_host *host, int reg)
> -{
> - u32 val = readl(host->ioaddr + reg);
> -
> - if (unlikely((reg == SDHCI_CAPABILITIES_1) &&
> - (host->mmc->caps & MMC_CAP_UHS_SDR50))) {
> - /* fake CAP_1 register */
> - val = SDHCI_SUPPORT_DDR50 |
> - SDHCI_SUPPORT_SDR50 | SDHCI_USE_SDR50_TUNING;
> - }
> -
> - if (unlikely(reg == SDHCI_SLOT_INT_STATUS)) {
> - u32 prss = val;
> - /* fake chips as V3.0 host conreoller */
> - prss &= ~(0xFF << 16);
> - val = prss | (SDHCI_SPEC_300 << 16);
> - }
> - return val;
> -}
> -
> -static u16 sdhci_sirf_readw_le(struct sdhci_host *host, int reg)
> -{
> - u16 ret = 0;
> -
> - ret = readw(host->ioaddr + reg);
> -
> - if (unlikely(reg == SDHCI_HOST_VERSION)) {
> - ret = readw(host->ioaddr + SDHCI_HOST_VERSION);
> - ret |= SDHCI_SPEC_300;
> - }
> -
> - return ret;
> -}
> -
> -static int sdhci_sirf_execute_tuning(struct sdhci_host *host, u32 opcode)
> -{
> - int tuning_seq_cnt = 3;
> - int phase;
> - u8 tuned_phase_cnt = 0;
> - int rc = 0, longest_range = 0;
> - int start = -1, end = 0, tuning_value = -1, range = 0;
> - u16 clock_setting;
> - struct mmc_host *mmc = host->mmc;
> -
> - clock_setting = sdhci_readw(host, SDHCI_CLK_DELAY_SETTING);
> - clock_setting &= ~0x3fff;
> -
> -retry:
> - phase = 0;
> - tuned_phase_cnt = 0;
> - do {
> - sdhci_writel(host,
> - clock_setting | phase,
> - SDHCI_CLK_DELAY_SETTING);
> -
> - if (!mmc_send_tuning(mmc, opcode, NULL)) {
> - /* Tuning is successful at this tuning point */
> - tuned_phase_cnt++;
> - dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
> - mmc_hostname(mmc), phase);
> - if (start == -1)
> - start = phase;
> - end = phase;
> - range++;
> - if (phase == (SIRF_TUNING_COUNT - 1)
> - && range > longest_range)
> - tuning_value = (start + end) / 2;
> - } else {
> - dev_dbg(mmc_dev(mmc), "%s: Found bad phase = %d\n",
> - mmc_hostname(mmc), phase);
> - if (range > longest_range) {
> - tuning_value = (start + end) / 2;
> - longest_range = range;
> - }
> - start = -1;
> - end = range = 0;
> - }
> - } while (++phase < SIRF_TUNING_COUNT);
> -
> - if (tuned_phase_cnt && tuning_value > 0) {
> - /*
> - * Finally set the selected phase in delay
> - * line hw block.
> - */
> - phase = tuning_value;
> - sdhci_writel(host,
> - clock_setting | phase,
> - SDHCI_CLK_DELAY_SETTING);
> -
> - dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
> - mmc_hostname(mmc), phase);
> - } else {
> - if (--tuning_seq_cnt)
> - goto retry;
> - /* Tuning failed */
> - dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
> - mmc_hostname(mmc));
> - rc = -EIO;
> - }
> -
> - return rc;
> -}
> -
> -static const struct sdhci_ops sdhci_sirf_ops = {
> - .read_l = sdhci_sirf_readl_le,
> - .read_w = sdhci_sirf_readw_le,
> - .platform_execute_tuning = sdhci_sirf_execute_tuning,
> - .set_clock = sdhci_set_clock,
> - .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> - .set_bus_width = sdhci_sirf_set_bus_width,
> - .reset = sdhci_reset,
> - .set_uhs_signaling = sdhci_set_uhs_signaling,
> -};
> -
> -static const struct sdhci_pltfm_data sdhci_sirf_pdata = {
> - .ops = &sdhci_sirf_ops,
> - .quirks = SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
> - SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
> - SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> - SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
> - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
> -};
> -
> -static int sdhci_sirf_probe(struct platform_device *pdev)
> -{
> - struct sdhci_host *host;
> - struct sdhci_pltfm_host *pltfm_host;
> - struct clk *clk;
> - int ret;
> -
> - clk = devm_clk_get(&pdev->dev, NULL);
> - if (IS_ERR(clk)) {
> - dev_err(&pdev->dev, "unable to get clock");
> - return PTR_ERR(clk);
> - }
> -
> - host = sdhci_pltfm_init(pdev, &sdhci_sirf_pdata, 0);
> - if (IS_ERR(host))
> - return PTR_ERR(host);
> -
> - pltfm_host = sdhci_priv(host);
> - pltfm_host->clk = clk;
> -
> - sdhci_get_of_property(pdev);
> -
> - ret = clk_prepare_enable(pltfm_host->clk);
> - if (ret)
> - goto err_clk_prepare;
> -
> - ret = sdhci_add_host(host);
> - if (ret)
> - goto err_sdhci_add;
> -
> - /*
> - * We must request the IRQ after sdhci_add_host(), as the tasklet only
> - * gets setup in sdhci_add_host() and we oops.
> - */
> - ret = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0);
> - if (ret == -EPROBE_DEFER)
> - goto err_request_cd;
> - if (!ret)
> - mmc_gpiod_request_cd_irq(host->mmc);
> -
> - return 0;
> -
> -err_request_cd:
> - sdhci_remove_host(host, 0);
> -err_sdhci_add:
> - clk_disable_unprepare(pltfm_host->clk);
> -err_clk_prepare:
> - sdhci_pltfm_free(pdev);
> - return ret;
> -}
> -
> -static const struct of_device_id sdhci_sirf_of_match[] = {
> - { .compatible = "sirf,prima2-sdhc" },
> - { }
> -};
> -MODULE_DEVICE_TABLE(of, sdhci_sirf_of_match);
> -
> -static struct platform_driver sdhci_sirf_driver = {
> - .driver = {
> - .name = "sdhci-sirf",
> - .probe_type = PROBE_PREFER_ASYNCHRONOUS,
> - .of_match_table = sdhci_sirf_of_match,
> - .pm = &sdhci_pltfm_pmops,
> - },
> - .probe = sdhci_sirf_probe,
> - .remove = sdhci_pltfm_unregister,
> -};
> -
> -module_platform_driver(sdhci_sirf_driver);
> -
> -MODULE_DESCRIPTION("SDHCI driver for SiRFprimaII/SiRFmarco");
> -MODULE_AUTHOR("Barry Song <[email protected]>");
> -MODULE_LICENSE("GPL v2");
> --
> 2.29.2
>
On Wed, 20 Jan 2021 at 15:28, Arnd Bergmann <[email protected]> wrote:
>
> From: Arnd Bergmann <[email protected]>
>
> A few Arm platforms are getting removed in v5.12, this removes
> the corresponding mmc drivers.
>
> Link: https://lore.kernel.org/linux-arm-kernel/[email protected]/T/
>
>
> Arnd Bergmann (2):
> mmc: remove dw_mmc-zx driver
> mmc: remove sirf prima/atlas driver
>
> .../devicetree/bindings/mmc/sdhci-sirf.txt | 18 --
> .../devicetree/bindings/mmc/zx-dw-mshc.txt | 31 ---
> drivers/mmc/host/Kconfig | 21 --
> drivers/mmc/host/Makefile | 2 -
> drivers/mmc/host/dw_mmc-zx.c | 234 -----------------
> drivers/mmc/host/dw_mmc-zx.h | 32 ---
> drivers/mmc/host/sdhci-sirf.c | 235 ------------------
> 7 files changed, 573 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-sirf.txt
> delete mode 100644 Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
> delete mode 100644 drivers/mmc/host/dw_mmc-zx.c
> delete mode 100644 drivers/mmc/host/dw_mmc-zx.h
> delete mode 100644 drivers/mmc/host/sdhci-sirf.c
Applied for next, thanks!
Kind regards
Uffe