The vendor kernel sets a previously unknown clock gating bit in the
VIVS_PM_MODULE_CONTROLS register to disable SH_EU clock gating.
Import new headers from rnndb for the definition and set the bit
for the VIPNano-Si+ NPU on i.MX8MP and other affected cores.
Signed-off-by: Philipp Zabel <[email protected]>
---
Changes in v2:
- Add patch to turn etnaviv_is_model_rev() into a function.
- Use model numbers instead of made up GCxxxx model names.
- Also disable SH_EU clock gating on other models/revisions listed in the
vendor kernel.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Philipp Zabel (3):
drm/etnaviv: Update hardware headers from rnndb
drm/etnaviv: Turn etnaviv_is_model_rev() into a function
drm/etnaviv: Disable SH_EU clock gating on VIPNano-Si+
drivers/gpu/drm/etnaviv/cmdstream.xml.h | 52 ++++++++++++++--
drivers/gpu/drm/etnaviv/common.xml.h | 12 ++--
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 72 +++++++++++++----------
drivers/gpu/drm/etnaviv/state.xml.h | 101 +++++++++++++++++++++++++++-----
drivers/gpu/drm/etnaviv/state_blt.xml.h | 20 +++----
drivers/gpu/drm/etnaviv/state_hi.xml.h | 28 +++++----
6 files changed, 210 insertions(+), 75 deletions(-)
---
base-commit: 6613476e225e090cc9aad49be7fa504e290dd33d
change-id: 20240124-etnaviv-npu-627f6881322c
Best regards,
--
Philipp Zabel <[email protected]>
Turn the etnaviv_is_model_rev() macro into a static inline function.
Use the raw model number as a parameter instead of the chipModel_GCxxxx
defines. This reduces synchronization requirements for the generated
headers. For newer hardware, the GCxxxx names are not the correct model
names anyway. For example, model 0x8000 NPUs are called VIPNano-QI/SI(+)
by VeriSilicon.
Signed-off-by: Philipp Zabel <[email protected]>
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 66 ++++++++++++++++++-----------------
1 file changed, 34 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
index 9b8445d2a128..c61d50dd3829 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
@@ -172,10 +172,12 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
return 0;
}
+static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
+{
+ return gpu->identity.model == model &&
+ gpu->identity.revision == revision;
+}
-#define etnaviv_is_model_rev(gpu, mod, rev) \
- ((gpu)->identity.model == chipModel_##mod && \
- (gpu)->identity.revision == rev)
#define etnaviv_field(val, field) \
(((val) & field##__MASK) >> field##__SHIFT)
@@ -281,7 +283,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
switch (gpu->identity.instruction_count) {
case 0:
- if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
+ if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
gpu->identity.model == chipModel_GC880)
gpu->identity.instruction_count = 512;
else
@@ -315,17 +317,17 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
* For some cores, two varyings are consumed for position, so the
* maximum varying count needs to be reduced by one.
*/
- if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
- etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
- etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
- etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
- etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
- etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
- etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
- etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
- etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
- etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
- etnaviv_is_model_rev(gpu, GC880, 0x5106))
+ if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||
+ etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
+ etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||
+ etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
+ etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||
+ etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||
+ etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||
+ etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
+ etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||
+ etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||
+ etnaviv_is_model_rev(gpu, 0x880, 0x5106))
gpu->identity.varyings_count -= 1;
}
@@ -351,7 +353,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
* Reading these two registers on GC600 rev 0x19 result in a
* unhandled fault: external abort on non-linefetch
*/
- if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
+ if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {
gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
}
@@ -368,7 +370,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
}
/* Another special case */
- if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
+ if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {
u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
if (chipDate == 0x20080814 && chipTime == 0x12051100) {
@@ -387,15 +389,15 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
* Fix model/rev here, so all other places can refer to this
* core by its real identity.
*/
- if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
+ if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {
gpu->identity.model = chipModel_GC3000;
gpu->identity.revision &= 0xffff;
}
- if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
+ if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))
gpu->identity.eco_id = 1;
- if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
+ if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))
gpu->identity.eco_id = 1;
}
@@ -630,14 +632,14 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
pmc |= BIT(15); /* Unknown bit */
/* Disable TX clock gating on affected core revisions. */
- if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
- etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
- etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
- etnaviv_is_model_rev(gpu, GC2000, 0x6203))
+ if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
+ etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
+ etnaviv_is_model_rev(gpu, 0x2000, 0x6202) ||
+ etnaviv_is_model_rev(gpu, 0x2000, 0x6203))
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
/* Disable SE and RA clock gating on affected core revisions. */
- if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
+ if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))
pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
@@ -690,14 +692,14 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
*/
u32 pulse_eater = 0x01590880;
- if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
- etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
+ if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
+ etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {
pulse_eater |= BIT(23);
}
- if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
- etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
+ if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||
+ etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {
pulse_eater &= ~BIT(16);
pulse_eater |= BIT(17);
}
@@ -718,8 +720,8 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
gpu->state == ETNA_GPU_STATE_RESET));
- if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
- etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
+ if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||
+ etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&
gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
u32 mc_memory_debug;
@@ -745,7 +747,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
VIVS_HI_AXI_CONFIG_ARCACHE(2));
/* GC2000 rev 5108 needs a special bus config */
- if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
+ if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {
u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
--
2.39.2
Update the state HI header from the rnndb commit
8d7ee714cfe2 ("Merge pull request #24 from pH5/unknown-3950").
Signed-off-by: Philipp Zabel <[email protected]>
---
drivers/gpu/drm/etnaviv/cmdstream.xml.h | 52 ++++++++++++++--
drivers/gpu/drm/etnaviv/common.xml.h | 12 ++--
drivers/gpu/drm/etnaviv/state.xml.h | 101 +++++++++++++++++++++++++++-----
drivers/gpu/drm/etnaviv/state_blt.xml.h | 20 +++----
drivers/gpu/drm/etnaviv/state_hi.xml.h | 28 +++++----
5 files changed, 170 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/cmdstream.xml.h b/drivers/gpu/drm/etnaviv/cmdstream.xml.h
index 65f1ba1099bd..a96597a27ae2 100644
--- a/drivers/gpu/drm/etnaviv/cmdstream.xml.h
+++ b/drivers/gpu/drm/etnaviv/cmdstream.xml.h
@@ -8,11 +8,11 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- cmdstream.xml ( 14094 bytes, from 2016-11-11 06:55:14)
-- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
-- common.xml ( 23344 bytes, from 2016-11-10 15:14:07)
+- cmdstream.xml ( 16933 bytes, from 2023-12-11 15:50:17)
+- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
+- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
-Copyright (C) 2012-2016 by the following authors:
+Copyright (C) 2012-2023 by the following authors:
- Wladimir J. van der Laan <[email protected]>
- Christian Gmeiner <[email protected]>
- Lucas Stach <[email protected]>
@@ -52,6 +52,9 @@ DEALINGS IN THE SOFTWARE.
#define FE_OPCODE_RETURN 0x0000000b
#define FE_OPCODE_DRAW_INSTANCED 0x0000000c
#define FE_OPCODE_CHIP_SELECT 0x0000000d
+#define FE_OPCODE_WAIT_FENCE 0x0000000f
+#define FE_OPCODE_DRAW_INDIRECT 0x00000010
+#define FE_OPCODE_SNAP_PAGES 0x00000013
#define PRIMITIVE_TYPE_POINTS 0x00000001
#define PRIMITIVE_TYPE_LINES 0x00000002
#define PRIMITIVE_TYPE_LINE_STRIP 0x00000003
@@ -192,6 +195,9 @@ DEALINGS IN THE SOFTWARE.
#define VIV_FE_STALL_TOKEN_TO__MASK 0x00001f00
#define VIV_FE_STALL_TOKEN_TO__SHIFT 8
#define VIV_FE_STALL_TOKEN_TO(x) (((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)
+#define VIV_FE_STALL_TOKEN_UNK28__MASK 0x30000000
+#define VIV_FE_STALL_TOKEN_UNK28__SHIFT 28
+#define VIV_FE_STALL_TOKEN_UNK28(x) (((x) << VIV_FE_STALL_TOKEN_UNK28__SHIFT) & VIV_FE_STALL_TOKEN_UNK28__MASK)
#define VIV_FE_CALL 0x00000000
@@ -266,5 +272,43 @@ DEALINGS IN THE SOFTWARE.
#define VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT 0
#define VIV_FE_DRAW_INSTANCED_START_INDEX(x) (((x) << VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT) & VIV_FE_DRAW_INSTANCED_START_INDEX__MASK)
+#define VIV_FE_WAIT_FENCE 0x00000000
+
+#define VIV_FE_WAIT_FENCE_HEADER 0x00000000
+#define VIV_FE_WAIT_FENCE_HEADER_OP__MASK 0xf8000000
+#define VIV_FE_WAIT_FENCE_HEADER_OP__SHIFT 27
+#define VIV_FE_WAIT_FENCE_HEADER_OP_WAIT_FENCE 0x78000000
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK 0x00030000
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT 16
+#define VIV_FE_WAIT_FENCE_HEADER_UNK16(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK)
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK 0x0000ffff
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT 0
+#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK)
+
+#define VIV_FE_WAIT_FENCE_ADDRESS 0x00000004
+
+#define VIV_FE_DRAW_INDIRECT 0x00000000
+
+#define VIV_FE_DRAW_INDIRECT_HEADER 0x00000000
+#define VIV_FE_DRAW_INDIRECT_HEADER_OP__MASK 0xf8000000
+#define VIV_FE_DRAW_INDIRECT_HEADER_OP__SHIFT 27
+#define VIV_FE_DRAW_INDIRECT_HEADER_OP_DRAW_INDIRECT 0x80000000
+#define VIV_FE_DRAW_INDIRECT_HEADER_INDEXED 0x00000100
+#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK 0x0000000f
+#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT 0
+#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE(x) (((x) << VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT) & VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK)
+
+#define VIV_FE_DRAW_INDIRECT_ADDRESS 0x00000004
+
+#define VIV_FE_SNAP_PAGES 0x00000000
+
+#define VIV_FE_SNAP_PAGES_HEADER 0x00000000
+#define VIV_FE_SNAP_PAGES_HEADER_OP__MASK 0xf8000000
+#define VIV_FE_SNAP_PAGES_HEADER_OP__SHIFT 27
+#define VIV_FE_SNAP_PAGES_HEADER_OP_SNAP_PAGES 0x98000000
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK 0x0000001f
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT 0
+#define VIV_FE_SNAP_PAGES_HEADER_UNK0(x) (((x) << VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT) & VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK)
+
#endif /* CMDSTREAM_XML */
diff --git a/drivers/gpu/drm/etnaviv/common.xml.h b/drivers/gpu/drm/etnaviv/common.xml.h
index 001faea80fef..07c0bf47d89f 100644
--- a/drivers/gpu/drm/etnaviv/common.xml.h
+++ b/drivers/gpu/drm/etnaviv/common.xml.h
@@ -8,12 +8,12 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- texdesc_3d.xml ( 3183 bytes, from 2017-12-18 16:51:59)
-- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
-- common.xml ( 35468 bytes, from 2018-01-22 13:48:54)
-- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
+- texdesc_3d.xml ( 3183 bytes, from 2022-11-18 09:38:25)
+- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
+- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
+- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
-Copyright (C) 2012-2018 by the following authors:
+Copyright (C) 2012-2023 by the following authors:
- Wladimir J. van der Laan <[email protected]>
- Christian Gmeiner <[email protected]>
- Lucas Stach <[email protected]>
@@ -65,6 +65,7 @@ DEALINGS IN THE SOFTWARE.
#define chipModel_GC520 0x00000520
#define chipModel_GC530 0x00000530
#define chipModel_GC600 0x00000600
+#define chipModel_GC620 0x00000620
#define chipModel_GC700 0x00000700
#define chipModel_GC800 0x00000800
#define chipModel_GC860 0x00000860
@@ -481,5 +482,6 @@ DEALINGS IN THE SOFTWARE.
#define chipMinorFeatures11_NN_INTERLEVE8 0x00000008
#define chipMinorFeatures11_TP_REORDER 0x00000010
#define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX 0x00000020
+#define chipMinorFeatures12_G2D_DEC400EX 0x00000020
#endif /* COMMON_XML */
diff --git a/drivers/gpu/drm/etnaviv/state.xml.h b/drivers/gpu/drm/etnaviv/state.xml.h
index 421cb7cc0053..573e39489a27 100644
--- a/drivers/gpu/drm/etnaviv/state.xml.h
+++ b/drivers/gpu/drm/etnaviv/state.xml.h
@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 26087 bytes, from 2017-12-18 16:51:59)
-- common.xml ( 35468 bytes, from 2018-01-22 13:48:54)
-- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
-- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01)
-- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
-- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56)
-- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59)
-- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59)
-- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56)
+- state.xml ( 29355 bytes, from 2024-01-19 10:18:54)
+- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
+- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
+- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17)
+- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
+- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03)
+- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54)
+- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09)
+- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32)
-Copyright (C) 2012-2017 by the following authors:
+Copyright (C) 2012-2024 by the following authors:
- Wladimir J. van der Laan <[email protected]>
- Christian Gmeiner <[email protected]>
- Lucas Stach <[email protected]>
@@ -55,6 +55,8 @@ DEALINGS IN THE SOFTWARE.
#define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
#define FE_DATA_TYPE_INT 0x00000004
#define FE_DATA_TYPE_UNSIGNED_INT 0x00000005
+#define FE_DATA_TYPE_INT_2_10_10_10_REV 0x00000006
+#define FE_DATA_TYPE_UNSIGNED_INT_2_10_10_10_REV 0x00000007
#define FE_DATA_TYPE_FLOAT 0x00000008
#define FE_DATA_TYPE_HALF_FLOAT 0x00000009
#define FE_DATA_TYPE_FIXED 0x0000000b
@@ -89,6 +91,7 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000
+#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND 0x00004000
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000
#define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16
@@ -209,7 +212,15 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0))
-#define VIVS_FE_HALTI5_UNK007C4 0x000007c4
+#define VIVS_FE_HALTI5_ID_CONFIG 0x000007c4
+#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE 0x00000001
+#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE 0x00000002
+#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK 0x0000ff00
+#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT 8
+#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK)
+#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK 0x00ff0000
+#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT 16
+#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK)
#define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0))
#define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004
@@ -232,6 +243,8 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8
+#define VIVS_FE_MULTI_CLUSTER_UNK007FC 0x000007fc
+
#define VIVS_GL 0x00000000
#define VIVS_GL_PIPE_SELECT 0x00003800
@@ -273,6 +286,7 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800
#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000
#define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000
+#define VIVS_GL_FLUSH_CACHE_UNK14 0x00004000
#define VIVS_GL_FLUSH_MMU 0x00003810
#define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001
@@ -282,6 +296,8 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010
#define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814
+#define VIVS_GL_VERTEX_ELEMENT_CONFIG_UNK0 0x00000001
+#define VIVS_GL_VERTEX_ELEMENT_CONFIG_REUSE 0x00000010
#define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818
#define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003
@@ -368,7 +384,7 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830
-#define VIVS_GL_UNK03834 0x00003834
+#define VIVS_GL_VARYING_NUM_COMPONENTS2 0x00003834
#define VIVS_GL_UNK03838 0x00003838
@@ -387,7 +403,16 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c
-#define VIVS_GL_HALTI5_UNK03884 0x00003884
+#define VIVS_GL_USC_CONTROL 0x00003884
+#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK 0x00000007
+#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT 0
+#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK)
+#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK 0x00000f00
+#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT 8
+#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK)
+#define VIVS_GL_USC_CONTROL_UNK16__MASK 0x001f0000
+#define VIVS_GL_USC_CONTROL_UNK16__SHIFT 16
+#define VIVS_GL_USC_CONTROL_UNK16(x) (((x) << VIVS_GL_USC_CONTROL_UNK16__SHIFT) & VIVS_GL_USC_CONTROL_UNK16__MASK)
#define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888
#define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f
@@ -421,7 +446,48 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_GL_SECURITY_UNK3904 0x00003904
+#define VIVS_GL_MULTI_CLUSTER_UNK3908 0x00003908
+#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK 0x00000007
+#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT 0
+#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK)
+
+#define VIVS_GL_MULTI_CLUSTER_UNK3910(i0) (0x00003910 + 0x4*(i0))
+#define VIVS_GL_MULTI_CLUSTER_UNK3910__ESIZE 0x00000004
+#define VIVS_GL_MULTI_CLUSTER_UNK3910__LEN 0x00000004
+#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK 0x000000ff
+#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT 0
+#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK)
+
+#define VIVS_GL_NN_CONFIG 0x00003930
+#define VIVS_GL_NN_CONFIG_UNK0__MASK 0x00000003
+#define VIVS_GL_NN_CONFIG_UNK0__SHIFT 0
+#define VIVS_GL_NN_CONFIG_UNK0(x) (((x) << VIVS_GL_NN_CONFIG_UNK0__SHIFT) & VIVS_GL_NN_CONFIG_UNK0__MASK)
+#define VIVS_GL_NN_CONFIG_DISABLE_ZDPN 0x00000004
+#define VIVS_GL_NN_CONFIG_DISABLE_SWTILING 0x00000008
+#define VIVS_GL_NN_CONFIG_SMALL_BATCH 0x00000010
+#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK 0x00000060
+#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT 5
+#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE(x) (((x) << VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT) & VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK)
+#define VIVS_GL_NN_CONFIG_UNK7 0x00000080
+#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK 0x00000f00
+#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT 8
+#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT(x) (((x) << VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT) & VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK)
+#define VIVS_GL_NN_CONFIG_UNK12 0x00001000
+
+#define VIVS_GL_SRAM_REMAP_ADDRESS 0x00003938
+
+#define VIVS_GL_OCB_REMAP_START 0x0000393c
+
+#define VIVS_GL_OCB_REMAP_END 0x00003940
+
+#define VIVS_GL_TP_CONFIG 0x0000394c
+
+#define VIVS_GL_UNK03950 0x00003950
+
#define VIVS_GL_UNK03A00 0x00003a00
+#define VIVS_GL_UNK03A00_UNK0__MASK 0x00000007
+#define VIVS_GL_UNK03A00_UNK0__SHIFT 0
+#define VIVS_GL_UNK03A00_UNK0(x) (((x) << VIVS_GL_UNK03A00_UNK0__SHIFT) & VIVS_GL_UNK03A00_UNK0__MASK)
#define VIVS_GL_UNK03A04 0x00003a04
@@ -451,7 +517,7 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0))
-#define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0))
+#define VIVS_NFE_VERTEX_STREAMS_VERTEX_DIVISOR(i0) (0x00014680 + 0x4*(i0))
#define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0))
@@ -498,5 +564,12 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_DUMMY_DUMMY 0x0003fffc
+#define VIVS_WD 0x00000000
+
+#define VIVS_WD_UNK18404 0x00018404
+#define VIVS_WD_UNK18404_UNK0__MASK 0x00000003
+#define VIVS_WD_UNK18404_UNK0__SHIFT 0
+#define VIVS_WD_UNK18404_UNK0(x) (((x) << VIVS_WD_UNK18404_UNK0__SHIFT) & VIVS_WD_UNK18404_UNK0__MASK)
+
#endif /* STATE_XML */
diff --git a/drivers/gpu/drm/etnaviv/state_blt.xml.h b/drivers/gpu/drm/etnaviv/state_blt.xml.h
index 0e8bcf9dcc93..380d3533d645 100644
--- a/drivers/gpu/drm/etnaviv/state_blt.xml.h
+++ b/drivers/gpu/drm/etnaviv/state_blt.xml.h
@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 26087 bytes, from 2017-12-18 16:51:59)
-- common.xml ( 35468 bytes, from 2018-01-22 13:48:54)
-- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
-- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01)
-- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
-- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56)
-- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59)
-- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59)
-- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56)
+- state.xml ( 29355 bytes, from 2024-01-19 10:18:54)
+- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
+- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
+- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17)
+- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
+- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03)
+- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54)
+- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09)
+- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32)
-Copyright (C) 2012-2017 by the following authors:
+Copyright (C) 2012-2023 by the following authors:
- Wladimir J. van der Laan <[email protected]>
- Christian Gmeiner <[email protected]>
- Lucas Stach <[email protected]>
diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h
index 94d5f33b1fd6..829bc528e618 100644
--- a/drivers/gpu/drm/etnaviv/state_hi.xml.h
+++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h
@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone git://0x04.net/rules-ng-ng
The rules-ng-ng source files this header was generated from are:
-- state.xml ( 27198 bytes, from 2022-04-22 10:35:24)
-- common.xml ( 35468 bytes, from 2020-10-28 12:56:03)
-- common_3d.xml ( 15058 bytes, from 2020-10-28 12:56:03)
-- state_hi.xml ( 34804 bytes, from 2022-12-02 09:06:28)
-- copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03)
-- state_2d.xml ( 51552 bytes, from 2020-10-28 12:56:03)
-- state_3d.xml ( 84445 bytes, from 2022-11-15 15:59:38)
-- state_blt.xml ( 14424 bytes, from 2022-11-07 11:18:41)
-- state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03)
+- state.xml ( 29355 bytes, from 2024-01-19 10:18:54)
+- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
+- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
+- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17)
+- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
+- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03)
+- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54)
+- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09)
+- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32)
-Copyright (C) 2012-2022 by the following authors:
+Copyright (C) 2012-2023 by the following authors:
- Wladimir J. van der Laan <[email protected]>
- Christian Gmeiner <[email protected]>
- Lucas Stach <[email protected]>
@@ -275,8 +275,10 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020
#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040
#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080
+#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU 0x00000400
#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000
#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000
+#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_NN 0x00400000
#define VIVS_PM_MODULE_STATUS 0x00000108
#define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001
@@ -620,5 +622,11 @@ DEALINGS IN THE SOFTWARE.
#define VIVS_MC_MC_AXI_SAMPLE_COUNT 0x00000574
+#define VIVS_DEC400EX 0x00000000
+
+#define VIVS_DEC400EX_UNK00800 0x00000800
+
+#define VIVS_DEC400EX_UNK00808 0x00000808
+
#endif /* STATE_HI_XML */
--
2.39.2
>
> Update the state HI header from the rnndb commit
> 8d7ee714cfe2 ("Merge pull request #24 from pH5/unknown-3950").
>
> Signed-off-by: Philipp Zabel <[email protected]>
You missed my R-b from the v1 series for this patch - please include
it the next time!
Reviewed-by: Christian Gmeiner <[email protected]>
> ---
> drivers/gpu/drm/etnaviv/cmdstream.xml.h | 52 ++++++++++++++--
> drivers/gpu/drm/etnaviv/common.xml.h | 12 ++--
> drivers/gpu/drm/etnaviv/state.xml.h | 101 +++++++++++++++++++++++++++-----
> drivers/gpu/drm/etnaviv/state_blt.xml.h | 20 +++----
> drivers/gpu/drm/etnaviv/state_hi.xml.h | 28 +++++----
> 5 files changed, 170 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/cmdstream.xml.h b/drivers/gpu/drm/etnaviv/cmdstream.xml.h
> index 65f1ba1099bd..a96597a27ae2 100644
> --- a/drivers/gpu/drm/etnaviv/cmdstream.xml.h
> +++ b/drivers/gpu/drm/etnaviv/cmdstream.xml.h
> @@ -8,11 +8,11 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone git://0x04.net/rules-ng-ng
>
> The rules-ng-ng source files this header was generated from are:
> -- cmdstream.xml ( 14094 bytes, from 2016-11-11 06:55:14)
> -- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22)
> -- common.xml ( 23344 bytes, from 2016-11-10 15:14:07)
> +- cmdstream.xml ( 16933 bytes, from 2023-12-11 15:50:17)
> +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
> +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
>
> -Copyright (C) 2012-2016 by the following authors:
> +Copyright (C) 2012-2023 by the following authors:
> - Wladimir J. van der Laan <[email protected]>
> - Christian Gmeiner <[email protected]>
> - Lucas Stach <[email protected]>
> @@ -52,6 +52,9 @@ DEALINGS IN THE SOFTWARE.
> #define FE_OPCODE_RETURN 0x0000000b
> #define FE_OPCODE_DRAW_INSTANCED 0x0000000c
> #define FE_OPCODE_CHIP_SELECT 0x0000000d
> +#define FE_OPCODE_WAIT_FENCE 0x0000000f
> +#define FE_OPCODE_DRAW_INDIRECT 0x00000010
> +#define FE_OPCODE_SNAP_PAGES 0x00000013
> #define PRIMITIVE_TYPE_POINTS 0x00000001
> #define PRIMITIVE_TYPE_LINES 0x00000002
> #define PRIMITIVE_TYPE_LINE_STRIP 0x00000003
> @@ -192,6 +195,9 @@ DEALINGS IN THE SOFTWARE.
> #define VIV_FE_STALL_TOKEN_TO__MASK 0x00001f00
> #define VIV_FE_STALL_TOKEN_TO__SHIFT 8
> #define VIV_FE_STALL_TOKEN_TO(x) (((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK)
> +#define VIV_FE_STALL_TOKEN_UNK28__MASK 0x30000000
> +#define VIV_FE_STALL_TOKEN_UNK28__SHIFT 28
> +#define VIV_FE_STALL_TOKEN_UNK28(x) (((x) << VIV_FE_STALL_TOKEN_UNK28__SHIFT) & VIV_FE_STALL_TOKEN_UNK28__MASK)
>
> #define VIV_FE_CALL 0x00000000
>
> @@ -266,5 +272,43 @@ DEALINGS IN THE SOFTWARE.
> #define VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT 0
> #define VIV_FE_DRAW_INSTANCED_START_INDEX(x) (((x) << VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT) & VIV_FE_DRAW_INSTANCED_START_INDEX__MASK)
>
> +#define VIV_FE_WAIT_FENCE 0x00000000
> +
> +#define VIV_FE_WAIT_FENCE_HEADER 0x00000000
> +#define VIV_FE_WAIT_FENCE_HEADER_OP__MASK 0xf8000000
> +#define VIV_FE_WAIT_FENCE_HEADER_OP__SHIFT 27
> +#define VIV_FE_WAIT_FENCE_HEADER_OP_WAIT_FENCE 0x78000000
> +#define VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK 0x00030000
> +#define VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT 16
> +#define VIV_FE_WAIT_FENCE_HEADER_UNK16(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK)
> +#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK 0x0000ffff
> +#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT 0
> +#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK)
> +
> +#define VIV_FE_WAIT_FENCE_ADDRESS 0x00000004
> +
> +#define VIV_FE_DRAW_INDIRECT 0x00000000
> +
> +#define VIV_FE_DRAW_INDIRECT_HEADER 0x00000000
> +#define VIV_FE_DRAW_INDIRECT_HEADER_OP__MASK 0xf8000000
> +#define VIV_FE_DRAW_INDIRECT_HEADER_OP__SHIFT 27
> +#define VIV_FE_DRAW_INDIRECT_HEADER_OP_DRAW_INDIRECT 0x80000000
> +#define VIV_FE_DRAW_INDIRECT_HEADER_INDEXED 0x00000100
> +#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK 0x0000000f
> +#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT 0
> +#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE(x) (((x) << VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT) & VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK)
> +
> +#define VIV_FE_DRAW_INDIRECT_ADDRESS 0x00000004
> +
> +#define VIV_FE_SNAP_PAGES 0x00000000
> +
> +#define VIV_FE_SNAP_PAGES_HEADER 0x00000000
> +#define VIV_FE_SNAP_PAGES_HEADER_OP__MASK 0xf8000000
> +#define VIV_FE_SNAP_PAGES_HEADER_OP__SHIFT 27
> +#define VIV_FE_SNAP_PAGES_HEADER_OP_SNAP_PAGES 0x98000000
> +#define VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK 0x0000001f
> +#define VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT 0
> +#define VIV_FE_SNAP_PAGES_HEADER_UNK0(x) (((x) << VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT) & VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK)
> +
>
> #endif /* CMDSTREAM_XML */
> diff --git a/drivers/gpu/drm/etnaviv/common.xml.h b/drivers/gpu/drm/etnaviv/common.xml.h
> index 001faea80fef..07c0bf47d89f 100644
> --- a/drivers/gpu/drm/etnaviv/common.xml.h
> +++ b/drivers/gpu/drm/etnaviv/common.xml.h
> @@ -8,12 +8,12 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone git://0x04.net/rules-ng-ng
>
> The rules-ng-ng source files this header was generated from are:
> -- texdesc_3d.xml ( 3183 bytes, from 2017-12-18 16:51:59)
> -- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
> -- common.xml ( 35468 bytes, from 2018-01-22 13:48:54)
> -- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
> +- texdesc_3d.xml ( 3183 bytes, from 2022-11-18 09:38:25)
> +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
> +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
> +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
>
> -Copyright (C) 2012-2018 by the following authors:
> +Copyright (C) 2012-2023 by the following authors:
> - Wladimir J. van der Laan <[email protected]>
> - Christian Gmeiner <[email protected]>
> - Lucas Stach <[email protected]>
> @@ -65,6 +65,7 @@ DEALINGS IN THE SOFTWARE.
> #define chipModel_GC520 0x00000520
> #define chipModel_GC530 0x00000530
> #define chipModel_GC600 0x00000600
> +#define chipModel_GC620 0x00000620
> #define chipModel_GC700 0x00000700
> #define chipModel_GC800 0x00000800
> #define chipModel_GC860 0x00000860
> @@ -481,5 +482,6 @@ DEALINGS IN THE SOFTWARE.
> #define chipMinorFeatures11_NN_INTERLEVE8 0x00000008
> #define chipMinorFeatures11_TP_REORDER 0x00000010
> #define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX 0x00000020
> +#define chipMinorFeatures12_G2D_DEC400EX 0x00000020
>
> #endif /* COMMON_XML */
> diff --git a/drivers/gpu/drm/etnaviv/state.xml.h b/drivers/gpu/drm/etnaviv/state.xml.h
> index 421cb7cc0053..573e39489a27 100644
> --- a/drivers/gpu/drm/etnaviv/state.xml.h
> +++ b/drivers/gpu/drm/etnaviv/state.xml.h
> @@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone git://0x04.net/rules-ng-ng
>
> The rules-ng-ng source files this header was generated from are:
> -- state.xml ( 26087 bytes, from 2017-12-18 16:51:59)
> -- common.xml ( 35468 bytes, from 2018-01-22 13:48:54)
> -- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
> -- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01)
> -- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
> -- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56)
> -- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59)
> -- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59)
> -- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56)
> +- state.xml ( 29355 bytes, from 2024-01-19 10:18:54)
> +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
> +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
> +- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17)
> +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
> +- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03)
> +- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54)
> +- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09)
> +- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32)
>
> -Copyright (C) 2012-2017 by the following authors:
> +Copyright (C) 2012-2024 by the following authors:
> - Wladimir J. van der Laan <[email protected]>
> - Christian Gmeiner <[email protected]>
> - Lucas Stach <[email protected]>
> @@ -55,6 +55,8 @@ DEALINGS IN THE SOFTWARE.
> #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003
> #define FE_DATA_TYPE_INT 0x00000004
> #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005
> +#define FE_DATA_TYPE_INT_2_10_10_10_REV 0x00000006
> +#define FE_DATA_TYPE_UNSIGNED_INT_2_10_10_10_REV 0x00000007
> #define FE_DATA_TYPE_FLOAT 0x00000008
> #define FE_DATA_TYPE_HALF_FLOAT 0x00000009
> #define FE_DATA_TYPE_FIXED 0x0000000b
> @@ -89,6 +91,7 @@ DEALINGS IN THE SOFTWARE.
> #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000
> #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14
> #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000
> +#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND 0x00004000
> #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000
> #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000
> #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16
> @@ -209,7 +212,15 @@ DEALINGS IN THE SOFTWARE.
>
> #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0))
>
> -#define VIVS_FE_HALTI5_UNK007C4 0x000007c4
> +#define VIVS_FE_HALTI5_ID_CONFIG 0x000007c4
> +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE 0x00000001
> +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE 0x00000002
> +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK 0x0000ff00
> +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT 8
> +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK)
> +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK 0x00ff0000
> +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT 16
> +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK)
>
> #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0))
> #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004
> @@ -232,6 +243,8 @@ DEALINGS IN THE SOFTWARE.
>
> #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8
>
> +#define VIVS_FE_MULTI_CLUSTER_UNK007FC 0x000007fc
> +
> #define VIVS_GL 0x00000000
>
> #define VIVS_GL_PIPE_SELECT 0x00003800
> @@ -273,6 +286,7 @@ DEALINGS IN THE SOFTWARE.
> #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800
> #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000
> #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000
> +#define VIVS_GL_FLUSH_CACHE_UNK14 0x00004000
>
> #define VIVS_GL_FLUSH_MMU 0x00003810
> #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001
> @@ -282,6 +296,8 @@ DEALINGS IN THE SOFTWARE.
> #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010
>
> #define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814
> +#define VIVS_GL_VERTEX_ELEMENT_CONFIG_UNK0 0x00000001
> +#define VIVS_GL_VERTEX_ELEMENT_CONFIG_REUSE 0x00000010
>
> #define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818
> #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003
> @@ -368,7 +384,7 @@ DEALINGS IN THE SOFTWARE.
>
> #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830
>
> -#define VIVS_GL_UNK03834 0x00003834
> +#define VIVS_GL_VARYING_NUM_COMPONENTS2 0x00003834
>
> #define VIVS_GL_UNK03838 0x00003838
>
> @@ -387,7 +403,16 @@ DEALINGS IN THE SOFTWARE.
>
> #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c
>
> -#define VIVS_GL_HALTI5_UNK03884 0x00003884
> +#define VIVS_GL_USC_CONTROL 0x00003884
> +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK 0x00000007
> +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT 0
> +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK)
> +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK 0x00000f00
> +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT 8
> +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK)
> +#define VIVS_GL_USC_CONTROL_UNK16__MASK 0x001f0000
> +#define VIVS_GL_USC_CONTROL_UNK16__SHIFT 16
> +#define VIVS_GL_USC_CONTROL_UNK16(x) (((x) << VIVS_GL_USC_CONTROL_UNK16__SHIFT) & VIVS_GL_USC_CONTROL_UNK16__MASK)
>
> #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888
> #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f
> @@ -421,7 +446,48 @@ DEALINGS IN THE SOFTWARE.
>
> #define VIVS_GL_SECURITY_UNK3904 0x00003904
>
> +#define VIVS_GL_MULTI_CLUSTER_UNK3908 0x00003908
> +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK 0x00000007
> +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT 0
> +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK)
> +
> +#define VIVS_GL_MULTI_CLUSTER_UNK3910(i0) (0x00003910 + 0x4*(i0))
> +#define VIVS_GL_MULTI_CLUSTER_UNK3910__ESIZE 0x00000004
> +#define VIVS_GL_MULTI_CLUSTER_UNK3910__LEN 0x00000004
> +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK 0x000000ff
> +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT 0
> +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK)
> +
> +#define VIVS_GL_NN_CONFIG 0x00003930
> +#define VIVS_GL_NN_CONFIG_UNK0__MASK 0x00000003
> +#define VIVS_GL_NN_CONFIG_UNK0__SHIFT 0
> +#define VIVS_GL_NN_CONFIG_UNK0(x) (((x) << VIVS_GL_NN_CONFIG_UNK0__SHIFT) & VIVS_GL_NN_CONFIG_UNK0__MASK)
> +#define VIVS_GL_NN_CONFIG_DISABLE_ZDPN 0x00000004
> +#define VIVS_GL_NN_CONFIG_DISABLE_SWTILING 0x00000008
> +#define VIVS_GL_NN_CONFIG_SMALL_BATCH 0x00000010
> +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK 0x00000060
> +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT 5
> +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE(x) (((x) << VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT) & VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK)
> +#define VIVS_GL_NN_CONFIG_UNK7 0x00000080
> +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK 0x00000f00
> +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT 8
> +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT(x) (((x) << VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT) & VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK)
> +#define VIVS_GL_NN_CONFIG_UNK12 0x00001000
> +
> +#define VIVS_GL_SRAM_REMAP_ADDRESS 0x00003938
> +
> +#define VIVS_GL_OCB_REMAP_START 0x0000393c
> +
> +#define VIVS_GL_OCB_REMAP_END 0x00003940
> +
> +#define VIVS_GL_TP_CONFIG 0x0000394c
> +
> +#define VIVS_GL_UNK03950 0x00003950
> +
> #define VIVS_GL_UNK03A00 0x00003a00
> +#define VIVS_GL_UNK03A00_UNK0__MASK 0x00000007
> +#define VIVS_GL_UNK03A00_UNK0__SHIFT 0
> +#define VIVS_GL_UNK03A00_UNK0(x) (((x) << VIVS_GL_UNK03A00_UNK0__SHIFT) & VIVS_GL_UNK03A00_UNK0__MASK)
>
> #define VIVS_GL_UNK03A04 0x00003a04
>
> @@ -451,7 +517,7 @@ DEALINGS IN THE SOFTWARE.
>
> #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0))
>
> -#define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0))
> +#define VIVS_NFE_VERTEX_STREAMS_VERTEX_DIVISOR(i0) (0x00014680 + 0x4*(i0))
>
> #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0))
>
> @@ -498,5 +564,12 @@ DEALINGS IN THE SOFTWARE.
>
> #define VIVS_DUMMY_DUMMY 0x0003fffc
>
> +#define VIVS_WD 0x00000000
> +
> +#define VIVS_WD_UNK18404 0x00018404
> +#define VIVS_WD_UNK18404_UNK0__MASK 0x00000003
> +#define VIVS_WD_UNK18404_UNK0__SHIFT 0
> +#define VIVS_WD_UNK18404_UNK0(x) (((x) << VIVS_WD_UNK18404_UNK0__SHIFT) & VIVS_WD_UNK18404_UNK0__MASK)
> +
>
> #endif /* STATE_XML */
> diff --git a/drivers/gpu/drm/etnaviv/state_blt.xml.h b/drivers/gpu/drm/etnaviv/state_blt.xml.h
> index 0e8bcf9dcc93..380d3533d645 100644
> --- a/drivers/gpu/drm/etnaviv/state_blt.xml.h
> +++ b/drivers/gpu/drm/etnaviv/state_blt.xml.h
> @@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone git://0x04.net/rules-ng-ng
>
> The rules-ng-ng source files this header was generated from are:
> -- state.xml ( 26087 bytes, from 2017-12-18 16:51:59)
> -- common.xml ( 35468 bytes, from 2018-01-22 13:48:54)
> -- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59)
> -- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01)
> -- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56)
> -- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56)
> -- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59)
> -- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59)
> -- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56)
> +- state.xml ( 29355 bytes, from 2024-01-19 10:18:54)
> +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
> +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
> +- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17)
> +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
> +- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03)
> +- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54)
> +- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09)
> +- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32)
>
> -Copyright (C) 2012-2017 by the following authors:
> +Copyright (C) 2012-2023 by the following authors:
> - Wladimir J. van der Laan <[email protected]>
> - Christian Gmeiner <[email protected]>
> - Lucas Stach <[email protected]>
> diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h
> index 94d5f33b1fd6..829bc528e618 100644
> --- a/drivers/gpu/drm/etnaviv/state_hi.xml.h
> +++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h
> @@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
> git clone git://0x04.net/rules-ng-ng
>
> The rules-ng-ng source files this header was generated from are:
> -- state.xml ( 27198 bytes, from 2022-04-22 10:35:24)
> -- common.xml ( 35468 bytes, from 2020-10-28 12:56:03)
> -- common_3d.xml ( 15058 bytes, from 2020-10-28 12:56:03)
> -- state_hi.xml ( 34804 bytes, from 2022-12-02 09:06:28)
> -- copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03)
> -- state_2d.xml ( 51552 bytes, from 2020-10-28 12:56:03)
> -- state_3d.xml ( 84445 bytes, from 2022-11-15 15:59:38)
> -- state_blt.xml ( 14424 bytes, from 2022-11-07 11:18:41)
> -- state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03)
> +- state.xml ( 29355 bytes, from 2024-01-19 10:18:54)
> +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32)
> +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24)
> +- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17)
> +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32)
> +- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03)
> +- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54)
> +- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09)
> +- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32)
>
> -Copyright (C) 2012-2022 by the following authors:
> +Copyright (C) 2012-2023 by the following authors:
> - Wladimir J. van der Laan <[email protected]>
> - Christian Gmeiner <[email protected]>
> - Lucas Stach <[email protected]>
> @@ -275,8 +275,10 @@ DEALINGS IN THE SOFTWARE.
> #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020
> #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040
> #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080
> +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU 0x00000400
> #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000
> #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000
> +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_NN 0x00400000
>
> #define VIVS_PM_MODULE_STATUS 0x00000108
> #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001
> @@ -620,5 +622,11 @@ DEALINGS IN THE SOFTWARE.
>
> #define VIVS_MC_MC_AXI_SAMPLE_COUNT 0x00000574
>
> +#define VIVS_DEC400EX 0x00000000
> +
> +#define VIVS_DEC400EX_UNK00800 0x00000800
> +
> +#define VIVS_DEC400EX_UNK00808 0x00000808
> +
>
> #endif /* STATE_HI_XML */
>
> --
> 2.39.2
>
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
On Do, 2024-01-25 at 17:14 +0100, Christian Gmeiner wrote:
> >
> > Update the state HI header from the rnndb commit
> > 8d7ee714cfe2 ("Merge pull request #24 from pH5/unknown-3950").
> >
> > Signed-off-by: Philipp Zabel <[email protected]>
>
> You missed my R-b from the v1 series for this patch - please include
> it the next time!
>
> Reviewed-by: Christian Gmeiner <[email protected]>
Sorry, I'm trying the b4 prep/send workflow and hadn't internalized yet
that "b4 trailers -u" is still a necessary manual step.
regards
Philipp
Hi Philipp
>
> Turn the etnaviv_is_model_rev() macro into a static inline function.
> Use the raw model number as a parameter instead of the chipModel_GCxxxx
> defines. This reduces synchronization requirements for the generated
> headers. For newer hardware, the GCxxxx names are not the correct model
> names anyway. For example, model 0x8000 NPUs are called VIPNano-QI/SI(+)
> by VeriSilicon.
To catch up with your NPU example Vivante's kernel driver has such
lines in its hw database [0]
/* vipnano-si+ */
{
0x8000, /* ChipID */
0x8002, /* ChipRevision */
0x5080009, /* ProductID */
0x6000000, /* EcoID */
0x9f, /* CustomerID */
...
I think in reality this function should be called
etnaviv_is_chip_rev(..) or etnaviv_is_id_rev(..). That would be
semantically correct and we could even stick the the current macro
(that gets renamed) and with the current
GCxxx defines.
[0]: https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/mxc/gpu-viv/hal/kernel/inc/gc_feature_database.h#L22373
>
> Signed-off-by: Philipp Zabel <[email protected]>
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 66 ++++++++++++++++++-----------------
> 1 file changed, 34 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index 9b8445d2a128..c61d50dd3829 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -172,10 +172,12 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
> return 0;
> }
>
> +static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
> +{
> + return gpu->identity.model == model &&
> + gpu->identity.revision == revision;
> +}
>
> -#define etnaviv_is_model_rev(gpu, mod, rev) \
> - ((gpu)->identity.model == chipModel_##mod && \
> - (gpu)->identity.revision == rev)
> #define etnaviv_field(val, field) \
> (((val) & field##__MASK) >> field##__SHIFT)
>
> @@ -281,7 +283,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
>
> switch (gpu->identity.instruction_count) {
> case 0:
> - if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
> + if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
> gpu->identity.model == chipModel_GC880)
> gpu->identity.instruction_count = 512;
> else
> @@ -315,17 +317,17 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
> * For some cores, two varyings are consumed for position, so the
> * maximum varying count needs to be reduced by one.
> */
> - if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
> - etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
> - etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
> - etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
> - etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
> - etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
> - etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
> - etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
> - etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
> - etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
> - etnaviv_is_model_rev(gpu, GC880, 0x5106))
> + if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||
> + etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
> + etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||
> + etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
> + etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||
> + etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||
> + etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||
> + etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
> + etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||
> + etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||
> + etnaviv_is_model_rev(gpu, 0x880, 0x5106))
> gpu->identity.varyings_count -= 1;
> }
>
> @@ -351,7 +353,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
> * Reading these two registers on GC600 rev 0x19 result in a
> * unhandled fault: external abort on non-linefetch
> */
> - if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
> + if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {
> gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
> gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
> }
> @@ -368,7 +370,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
> }
>
> /* Another special case */
> - if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
> + if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {
> u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
>
> if (chipDate == 0x20080814 && chipTime == 0x12051100) {
> @@ -387,15 +389,15 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
> * Fix model/rev here, so all other places can refer to this
> * core by its real identity.
> */
> - if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
> + if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {
> gpu->identity.model = chipModel_GC3000;
> gpu->identity.revision &= 0xffff;
> }
>
> - if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
> + if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))
> gpu->identity.eco_id = 1;
>
> - if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
> + if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))
> gpu->identity.eco_id = 1;
> }
>
> @@ -630,14 +632,14 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
> pmc |= BIT(15); /* Unknown bit */
>
> /* Disable TX clock gating on affected core revisions. */
> - if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
> - etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
> - etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
> - etnaviv_is_model_rev(gpu, GC2000, 0x6203))
> + if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
> + etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
> + etnaviv_is_model_rev(gpu, 0x2000, 0x6202) ||
> + etnaviv_is_model_rev(gpu, 0x2000, 0x6203))
> pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
>
> /* Disable SE and RA clock gating on affected core revisions. */
> - if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
> + if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))
> pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
> VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
>
> @@ -690,14 +692,14 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
> */
> u32 pulse_eater = 0x01590880;
>
> - if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
> - etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
> + if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
> + etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {
> pulse_eater |= BIT(23);
>
> }
>
> - if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
> - etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
> + if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||
> + etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {
> pulse_eater &= ~BIT(16);
> pulse_eater |= BIT(17);
> }
> @@ -718,8 +720,8 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
> WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
> gpu->state == ETNA_GPU_STATE_RESET));
>
> - if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
> - etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
> + if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||
> + etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&
> gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
> u32 mc_memory_debug;
>
> @@ -745,7 +747,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
> VIVS_HI_AXI_CONFIG_ARCACHE(2));
>
> /* GC2000 rev 5108 needs a special bus config */
> - if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
> + if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {
> u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
> bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
> VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
>
> --
> 2.39.2
>
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
Am Donnerstag, dem 25.01.2024 um 17:27 +0100 schrieb Christian Gmeiner:
> Hi Philipp
>
> >
> > Turn the etnaviv_is_model_rev() macro into a static inline function.
> > Use the raw model number as a parameter instead of the chipModel_GCxxxx
> > defines. This reduces synchronization requirements for the generated
> > headers. For newer hardware, the GCxxxx names are not the correct model
> > names anyway. For example, model 0x8000 NPUs are called VIPNano-QI/SI(+)
> > by VeriSilicon.
>
> To catch up with your NPU example Vivante's kernel driver has such
> lines in its hw database [0]
>
> /* vipnano-si+ */
> {
> 0x8000, /* ChipID */
> 0x8002, /* ChipRevision */
> 0x5080009, /* ProductID */
> 0x6000000, /* EcoID */
> 0x9f, /* CustomerID */
> ...
>
> I think in reality this function should be called
> etnaviv_is_chip_rev(..) or etnaviv_is_id_rev(..). That would be
> semantically correct and we could even stick the the current macro
> (that gets renamed) and with the current
> GCxxx defines.
The value for what is called ChipID in the downstream driver is read
from a register which is called VIVS_HI_CHIP_MODEL in rnndb. I would
like to stay consistent by calling this model in the etnaviv driver.
I don't see any value in the GCxxx defines, which only add a (pretty)
prefix to a perfectly readable hex number, so I'm fine with changing
the current macro and getting rid of any usage of those defines in the
driver.
Regards,
Lucas
>
> [0]: https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/mxc/gpu-viv/hal/kernel/inc/gc_feature_database.h#L22373
>
> >
> > Signed-off-by: Philipp Zabel <[email protected]>
> > ---
> > drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 66 ++++++++++++++++++-----------------
> > 1 file changed, 34 insertions(+), 32 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> > index 9b8445d2a128..c61d50dd3829 100644
> > --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> > +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> > @@ -172,10 +172,12 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
> > return 0;
> > }
> >
> > +static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
> > +{
> > + return gpu->identity.model == model &&
> > + gpu->identity.revision == revision;
> > +}
> >
> > -#define etnaviv_is_model_rev(gpu, mod, rev) \
> > - ((gpu)->identity.model == chipModel_##mod && \
> > - (gpu)->identity.revision == rev)
> > #define etnaviv_field(val, field) \
> > (((val) & field##__MASK) >> field##__SHIFT)
> >
> > @@ -281,7 +283,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
> >
> > switch (gpu->identity.instruction_count) {
> > case 0:
> > - if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
> > + if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
> > gpu->identity.model == chipModel_GC880)
> > gpu->identity.instruction_count = 512;
> > else
> > @@ -315,17 +317,17 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
> > * For some cores, two varyings are consumed for position, so the
> > * maximum varying count needs to be reduced by one.
> > */
> > - if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
> > - etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
> > - etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
> > - etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
> > - etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
> > - etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
> > - etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
> > - etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
> > - etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
> > - etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
> > - etnaviv_is_model_rev(gpu, GC880, 0x5106))
> > + if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) ||
> > + etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
> > + etnaviv_is_model_rev(gpu, 0x4000, 0x5245) ||
> > + etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
> > + etnaviv_is_model_rev(gpu, 0x3000, 0x5435) ||
> > + etnaviv_is_model_rev(gpu, 0x2200, 0x5244) ||
> > + etnaviv_is_model_rev(gpu, 0x2100, 0x5108) ||
> > + etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
> > + etnaviv_is_model_rev(gpu, 0x1500, 0x5246) ||
> > + etnaviv_is_model_rev(gpu, 0x880, 0x5107) ||
> > + etnaviv_is_model_rev(gpu, 0x880, 0x5106))
> > gpu->identity.varyings_count -= 1;
> > }
> >
> > @@ -351,7 +353,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
> > * Reading these two registers on GC600 rev 0x19 result in a
> > * unhandled fault: external abort on non-linefetch
> > */
> > - if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) {
> > + if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) {
> > gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID);
> > gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID);
> > }
> > @@ -368,7 +370,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
> > }
> >
> > /* Another special case */
> > - if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
> > + if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) {
> > u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
> >
> > if (chipDate == 0x20080814 && chipTime == 0x12051100) {
> > @@ -387,15 +389,15 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
> > * Fix model/rev here, so all other places can refer to this
> > * core by its real identity.
> > */
> > - if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
> > + if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) {
> > gpu->identity.model = chipModel_GC3000;
> > gpu->identity.revision &= 0xffff;
> > }
> >
> > - if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617))
> > + if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617))
> > gpu->identity.eco_id = 1;
> >
> > - if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511))
> > + if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511))
> > gpu->identity.eco_id = 1;
> > }
> >
> > @@ -630,14 +632,14 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
> > pmc |= BIT(15); /* Unknown bit */
> >
> > /* Disable TX clock gating on affected core revisions. */
> > - if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
> > - etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
> > - etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||
> > - etnaviv_is_model_rev(gpu, GC2000, 0x6203))
> > + if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) ||
> > + etnaviv_is_model_rev(gpu, 0x2000, 0x5108) ||
> > + etnaviv_is_model_rev(gpu, 0x2000, 0x6202) ||
> > + etnaviv_is_model_rev(gpu, 0x2000, 0x6203))
> > pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
> >
> > /* Disable SE and RA clock gating on affected core revisions. */
> > - if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))
> > + if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202))
> > pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |
> > VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;
> >
> > @@ -690,14 +692,14 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
> > */
> > u32 pulse_eater = 0x01590880;
> >
> > - if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
> > - etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
> > + if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) ||
> > + etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) {
> > pulse_eater |= BIT(23);
> >
> > }
> >
> > - if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
> > - etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
> > + if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) ||
> > + etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) {
> > pulse_eater &= ~BIT(16);
> > pulse_eater |= BIT(17);
> > }
> > @@ -718,8 +720,8 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
> > WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED ||
> > gpu->state == ETNA_GPU_STATE_RESET));
> >
> > - if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
> > - etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
> > + if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) ||
> > + etnaviv_is_model_rev(gpu, 0x320, 0x5220)) &&
> > gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
> > u32 mc_memory_debug;
> >
> > @@ -745,7 +747,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
> > VIVS_HI_AXI_CONFIG_ARCACHE(2));
> >
> > /* GC2000 rev 5108 needs a special bus config */
> > - if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
> > + if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) {
> > u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
> > bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
> > VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
> >
> > --
> > 2.39.2
> >
>
>