LinuxLists.cc - [PATCH v2] PCI: cadence: Enable Controller to respond to received PTM Requests

2022-02-22 21:08:43

Subject: [PATCH v2] PCI: cadence: Enable Controller to respond to received PTM Requests

This enables the Controller [RP] to automatically respond with
Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
and PCI_PTM_CTRL_ENABLE bits are both set.

Signed-off-by: Christian Gmeiner <[email protected]>
---
drivers/pci/controller/cadence/pcie-cadence-host.c | 10 ++++++++++
drivers/pci/controller/cadence/pcie-cadence.h | 4 ++++
2 files changed, 14 insertions(+)

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index fb96d37a135c..940c7dd701d6 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
return ret;
}

+static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
+{
+ u32 val;
+
+ val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
+ cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
+}
+
static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
{
struct cdns_pcie *pcie = &rc->pcie;
@@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
if (rc->quirk_detect_quiet_flag)
cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);

+ cdns_pcie_host_enable_ptm_response(pcie);
+
ret = cdns_pcie_start_link(pcie);
if (ret) {
dev_err(dev, "Failed to start link\n");
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index c8a27b6290ce..1ffa8fa77a8a 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -116,6 +116,10 @@
#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
(((aperture) - 2) << ((bar) * 8))

+/* PTM Control Register */
+#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)
+#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
+
/*
* Endpoint Function Registers (PCI configuration space for endpoint functions)
*/
--
2.35.1

2022-03-11 22:02:57

by Christian Gmeiner

[permalink] [raw]

Subject: Re: [PATCH v2] PCI: cadence: Enable Controller to respond to received PTM Requests

Hi all

> This enables the Controller [RP] to automatically respond with
> Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
> and PCI_PTM_CTRL_ENABLE bits are both set.
>
> Signed-off-by: Christian Gmeiner <[email protected]>
> ---
> drivers/pci/controller/cadence/pcie-cadence-host.c | 10 ++++++++++
> drivers/pci/controller/cadence/pcie-cadence.h | 4 ++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index fb96d37a135c..940c7dd701d6 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
> return ret;
> }
>
> +static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
> +{
> + u32 val;
> +
> + val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
> + cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
> +}
> +
> static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
> {
> struct cdns_pcie *pcie = &rc->pcie;
> @@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> if (rc->quirk_detect_quiet_flag)
> cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
>
> + cdns_pcie_host_enable_ptm_response(pcie);
> +
> ret = cdns_pcie_start_link(pcie);
> if (ret) {
> dev_err(dev, "Failed to start link\n");
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index c8a27b6290ce..1ffa8fa77a8a 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -116,6 +116,10 @@
> #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
> (((aperture) - 2) << ((bar) * 8))
>
> +/* PTM Control Register */
> +#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)
> +#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
> +
> /*
> * Endpoint Function Registers (PCI configuration space for endpoint functions)
> */
> --
> 2.35.1
>

This patch should be ready to land - or is anything missing?

--
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy

2022-03-22 20:43:02

by Christian Gmeiner

[permalink] [raw]

Subject: Re: [PATCH v2] PCI: cadence: Enable Controller to respond to received PTM Requests

Am Do., 10. März 2022 um 13:14 Uhr schrieb Christian Gmeiner
<[email protected]>:
>
> Hi all
>
> > This enables the Controller [RP] to automatically respond with
> > Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
> > and PCI_PTM_CTRL_ENABLE bits are both set.
> >
> > Signed-off-by: Christian Gmeiner <[email protected]>
> > ---
> > drivers/pci/controller/cadence/pcie-cadence-host.c | 10 ++++++++++
> > drivers/pci/controller/cadence/pcie-cadence.h | 4 ++++
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > index fb96d37a135c..940c7dd701d6 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > @@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
> > return ret;
> > }
> >
> > +static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
> > +{
> > + u32 val;
> > +
> > + val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
> > + cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
> > +}
> > +
> > static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
> > {
> > struct cdns_pcie *pcie = &rc->pcie;
> > @@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> > if (rc->quirk_detect_quiet_flag)
> > cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
> >
> > + cdns_pcie_host_enable_ptm_response(pcie);
> > +
> > ret = cdns_pcie_start_link(pcie);
> > if (ret) {
> > dev_err(dev, "Failed to start link\n");
> > diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> > index c8a27b6290ce..1ffa8fa77a8a 100644
> > --- a/drivers/pci/controller/cadence/pcie-cadence.h
> > +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> > @@ -116,6 +116,10 @@
> > #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
> > (((aperture) - 2) << ((bar) * 8))
> >
> > +/* PTM Control Register */
> > +#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)
> > +#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
> > +
> > /*
> > * Endpoint Function Registers (PCI configuration space for endpoint functions)
> > */
> > --
> > 2.35.1
> >
>
> This patch should be ready to land - or is anything missing?
>

Gentle ping.

--
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy

2022-03-25 20:01:30

by Bjorn Helgaas

[permalink] [raw]

Subject: Re: [PATCH v2] PCI: cadence: Enable Controller to respond to received PTM Requests

On Tue, Mar 22, 2022 at 02:20:14PM +0100, Christian Gmeiner wrote:
> Am Do., 10. M?rz 2022 um 13:14 Uhr schrieb Christian Gmeiner
> <[email protected]>:
> >
> > Hi all
> >
> > > This enables the Controller [RP] to automatically respond with
> > > Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
> > > and PCI_PTM_CTRL_ENABLE bits are both set.
> > >
> > > Signed-off-by: Christian Gmeiner <[email protected]>

We're in the middle of the merge window right now, but I'm sure
Lorenzo will be able to look at it after -rc1. This looks fine to me.

> > > ---
> > > drivers/pci/controller/cadence/pcie-cadence-host.c | 10 ++++++++++
> > > drivers/pci/controller/cadence/pcie-cadence.h | 4 ++++
> > > 2 files changed, 14 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > > index fb96d37a135c..940c7dd701d6 100644
> > > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> > > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> > > @@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
> > > return ret;
> > > }
> > >
> > > +static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
> > > +{
> > > + u32 val;
> > > +
> > > + val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
> > > + cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);

Lorenzo will likely wrap this line to fit in 80 columns like the rest
of the file, or if you rebase to v5.18-rc1 and post a v3, you could do
so.

> > > +}
> > > +
> > > static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
> > > {
> > > struct cdns_pcie *pcie = &rc->pcie;
> > > @@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
> > > if (rc->quirk_detect_quiet_flag)
> > > cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
> > >
> > > + cdns_pcie_host_enable_ptm_response(pcie);
> > > +
> > > ret = cdns_pcie_start_link(pcie);
> > > if (ret) {
> > > dev_err(dev, "Failed to start link\n");
> > > diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> > > index c8a27b6290ce..1ffa8fa77a8a 100644
> > > --- a/drivers/pci/controller/cadence/pcie-cadence.h
> > > +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> > > @@ -116,6 +116,10 @@
> > > #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
> > > (((aperture) - 2) << ((bar) * 8))
> > >
> > > +/* PTM Control Register */
> > > +#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)
> > > +#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
> > > +
> > > /*
> > > * Endpoint Function Registers (PCI configuration space for endpoint functions)
> > > */
> > > --
> > > 2.35.1
> > >
> >
> > This patch should be ready to land - or is anything missing?
> >
>
> Gentle ping.
>
> --
> greets
> --
> Christian Gmeiner, MSc
>
> https://christian-gmeiner.info/privacypolicy

2022-04-17 16:54:51

by Christian Gmeiner

[permalink] [raw]

Subject: Re: [PATCH v2] PCI: cadence: Enable Controller to respond to received PTM Requests

> > >
> > > > This enables the Controller [RP] to automatically respond with
> > > > Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
> > > > and PCI_PTM_CTRL_ENABLE bits are both set.
> > > >
> > > > Signed-off-by: Christian Gmeiner <[email protected]>
>
> We're in the middle of the merge window right now, but I'm sure
> Lorenzo will be able to look at it after -rc1. This looks fine to me.
>

Another gentle ping :(

--
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy

2022-05-03 00:14:26

by Christian Gmeiner

[permalink] [raw]

Subject: Re: [PATCH v2] PCI: cadence: Enable Controller to respond to received PTM Requests

>
> > > >
> > > > > This enables the Controller [RP] to automatically respond with
> > > > > Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN
> > > > > and PCI_PTM_CTRL_ENABLE bits are both set.
> > > > >
> > > > > Signed-off-by: Christian Gmeiner <[email protected]>
> >
> > We're in the middle of the merge window right now, but I'm sure
> > Lorenzo will be able to look at it after -rc1. This looks fine to me.
> >
>
> Another gentle ping :(
>

Ping..
--
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info/privacypolicy