This patch series does the following
- Covert Zynq pinctrl driver binding file to yaml.
- Update the binding for Zynq pinctrl to replace the 'io-standard' with
'power-source' parameter as recommended by Linus during ZynqMP pinctrl
driver review(https://lkml.org/lkml/2021/3/25/278).
- Update the Zynq pinctrl the driver to remove custom pin
parameter(io-standard) and instead use generic parameter(power-source).
- Update Zynq dts files to replace 'io-standard' with 'power-source'.
Reason for adding the generic parameter 'power-source' in Zynq pinctrl driver
is to maintain common pin parameter across Xilinx Zynq and ZynqMP platforms
for power supply configuration.
Sai Krishna Potthuri (4):
dt-bindings: pinctrl: pinctrl-zynq: Convert to yaml
dt-bindings: pinctrl-zynq: Replace 'io-standard' with 'power-source'
pinctrl: pinctrl-zynq: Add support for 'power-source' parameter
arm: dts: zynq: Replace 'io-standard' with 'power-source' property
.../bindings/pinctrl/xlnx,zynq-pinctrl.txt | 105 ---------
.../bindings/pinctrl/xlnx,zynq-pinctrl.yaml | 214 ++++++++++++++++++
arch/arm/boot/dts/zynq-ebaz4205.dts | 8 +-
arch/arm/boot/dts/zynq-microzed.dts | 2 +-
arch/arm/boot/dts/zynq-zc702.dts | 20 +-
arch/arm/boot/dts/zynq-zc706.dts | 18 +-
drivers/pinctrl/pinctrl-zynq.c | 2 +
include/dt-bindings/pinctrl/pinctrl-zynq.h | 17 ++
8 files changed, 257 insertions(+), 129 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynq.h
--
2.17.1
Add support for generic pin parameter 'power-source'.
To maintain the backward compatibility, 'io-standard' parameter is still
supported in the driver.
Signed-off-by: Sai Krishna Potthuri <[email protected]>
---
drivers/pinctrl/pinctrl-zynq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-zynq.c b/drivers/pinctrl/pinctrl-zynq.c
index 5fb924a2eedd..a96af8a76a7a 100644
--- a/drivers/pinctrl/pinctrl-zynq.c
+++ b/drivers/pinctrl/pinctrl-zynq.c
@@ -1028,6 +1028,7 @@ static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
break;
}
case PIN_CONFIG_IOSTANDARD:
+ case PIN_CONFIG_POWER_SOURCE:
arg = zynq_pinconf_iostd_get(reg);
break;
default:
@@ -1078,6 +1079,7 @@ static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_IOSTANDARD:
+ case PIN_CONFIG_POWER_SOURCE:
if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
dev_warn(pctldev->dev,
"unsupported IO standard '%u'\n",
--
2.17.1
Replace custom pin configuration option 'io-standard' with generic property
'power-source' for Zynq pinctrl also add dt-binding file contains pin
configuration defines for Zynq pinctrl.
Signed-off-by: Sai Krishna Potthuri <[email protected]>
---
.../bindings/pinctrl/xlnx,zynq-pinctrl.yaml | 8 +++-----
include/dt-bindings/pinctrl/pinctrl-zynq.h | 17 +++++++++++++++++
2 files changed, 20 insertions(+), 5 deletions(-)
create mode 100644 include/dt-bindings/pinctrl/pinctrl-zynq.h
diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
index 2da1969e02ec..ac97dbf6998e 100644
--- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
@@ -156,10 +156,7 @@ patternProperties:
slew-rate:
enum: [0, 1]
- io-standard:
- description:
- Selects the IO standard for MIO pins, this is driver specific.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ power-source:
enum: [1, 2, 3, 4]
oneOf:
@@ -179,6 +176,7 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/pinctrl/pinctrl-zynq.h>
pinctrl0: pinctrl@700 {
compatible = "xlnx,zynq-pinctrl";
reg = <0x700 0x200>;
@@ -193,7 +191,7 @@ examples:
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
diff --git a/include/dt-bindings/pinctrl/pinctrl-zynq.h b/include/dt-bindings/pinctrl/pinctrl-zynq.h
new file mode 100644
index 000000000000..bbfc345f017d
--- /dev/null
+++ b/include/dt-bindings/pinctrl/pinctrl-zynq.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * MIO pin configuration defines for Xilinx Zynq
+ *
+ * Copyright (C) 2021 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H
+#define _DT_BINDINGS_PINCTRL_ZYNQ_H
+
+/* Configuration options for different power supplies */
+#define IO_STANDARD_LVCMOS18 1
+#define IO_STANDARD_LVCMOS25 2
+#define IO_STANDARD_LVCMOS33 3
+#define IO_STANDARD_HSTL 4
+
+#endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */
--
2.17.1
Replace 'io-standard' property with 'power-source' property in all zynq dts
files to be in sync with Zynq pinctrl driver.
Signed-off-by: Sai Krishna Potthuri <[email protected]>
---
arch/arm/boot/dts/zynq-ebaz4205.dts | 8 ++++----
arch/arm/boot/dts/zynq-microzed.dts | 2 +-
arch/arm/boot/dts/zynq-zc702.dts | 20 ++++++++++----------
arch/arm/boot/dts/zynq-zc706.dts | 18 +++++++++---------
4 files changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
index b0b836aedd76..be7eae611fb7 100644
--- a/arch/arm/boot/dts/zynq-ebaz4205.dts
+++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
@@ -57,7 +57,7 @@
conf {
groups = "gpio0_20_grp", "gpio0_32_grp";
- io-standard = <3>;
+ power-source = <3>;
slew-rate = <0>;
};
@@ -75,7 +75,7 @@
conf {
groups = "sdio0_2_grp";
- io-standard = <3>;
+ power-source = <3>;
slew-rate = <0>;
bias-disable;
};
@@ -87,7 +87,7 @@
conf-cd {
groups = "gpio0_34_grp";
- io-standard = <3>;
+ power-source = <3>;
slew-rate = <0>;
bias-high-impedance;
bias-pull-up;
@@ -102,7 +102,7 @@
conf {
groups = "uart1_4_grp";
- io-standard = <3>;
+ power-source = <3>;
slew-rate = <0>;
};
diff --git a/arch/arm/boot/dts/zynq-microzed.dts b/arch/arm/boot/dts/zynq-microzed.dts
index 6ed84fb15902..f44a4464943b 100644
--- a/arch/arm/boot/dts/zynq-microzed.dts
+++ b/arch/arm/boot/dts/zynq-microzed.dts
@@ -71,7 +71,7 @@
conf {
groups = "usb0_0_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
conf-rx {
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index cf70aff26c66..cf1e1cc3d132 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -206,7 +206,7 @@
conf {
groups = "can0_9_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
conf-rx {
@@ -229,7 +229,7 @@
conf {
groups = "ethernet0_0_grp";
slew-rate = <0>;
- io-standard = <4>;
+ power-source = <4>;
};
conf-rx {
@@ -252,7 +252,7 @@
conf-mdio {
groups = "mdio0_0_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
bias-disable;
};
};
@@ -270,7 +270,7 @@
"gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
"gpio0_13_grp", "gpio0_14_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
conf-pull-up {
@@ -294,7 +294,7 @@
groups = "i2c0_10_grp";
bias-pull-up;
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
};
@@ -307,7 +307,7 @@
conf {
groups = "sdio0_2_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
bias-disable;
};
@@ -321,7 +321,7 @@
bias-high-impedance;
bias-pull-up;
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
mux-wp {
@@ -334,7 +334,7 @@
bias-high-impedance;
bias-pull-up;
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
};
@@ -347,7 +347,7 @@
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
conf-rx {
@@ -370,7 +370,7 @@
conf {
groups = "usb0_0_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
conf-rx {
diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts
index 77943c16d33f..d21e3ae4ebb2 100644
--- a/arch/arm/boot/dts/zynq-zc706.dts
+++ b/arch/arm/boot/dts/zynq-zc706.dts
@@ -150,7 +150,7 @@
conf {
groups = "ethernet0_0_grp";
slew-rate = <0>;
- io-standard = <4>;
+ power-source = <4>;
};
conf-rx {
@@ -173,7 +173,7 @@
conf-mdio {
groups = "mdio0_0_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
bias-disable;
};
};
@@ -187,7 +187,7 @@
conf {
groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
conf-pull-up {
@@ -211,7 +211,7 @@
groups = "i2c0_10_grp";
bias-pull-up;
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
};
@@ -224,7 +224,7 @@
conf {
groups = "sdio0_2_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
bias-disable;
};
@@ -238,7 +238,7 @@
bias-high-impedance;
bias-pull-up;
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
mux-wp {
@@ -251,7 +251,7 @@
bias-high-impedance;
bias-pull-up;
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
};
@@ -264,7 +264,7 @@
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
conf-rx {
@@ -287,7 +287,7 @@
conf {
groups = "usb0_0_grp";
slew-rate = <0>;
- io-standard = <1>;
+ power-source = <1>;
};
conf-rx {
--
2.17.1
Convert the Zynq pinctrl binding file to yaml.
Signed-off-by: Sai Krishna Potthuri <[email protected]>
---
.../bindings/pinctrl/xlnx,zynq-pinctrl.txt | 105 ---------
.../bindings/pinctrl/xlnx,zynq-pinctrl.yaml | 216 ++++++++++++++++++
2 files changed, 216 insertions(+), 105 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
deleted file mode 100644
index f488b0f77406..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
+++ /dev/null
@@ -1,105 +0,0 @@
- Binding for Xilinx Zynq Pinctrl
-
-Required properties:
-- compatible: "xlnx,zynq-pinctrl"
-- syscon: phandle to SLCR
-- reg: Offset and length of pinctrl space in SLCR
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Zynq's pin configuration nodes act as a container for an arbitrary number of
-subnodes. Each of these subnodes represents some desired configuration for a
-pin, a group, or a list of pins or groups. This configuration can include the
-mux function to select on those pin(s)/group(s), and various pin configuration
-parameters, such as pull-up, slew rate, etc.
-
-Each configuration node can consist of multiple nodes describing the pinmux and
-pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
-
-The name of each subnode is not important; all subnodes should be enumerated
-and processed purely based on their content.
-
-Required properties for pinmux nodes are:
- - groups: A list of pinmux groups.
- - function: The name of a pinmux function to activate for the specified set
- of groups.
-
-Required properties for configuration nodes:
-One of:
- - pins: a list of pin names
- - groups: A list of pinmux groups.
-
-The following generic properties as defined in pinctrl-bindings.txt are valid
-to specify in a pinmux subnode:
- groups, function
-
-The following generic properties as defined in pinctrl-bindings.txt are valid
-to specify in a pinconf subnode:
- groups, pins, bias-disable, bias-high-impedance, bias-pull-up, slew-rate,
- low-power-disable, low-power-enable
-
- Valid arguments for 'slew-rate' are '0' and '1' to select between slow and fast
- respectively.
-
- Valid values for groups are:
- ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp, mdio1_0_grp,
- qspi0_0_grp, qspi1_0_grp, qspi_fbclk, qspi_cs1_grp, spi0_0_grp - spi0_2_grp,
- spi0_X_ssY (X=0..2, Y=0..2), spi1_0_grp - spi1_3_grp,
- spi1_X_ssY (X=0..3, Y=0..2), sdio0_0_grp - sdio0_2_grp,
- sdio1_0_grp - sdio1_3_grp, sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
- sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp, smc0_nor_addr25_grp, smc0_nand,
- can0_0_grp - can0_10_grp, can1_0_grp - can1_11_grp, uart0_0_grp - uart0_10_grp,
- uart1_0_grp - uart1_11_grp, i2c0_0_grp - i2c0_10_grp, i2c1_0_grp - i2c1_10_grp,
- ttc0_0_grp - ttc0_2_grp, ttc1_0_grp - ttc1_2_grp, swdt0_0_grp - swdt0_4_grp,
- gpio0_0_grp - gpio0_53_grp, usb0_0_grp, usb1_0_grp
-
- Valid values for pins are:
- MIO0 - MIO53
-
- Valid values for function are:
- ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk, qspi_cs1,
- spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc, sdio0_cd, sdio0_wp,
- sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
- smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0, can1, uart0, uart1,
- i2c0, i2c1, ttc0, ttc1, swdt0, gpio0, usb0, usb1
-
-The following driver-specific properties as defined here are valid to specify in
-a pin configuration subnode:
- - io-standard: Configure the pin to use the selected IO standard according to
- this mapping:
- 1: LVCMOS18
- 2: LVCMOS25
- 3: LVCMOS33
- 4: HSTL
-
-Example:
- pinctrl0: pinctrl@700 {
- compatible = "xlnx,pinctrl-zynq";
- reg = <0x700 0x200>;
- syscon = <&slcr>;
-
- pinctrl_uart1_default: uart1-default {
- mux {
- groups = "uart1_10_grp";
- function = "uart1";
- };
-
- conf {
- groups = "uart1_10_grp";
- slew-rate = <0>;
- io-standard = <1>;
- };
-
- conf-rx {
- pins = "MIO49";
- bias-high-impedance;
- };
-
- conf-tx {
- pins = "MIO48";
- bias-disable;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
new file mode 100644
index 000000000000..2da1969e02ec
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/xlnx,zynq-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq Pinctrl
+
+maintainers:
+ - Sai Krishna Potthuri <[email protected]>
+
+description: |
+ Please refer to pinctrl-bindings.txt in this directory for details of the
+ common pinctrl bindings used by client devices, including the meaning of the
+ phrase "pin configuration node".
+
+ Zynq's pin configuration nodes act as a container for an arbitrary number of
+ subnodes. Each of these subnodes represents some desired configuration for a
+ pin, a group, or a list of pins or groups. This configuration can include the
+ mux function to select on those pin(s)/group(s), and various pin configuration
+ parameters, such as pull-up, slew rate, etc.
+
+ Each configuration node can consist of multiple nodes describing the pinmux and
+ pinconf options. Those nodes can be pinmux nodes or pinconf nodes.
+
+ The name of each subnode is not important; all subnodes should be enumerated
+ and processed purely based on their content.
+
+properties:
+ compatible:
+ const: xlnx,zynq-pinctrl
+
+ reg:
+ description: Specifies the base address and size of the SLCR space.
+ maxItems: 1
+
+ syscon:
+ description:
+ phandle to the SLCR.
+
+patternProperties:
+ '^(.*-)?(default|gpio)$':
+ type: object
+ patternProperties:
+ '^mux':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for pin muxes,
+ which in turn use below standard properties.
+ $ref: pinmux-node.yaml#
+
+ properties:
+ groups:
+ description:
+ List of groups to select (either this or "pins" must be
+ specified), available groups for this subnode.
+ items:
+ enum: [ethernet0_0_grp, ethernet1_0_grp, mdio0_0_grp,
+ mdio1_0_grp, qspi0_0_grp, qspi1_0_grp, qspi_fbclk,
+ qspi_cs1_grp, spi0_0_grp, spi0_1_grp, spi0_2_grp,
+ spi0_0_ss0, spi0_0_ss1, spi0_0_ss2, spi0_1_ss0,
+ spi0_1_ss1, spi0_1_ss2, spi0_2_ss0, spi0_2_ss1,
+ spi0_2_ss2, spi1_0_grp, spi1_1_grp, spi1_2_grp,
+ spi1_3_grp, spi1_0_ss0, spi1_0_ss1, spi1_0_ss2,
+ spi1_1_ss0, spi1_1_ss1, spi1_1_ss2, spi1_2_ss0,
+ spi1_2_ss1, spi1_2_ss2, spi1_3_ss0, spi1_3_ss1,
+ spi1_3_ss2, sdio0_0_grp, sdio0_1_grp, sdio0_2_grp,
+ sdio1_0_grp, sdio1_1_grp, sdio1_2_grp, sdio1_3_grp,
+ sdio0_emio_wp, sdio0_emio_cd, sdio1_emio_wp,
+ sdio1_emio_cd, smc0_nor, smc0_nor_cs1_grp,
+ smc0_nor_addr25_grp, smc0_nand, can0_0_grp, can0_1_grp,
+ can0_2_grp, can0_3_grp, can0_4_grp, can0_5_grp,
+ can0_6_grp, can0_7_grp, can0_8_grp, can0_9_grp,
+ can0_10_grp, can1_0_grp, can1_1_grp, can1_2_grp,
+ can1_3_grp, can1_4_grp, can1_5_grp, can1_6_grp,
+ can1_7_grp, can1_8_grp, can1_9_grp, can1_10_grp,
+ can1_11_grp, uart0_0_grp, uart0_1_grp, uart0_2_grp,
+ uart0_3_grp, uart0_4_grp, uart0_5_grp, uart0_6_grp,
+ uart0_7_grp, uart0_8_grp, uart0_9_grp, uart0_10_grp,
+ uart1_0_grp, uart1_1_grp, uart1_2_grp, uart1_3_grp,
+ uart1_4_grp, uart1_5_grp, uart1_6_grp, uart1_7_grp,
+ uart1_8_grp, uart1_9_grp, uart1_10_grp, uart1_11_grp,
+ i2c0_0_grp, i2c0_1_grp, i2c0_2_grp, i2c0_3_grp,
+ i2c0_4_grp, i2c0_5_grp, i2c0_6_grp, i2c0_7_grp,
+ i2c0_8_grp, i2c0_9_grp, i2c0_10_grp, i2c1_0_grp,
+ i2c1_1_grp, i2c1_2_grp, i2c1_3_grp, i2c1_4_grp,
+ i2c1_5_grp, i2c1_6_grp, i2c1_7_grp, i2c1_8_grp,
+ i2c1_9_grp, i2c1_10_grp, ttc0_0_grp, ttc0_1_grp,
+ ttc0_2_grp, ttc1_0_grp, ttc1_1_grp, ttc1_2_grp,
+ swdt0_0_grp, swdt0_1_grp, swdt0_2_grp, swdt0_3_grp,
+ swdt0_4_grp, gpio0_0_grp, gpio0_1_grp, gpio0_2_grp,
+ gpio0_3_grp, gpio0_4_grp, gpio0_5_grp, gpio0_6_grp,
+ gpio0_7_grp, gpio0_8_grp, gpio0_9_grp, gpio0_10_grp,
+ gpio0_11_grp, gpio0_12_grp, gpio0_13_grp, gpio0_14_grp,
+ gpio0_15_grp, gpio0_16_grp, gpio0_17_grp, gpio0_18_grp,
+ gpio0_19_grp, gpio0_20_grp, gpio0_21_grp, gpio0_22_grp,
+ gpio0_23_grp, gpio0_24_grp, gpio0_25_grp, gpio0_26_grp,
+ gpio0_27_grp, gpio0_28_grp, gpio0_29_grp, gpio0_30_grp,
+ gpio0_31_grp, gpio0_32_grp, gpio0_33_grp, gpio0_34_grp,
+ gpio0_35_grp, gpio0_36_grp, gpio0_37_grp, gpio0_38_grp,
+ gpio0_39_grp, gpio0_40_grp, gpio0_41_grp, gpio0_42_grp,
+ gpio0_43_grp, gpio0_44_grp, gpio0_45_grp, gpio0_46_grp,
+ gpio0_47_grp, gpio0_48_grp, gpio0_49_grp, gpio0_50_grp,
+ gpio0_51_grp, gpio0_52_grp, gpio0_53_grp, usb0_0_grp,
+ usb1_0_grp]
+ maxItems: 54
+
+ function:
+ description:
+ Specify the alternative function to be configured for the
+ given pin groups.
+ enum: [ethernet0, ethernet1, mdio0, mdio1, qspi0, qspi1, qspi_fbclk,
+ qspi_cs1, spi0, spi0_ss, spi1, spi1_ss, sdio0, sdio0_pc,
+ sdio0_cd, sdio0_wp, sdio1, sdio1_pc, sdio1_cd, sdio1_wp,
+ smc0_nor, smc0_nor_cs1, smc0_nor_addr25, smc0_nand, can0,
+ can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0,
+ usb0, usb1]
+
+ required:
+ - groups
+ - function
+
+ additionalProperties: false
+
+ '^conf':
+ type: object
+ description:
+ Pinctrl node's client devices use subnodes for pin configurations,
+ which in turn use the standard properties below.
+ $ref: pincfg-node.yaml#
+
+ properties:
+ groups:
+ description:
+ List of pin groups as mentioned above.
+
+ pins:
+ description:
+ List of pin names to select in this subnode.
+ items:
+ pattern: '^MIO([0-9]|[1-4][0-9]|5[0-3])$'
+ maxItems: 54
+
+ bias-pull-up: true
+
+ bias-pull-down: true
+
+ bias-disable: true
+
+ bias-high-impedance: true
+
+ low-power-enable: true
+
+ low-power-disable: true
+
+ slew-rate:
+ enum: [0, 1]
+
+ io-standard:
+ description:
+ Selects the IO standard for MIO pins, this is driver specific.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ enum: [1, 2, 3, 4]
+
+ oneOf:
+ - required: [ groups ]
+ - required: [ pins ]
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ pinctrl0: pinctrl@700 {
+ compatible = "xlnx,zynq-pinctrl";
+ reg = <0x700 0x200>;
+ syscon = <&slcr>;
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_10_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_10_grp";
+ slew-rate = <0>;
+ io-standard = <1>;
+ };
+
+ conf-rx {
+ pins = "MIO49";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO48";
+ bias-disable;
+ };
+ };
+ };
+
+ uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+ };
+
+...
--
2.17.1
On Wed, 21 Jul 2021 17:22:30 +0530, Sai Krishna Potthuri wrote:
> Convert the Zynq pinctrl binding file to yaml.
>
> Signed-off-by: Sai Krishna Potthuri <[email protected]>
> ---
> .../bindings/pinctrl/xlnx,zynq-pinctrl.txt | 105 ---------
> .../bindings/pinctrl/xlnx,zynq-pinctrl.yaml | 216 ++++++++++++++++++
> 2 files changed, 216 insertions(+), 105 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.txt
> create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynq-pinctrl.yaml
>
Reviewed-by: Rob Herring <[email protected]>
On Wed, Jul 21, 2021 at 05:22:33PM +0530, Sai Krishna Potthuri wrote:
> Replace 'io-standard' property with 'power-source' property in all zynq dts
> files to be in sync with Zynq pinctrl driver.
>
> Signed-off-by: Sai Krishna Potthuri <[email protected]>
> ---
> arch/arm/boot/dts/zynq-ebaz4205.dts | 8 ++++----
> arch/arm/boot/dts/zynq-microzed.dts | 2 +-
> arch/arm/boot/dts/zynq-zc702.dts | 20 ++++++++++----------
> arch/arm/boot/dts/zynq-zc706.dts | 18 +++++++++---------
> 4 files changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
> index b0b836aedd76..be7eae611fb7 100644
> --- a/arch/arm/boot/dts/zynq-ebaz4205.dts
> +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
> @@ -57,7 +57,7 @@
>
> conf {
> groups = "gpio0_20_grp", "gpio0_32_grp";
> - io-standard = <3>;
> + power-source = <3>;
This will break using a new DT with a kernel without patch 3.
On 7/29/21 9:59 PM, Rob Herring wrote:
> On Wed, Jul 21, 2021 at 05:22:33PM +0530, Sai Krishna Potthuri wrote:
>> Replace 'io-standard' property with 'power-source' property in all zynq dts
>> files to be in sync with Zynq pinctrl driver.
>>
>> Signed-off-by: Sai Krishna Potthuri <[email protected]>
>> ---
>> arch/arm/boot/dts/zynq-ebaz4205.dts | 8 ++++----
>> arch/arm/boot/dts/zynq-microzed.dts | 2 +-
>> arch/arm/boot/dts/zynq-zc702.dts | 20 ++++++++++----------
>> arch/arm/boot/dts/zynq-zc706.dts | 18 +++++++++---------
>> 4 files changed, 24 insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
>> index b0b836aedd76..be7eae611fb7 100644
>> --- a/arch/arm/boot/dts/zynq-ebaz4205.dts
>> +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
>> @@ -57,7 +57,7 @@
>>
>> conf {
>> groups = "gpio0_20_grp", "gpio0_32_grp";
>> - io-standard = <3>;
>> + power-source = <3>;
>
> This will break using a new DT with a kernel without patch 3.
>
What do you suggest? Not to update any old DT?
Thanks,
Michal
On Wed, Jul 21, 2021 at 1:54 PM Sai Krishna Potthuri
<[email protected]> wrote:
> This patch series does the following
> - Covert Zynq pinctrl driver binding file to yaml.
> - Update the binding for Zynq pinctrl to replace the 'io-standard' with
> 'power-source' parameter as recommended by Linus during ZynqMP pinctrl
> driver review(https://lkml.org/lkml/2021/3/25/278).
> - Update the Zynq pinctrl the driver to remove custom pin
> parameter(io-standard) and instead use generic parameter(power-source).
> - Update Zynq dts files to replace 'io-standard' with 'power-source'.
>
> Reason for adding the generic parameter 'power-source' in Zynq pinctrl driver
> is to maintain common pin parameter across Xilinx Zynq and ZynqMP platforms
> for power supply configuration.
I applied patches 1-3 to the pinctrl tree, patch 4 should be applied
to the SoC tree.
Yours,
Linus Walleij
On Thu, Jul 29, 2021 at 9:59 PM Rob Herring <[email protected]> wrote:
> On Wed, Jul 21, 2021 at 05:22:33PM +0530, Sai Krishna Potthuri wrote:
> > Replace 'io-standard' property with 'power-source' property in all zynq dts
> > files to be in sync with Zynq pinctrl driver.
> >
> > Signed-off-by: Sai Krishna Potthuri <[email protected]>
> > ---
> > arch/arm/boot/dts/zynq-ebaz4205.dts | 8 ++++----
> > arch/arm/boot/dts/zynq-microzed.dts | 2 +-
> > arch/arm/boot/dts/zynq-zc702.dts | 20 ++++++++++----------
> > arch/arm/boot/dts/zynq-zc706.dts | 18 +++++++++---------
> > 4 files changed, 24 insertions(+), 24 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
> > index b0b836aedd76..be7eae611fb7 100644
> > --- a/arch/arm/boot/dts/zynq-ebaz4205.dts
> > +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
> > @@ -57,7 +57,7 @@
> >
> > conf {
> > groups = "gpio0_20_grp", "gpio0_32_grp";
> > - io-standard = <3>;
> > + power-source = <3>;
>
> This will break using a new DT with a kernel without patch 3.
The old (Linux) kernel never supported the "io-standard" property
anyway.
Unless someone is running som BSD or Windows with support for
this property it can be merged by the quality of zero real-world
impacts (no-one there to hear the tree fall in the forest).
Sai Krishna: correct?
Yours,
Linus Walleij
On 7/30/21 2:43 PM, Linus Walleij wrote:
> On Thu, Jul 29, 2021 at 9:59 PM Rob Herring <[email protected]> wrote:
>> On Wed, Jul 21, 2021 at 05:22:33PM +0530, Sai Krishna Potthuri wrote:
>>> Replace 'io-standard' property with 'power-source' property in all zynq dts
>>> files to be in sync with Zynq pinctrl driver.
>>>
>>> Signed-off-by: Sai Krishna Potthuri <[email protected]>
>>> ---
>>> arch/arm/boot/dts/zynq-ebaz4205.dts | 8 ++++----
>>> arch/arm/boot/dts/zynq-microzed.dts | 2 +-
>>> arch/arm/boot/dts/zynq-zc702.dts | 20 ++++++++++----------
>>> arch/arm/boot/dts/zynq-zc706.dts | 18 +++++++++---------
>>> 4 files changed, 24 insertions(+), 24 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
>>> index b0b836aedd76..be7eae611fb7 100644
>>> --- a/arch/arm/boot/dts/zynq-ebaz4205.dts
>>> +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
>>> @@ -57,7 +57,7 @@
>>>
>>> conf {
>>> groups = "gpio0_20_grp", "gpio0_32_grp";
>>> - io-standard = <3>;
>>> + power-source = <3>;
>>
>> This will break using a new DT with a kernel without patch 3.
>
> The old (Linux) kernel never supported the "io-standard" property
> anyway.
>
> Unless someone is running som BSD or Windows with support for
> this property it can be merged by the quality of zero real-world
> impacts (no-one there to hear the tree fall in the forest).
>
> Sai Krishna: correct?
Linux Zynq pinctrl driver and in tree dts files are using io-standard
properties at least from 2015.
M
On Fri, Jul 30, 2021 at 2:46 PM Michal Simek <[email protected]> wrote:
> Linux Zynq pinctrl driver and in tree dts files are using io-standard
> properties at least from 2015.
Ooops my wrong.
What about supporting both the new property and io-standard as
a fallback, simply?
Yours,
Linus Walleij
po 2. 8. 2021 v 15:20 odesÃlatel Linus Walleij
<[email protected]> napsal:
>
> On Fri, Jul 30, 2021 at 2:46 PM Michal Simek <[email protected]> wrote:
>
> > Linux Zynq pinctrl driver and in tree dts files are using io-standard
> > properties at least from 2015.
>
> Ooops my wrong.
>
> What about supporting both the new property and io-standard as
> a fallback, simply?
That's exactly what I have Sai to do and PIN_CONFIG_IOSTANDARD is still there.
https://lore.kernel.org/linux-arm-kernel/1626868353-96475-1-git-send-email-lakshmi.sai.krishna.potthuri@xilinx.com/T/#md7d304d9d8f746e51d909237b9073f2ae8930543
But IIRC I have also asked to show any warning message when io
standard property is used to convert to new property.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: http://www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
On Thu, Jul 29, 2021 at 10:59 PM Michal Simek <[email protected]> wrote:
>
>
>
> On 7/29/21 9:59 PM, Rob Herring wrote:
> > On Wed, Jul 21, 2021 at 05:22:33PM +0530, Sai Krishna Potthuri wrote:
> >> Replace 'io-standard' property with 'power-source' property in all zynq dts
> >> files to be in sync with Zynq pinctrl driver.
> >>
> >> Signed-off-by: Sai Krishna Potthuri <[email protected]>
> >> ---
> >> arch/arm/boot/dts/zynq-ebaz4205.dts | 8 ++++----
> >> arch/arm/boot/dts/zynq-microzed.dts | 2 +-
> >> arch/arm/boot/dts/zynq-zc702.dts | 20 ++++++++++----------
> >> arch/arm/boot/dts/zynq-zc706.dts | 18 +++++++++---------
> >> 4 files changed, 24 insertions(+), 24 deletions(-)
> >>
> >> diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
> >> index b0b836aedd76..be7eae611fb7 100644
> >> --- a/arch/arm/boot/dts/zynq-ebaz4205.dts
> >> +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
> >> @@ -57,7 +57,7 @@
> >>
> >> conf {
> >> groups = "gpio0_20_grp", "gpio0_32_grp";
> >> - io-standard = <3>;
> >> + power-source = <3>;
> >
> > This will break using a new DT with a kernel without patch 3.
> >
>
> What do you suggest? Not to update any old DT?
Your options are don't change the dts files, patch 3 needs to go to
stable kernels, or you document the breakage (if you don't care).
Rob
On 8/2/21 7:29 PM, Rob Herring wrote:
> On Thu, Jul 29, 2021 at 10:59 PM Michal Simek <[email protected]> wrote:
>>
>>
>>
>> On 7/29/21 9:59 PM, Rob Herring wrote:
>>> On Wed, Jul 21, 2021 at 05:22:33PM +0530, Sai Krishna Potthuri wrote:
>>>> Replace 'io-standard' property with 'power-source' property in all zynq dts
>>>> files to be in sync with Zynq pinctrl driver.
>>>>
>>>> Signed-off-by: Sai Krishna Potthuri <[email protected]>
>>>> ---
>>>> arch/arm/boot/dts/zynq-ebaz4205.dts | 8 ++++----
>>>> arch/arm/boot/dts/zynq-microzed.dts | 2 +-
>>>> arch/arm/boot/dts/zynq-zc702.dts | 20 ++++++++++----------
>>>> arch/arm/boot/dts/zynq-zc706.dts | 18 +++++++++---------
>>>> 4 files changed, 24 insertions(+), 24 deletions(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
>>>> index b0b836aedd76..be7eae611fb7 100644
>>>> --- a/arch/arm/boot/dts/zynq-ebaz4205.dts
>>>> +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
>>>> @@ -57,7 +57,7 @@
>>>>
>>>> conf {
>>>> groups = "gpio0_20_grp", "gpio0_32_grp";
>>>> - io-standard = <3>;
>>>> + power-source = <3>;
>>>
>>> This will break using a new DT with a kernel without patch 3.
>>>
>>
>> What do you suggest? Not to update any old DT?
>
> Your options are don't change the dts files, patch 3 needs to go to
> stable kernels, or you document the breakage (if you don't care).
There is no intention to go to stable kernel and I don't think this is
stable material. Linus has applied 3 patches and this one should go via
my tree. It means I will make sure that this DT change will be in the
tree when pinctrl changes are applied.
Thanks,
Michal
Hi Rob,
On 8/5/21 9:52 AM, Michal Simek wrote:
>
>
> On 8/2/21 7:29 PM, Rob Herring wrote:
>> On Thu, Jul 29, 2021 at 10:59 PM Michal Simek <[email protected]> wrote:
>>>
>>>
>>>
>>> On 7/29/21 9:59 PM, Rob Herring wrote:
>>>> On Wed, Jul 21, 2021 at 05:22:33PM +0530, Sai Krishna Potthuri wrote:
>>>>> Replace 'io-standard' property with 'power-source' property in all zynq dts
>>>>> files to be in sync with Zynq pinctrl driver.
>>>>>
>>>>> Signed-off-by: Sai Krishna Potthuri <[email protected]>
>>>>> ---
>>>>> arch/arm/boot/dts/zynq-ebaz4205.dts | 8 ++++----
>>>>> arch/arm/boot/dts/zynq-microzed.dts | 2 +-
>>>>> arch/arm/boot/dts/zynq-zc702.dts | 20 ++++++++++----------
>>>>> arch/arm/boot/dts/zynq-zc706.dts | 18 +++++++++---------
>>>>> 4 files changed, 24 insertions(+), 24 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/zynq-ebaz4205.dts b/arch/arm/boot/dts/zynq-ebaz4205.dts
>>>>> index b0b836aedd76..be7eae611fb7 100644
>>>>> --- a/arch/arm/boot/dts/zynq-ebaz4205.dts
>>>>> +++ b/arch/arm/boot/dts/zynq-ebaz4205.dts
>>>>> @@ -57,7 +57,7 @@
>>>>>
>>>>> conf {
>>>>> groups = "gpio0_20_grp", "gpio0_32_grp";
>>>>> - io-standard = <3>;
>>>>> + power-source = <3>;
>>>>
>>>> This will break using a new DT with a kernel without patch 3.
>>>>
>>>
>>> What do you suggest? Not to update any old DT?
>>
>> Your options are don't change the dts files, patch 3 needs to go to
>> stable kernels, or you document the breakage (if you don't care).
>
> There is no intention to go to stable kernel and I don't think this is
> stable material. Linus has applied 3 patches and this one should go via
> my tree. It means I will make sure that this DT change will be in the
> tree when pinctrl changes are applied.
Any issue with this patch? Or can I apply it to my tree?
Thanks,
Michal