Move UART related GPIO into hog group so that they still are pinmuxed
even if the uart driver is not probed.
Signed-off-by: Tim Harvey <[email protected]>
---
.../dts/freescale/imx8mm-venice-gw7901.dts | 44 +++++++------------
1 file changed, 15 insertions(+), 29 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
index 7e7231046215..ee78c189c556 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -710,7 +710,7 @@
&uart1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
+ pinctrl-0 = <&pinctrl_uart1>;
rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
@@ -728,7 +728,7 @@
&uart3 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
+ pinctrl-0 = <&pinctrl_uart3>;
cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
status = "okay";
@@ -736,7 +736,7 @@
&uart4 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
+ pinctrl-0 = <&pinctrl_uart4>;
cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
status = "okay";
@@ -807,6 +807,18 @@
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
+ MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
+ MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* UART1_RS422# */
+ MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* UART1_RS485# */
+ MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* UART1_RS232# */
+ MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* UART3_RS232# */
+ MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* UART3_RS422# */
+ MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* UART3_RS485# */
+
+ MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* UART4_RS232# */
+ MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* UART4_RS422# */
+ MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* UART4_RS485# */
+
>;
};
@@ -874,7 +886,6 @@
pinctrl_pcie0: pciegrp {
fsl,pins = <
- MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
>;
};
@@ -932,14 +943,6 @@
>;
};
- pinctrl_uart1_gpio: uart1gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
- MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
- MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
- >;
- };
-
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
@@ -956,14 +959,6 @@
>;
};
- pinctrl_uart3_gpio: uart3gpiogrp {
- fsl,pins = <
- MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
- MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
- MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
- >;
- };
-
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
@@ -973,15 +968,6 @@
>;
};
- pinctrl_uart4_gpio: uart4gpiogrp {
- fsl,pins = <
-
- MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
- MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
- MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
- >;
- };
-
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
--
2.17.1
On Tue, Apr 05, 2022 at 01:04:07PM -0700, Tim Harvey wrote:
> Move UART related GPIO into hog group so that they still are pinmuxed
> even if the uart driver is not probed.
What are these GPIOs used for? So they will be used anyway even when
UART support is disabled?
Shawn
>
> Signed-off-by: Tim Harvey <[email protected]>
> ---
> .../dts/freescale/imx8mm-venice-gw7901.dts | 44 +++++++------------
> 1 file changed, 15 insertions(+), 29 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> index 7e7231046215..ee78c189c556 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
> @@ -710,7 +710,7 @@
>
> &uart1 {
> pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
> + pinctrl-0 = <&pinctrl_uart1>;
> rts-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> cts-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
> dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
> @@ -728,7 +728,7 @@
>
> &uart3 {
> pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
> + pinctrl-0 = <&pinctrl_uart3>;
> cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
> rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
> status = "okay";
> @@ -736,7 +736,7 @@
>
> &uart4 {
> pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
> + pinctrl-0 = <&pinctrl_uart4>;
> cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
> rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
> status = "okay";
> @@ -807,6 +807,18 @@
> MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x40000041 /* SIM2DET# */
> MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x40000041 /* SIM1DET# */
> MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* SIM2SEL */
> + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
> + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* UART1_RS422# */
> + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* UART1_RS485# */
> + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* UART1_RS232# */
> + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* UART3_RS232# */
> + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* UART3_RS422# */
> + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* UART3_RS485# */
> +
> + MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* UART4_RS232# */
> + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* UART4_RS422# */
> + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* UART4_RS485# */
> +
> >;
> };
>
> @@ -874,7 +886,6 @@
>
> pinctrl_pcie0: pciegrp {
> fsl,pins = <
> - MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
> MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
> >;
> };
> @@ -932,14 +943,6 @@
> >;
> };
>
> - pinctrl_uart1_gpio: uart1gpiogrp {
> - fsl,pins = <
> - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x40000041 /* RS422# */
> - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000041 /* RS485# */
> - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x40000041 /* RS232# */
> - >;
> - };
> -
> pinctrl_uart2: uart2grp {
> fsl,pins = <
> MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> @@ -956,14 +959,6 @@
> >;
> };
>
> - pinctrl_uart3_gpio: uart3gpiogrp {
> - fsl,pins = <
> - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000110 /* RS232# */
> - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000110 /* RS422# */
> - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000110 /* RS485# */
> - >;
> - };
> -
> pinctrl_uart4: uart4grp {
> fsl,pins = <
> MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
> @@ -973,15 +968,6 @@
> >;
> };
>
> - pinctrl_uart4_gpio: uart4gpiogrp {
> - fsl,pins = <
> -
> - MX8MM_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x40000041 /* RS232# */
> - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40000041 /* RS422# */
> - MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* RS485# */
> - >;
> - };
> -
> pinctrl_usdhc1: usdhc1grp {
> fsl,pins = <
> MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
> --
> 2.17.1
>
On Sun, Apr 10, 2022 at 6:27 PM Shawn Guo <[email protected]> wrote:
>
> On Tue, Apr 05, 2022 at 01:04:07PM -0700, Tim Harvey wrote:
> > Move UART related GPIO into hog group so that they still are pinmuxed
> > even if the uart driver is not probed.
>
> What are these GPIOs used for? So they will be used anyway even when
> UART support is disabled?
>
> Shawn
Shawn,
Agreed - please drop this and 'imx8mm-venice-gw7902: move UART gpio
config into hog group' [1]
Best Regards,
Tim
[1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/