2022-02-03 15:39:11

by James Clark

Subject: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

This is a no-op change for style and consistency and has no effect on the
binary produced by gcc-11.

Signed-off-by: James Clark <[email protected]>
---
.../coresight/coresight-etm4x-core.c | 36 +++++--------------
drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++
drivers/hwtracing/coresight/coresight-priv.h | 5 +++
3 files changed, 30 insertions(+), 28 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index e2eebd865241..107e81948f76 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info)
etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);

/* INSTP0, bits[2:1] P0 tracing support field */
- if (BMVAL(etmidr0, 1, 2) == 0b11)
- drvdata->instrp0 = true;
- else
- drvdata->instrp0 = false;
-
+ drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11);
/* TRCBB, bit[5] Branch broadcast tracing support bit */
- if (BMVAL(etmidr0, 5, 5))
- drvdata->trcbb = true;
- else
- drvdata->trcbb = false;
-
+ drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
/* TRCCOND, bit[6] Conditional instruction tracing support bit */
- if (BMVAL(etmidr0, 6, 6))
- drvdata->trccond = true;
- else
- drvdata->trccond = false;
-
+ drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
/* TRCCCI, bit[7] Cycle counting instruction bit */
- if (BMVAL(etmidr0, 7, 7))
- drvdata->trccci = true;
- else
- drvdata->trccci = false;
-
+ drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
/* RETSTACK, bit[9] Return stack bit */
- if (BMVAL(etmidr0, 9, 9))
- drvdata->retstack = true;
- else
- drvdata->retstack = false;
-
+ drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
/* NUMEVENT, bits[11:10] Number of events field */
- drvdata->nr_event = BMVAL(etmidr0, 10, 11);
+ drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT);
/* QSUPP, bits[16:15] Q element support field */
- drvdata->q_support = BMVAL(etmidr0, 15, 16);
+ drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP);
/* TSSIZE, bits[28:24] Global timestamp size field */
- drvdata->ts_size = BMVAL(etmidr0, 24, 28);
+ drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE);

/* maximum size of resources */
etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 3c4d69b096ca..2bd8ad953b8e 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -130,6 +130,23 @@

#define TRCRSR_TA BIT(12)

+/*
+ * Bit positions of registers that are defined above, in the sysreg.h style
+ * of _MASK, _SHIFT and BIT().
+ */
+#define TRCIDR0_INSTP0_SHIFT 1
+#define TRCIDR0_INSTP0_MASK GENMASK(1, 0)
+#define TRCIDR0_TRCBB BIT(5)
+#define TRCIDR0_TRCCOND BIT(6)
+#define TRCIDR0_TRCCCI BIT(7)
+#define TRCIDR0_RETSTACK BIT(9)
+#define TRCIDR0_NUMEVENT_SHIFT 10
+#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0)
+#define TRCIDR0_QSUPP_SHIFT 15
+#define TRCIDR0_QSUPP_MASK GENMASK(1, 0)
+#define TRCIDR0_TSSIZE_SHIFT 24
+#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)
+
/*
* System instructions to access ETM registers.
* See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index ff1dd2092ac5..1452c6038421 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -36,6 +36,11 @@

#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
+/*
+ * Extract a field from a register where field is #defined in the form
+ * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
+ */
+#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT)

#define ETM_MODE_EXCL_KERN BIT(30)
#define ETM_MODE_EXCL_USER BIT(31)
--
2.28.0

2022-02-08 02:25:32

by Anshuman Khandual

Subject: Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

Hi James,

These are all ETM4X specific changes. Something like this might be cleaner
and also more compact. Also would suggest to follow the same for subsequent
patches as well.

coresight: etm4x: Cleanup TRCIDR0 register accesses

Consistency with sysreg.h could be mentioned in the commit message itself.

On 2/3/22 5:35 PM, James Clark wrote:
> This is a no-op change for style and consistency and has no effect on the
> binary produced by gcc-11.

This patch adds register definitions, helper macros as well. Please expand
the commit message to add more details. This is too short, for the change
it creates. BTW why is it necessary to mention GCC version number here.

>
> Signed-off-by: James Clark <[email protected]>
> ---
> .../coresight/coresight-etm4x-core.c | 36 +++++--------------
> drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++
> drivers/hwtracing/coresight/coresight-priv.h | 5 +++
> 3 files changed, 30 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index e2eebd865241..107e81948f76 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info)
> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
>
> /* INSTP0, bits[2:1] P0 tracing support field */
> - if (BMVAL(etmidr0, 1, 2) == 0b11)
> - drvdata->instrp0 = true;
> - else
> - drvdata->instrp0 = false;
> -
> + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11);
> /* TRCBB, bit[5] Branch broadcast tracing support bit */
> - if (BMVAL(etmidr0, 5, 5))
> - drvdata->trcbb = true;
> - else
> - drvdata->trcbb = false;
> -
> + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
> /* TRCCOND, bit[6] Conditional instruction tracing support bit */
> - if (BMVAL(etmidr0, 6, 6))
> - drvdata->trccond = true;
> - else
> - drvdata->trccond = false;
> -
> + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
> /* TRCCCI, bit[7] Cycle counting instruction bit */
> - if (BMVAL(etmidr0, 7, 7))
> - drvdata->trccci = true;
> - else
> - drvdata->trccci = false;
> -
> + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
> /* RETSTACK, bit[9] Return stack bit */
> - if (BMVAL(etmidr0, 9, 9))
> - drvdata->retstack = true;
> - else
> - drvdata->retstack = false;
> -
> + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
> /* NUMEVENT, bits[11:10] Number of events field */
> - drvdata->nr_event = BMVAL(etmidr0, 10, 11);
> + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT);
> /* QSUPP, bits[16:15] Q element support field */
> - drvdata->q_support = BMVAL(etmidr0, 15, 16);
> + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP);
> /* TSSIZE, bits[28:24] Global timestamp size field */
> - drvdata->ts_size = BMVAL(etmidr0, 24, 28);
> + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE);
>
> /* maximum size of resources */
> etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 3c4d69b096ca..2bd8ad953b8e 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -130,6 +130,23 @@
>
> #define TRCRSR_TA BIT(12)
>
> +/*
> + * Bit positions of registers that are defined above, in the sysreg.h style
> + * of _MASK, _SHIFT and BIT().
> + */

^^^ not really necessary. Instead the format requirement for below mentioned
CORESIGHT_REG_VAL() macro might be relevant and should be mentioned.

> +#define TRCIDR0_INSTP0_SHIFT 1
> +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0)
> +#define TRCIDR0_TRCBB BIT(5)
> +#define TRCIDR0_TRCCOND BIT(6)
> +#define TRCIDR0_TRCCCI BIT(7)
> +#define TRCIDR0_RETSTACK BIT(9)
> +#define TRCIDR0_NUMEVENT_SHIFT 10
> +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0)
> +#define TRCIDR0_QSUPP_SHIFT 15
> +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0)
> +#define TRCIDR0_TSSIZE_SHIFT 24
> +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)
> +
> /*
> * System instructions to access ETM registers.
> * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> index ff1dd2092ac5..1452c6038421 100644
> --- a/drivers/hwtracing/coresight/coresight-priv.h
> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> @@ -36,6 +36,11 @@
>
> #define TIMEOUT_US 100
> #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
> +/*
> + * Extract a field from a register where field is #defined in the form
> + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
> + */

Looking at the usage, <register_name> is already embedded in <filed_name>. So
it requires <field_name>_SHIFT and <field_name>_MASK instead. Unless register
name should be passed as separate argument (which actually might be better).

REG_VAL(etmidr0, TRCIDR0_TSSIZE) ----> REG_VAL(etmidr0, TRCIDR0, TSSIZE)

with some restructuring in the comment ..

/*
* Extract a field from a coresight register
*
* Required fields are defined as macros like the following
*
* <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
*/

> +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT)

This is too generic to be in a coresight header or it should just be
named CORESIGHT_REG_VAL() instead, making it more specific for here.

The build should fail in case any required macro definition is absent.
I guess no more fortification is required in case macros are missing.

However CORESIGHT_REG_VAL() is better placed in <coresight-etm4x.h>
just before all the dependent SHIFT/MASK register field definition
starts.

>
> #define ETM_MODE_EXCL_KERN BIT(30)
> #define ETM_MODE_EXCL_USER BIT(31)
>

- Anshuman

2022-02-08 15:51:10

by Mike Leach

Subject: Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

Hi James,

On Thu, 3 Feb 2022 at 12:06, James Clark <[email protected]> wrote:
>
> This is a no-op change for style and consistency and has no effect on the
> binary produced by gcc-11.
>
> Signed-off-by: James Clark <[email protected]>
> ---
> .../coresight/coresight-etm4x-core.c | 36 +++++--------------
> drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++
> drivers/hwtracing/coresight/coresight-priv.h | 5 +++
> 3 files changed, 30 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index e2eebd865241..107e81948f76 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info)
> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
>
> /* INSTP0, bits[2:1] P0 tracing support field */
> - if (BMVAL(etmidr0, 1, 2) == 0b11)
> - drvdata->instrp0 = true;
> - else
> - drvdata->instrp0 = false;
> -
> + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11);
> /* TRCBB, bit[5] Branch broadcast tracing support bit */
> - if (BMVAL(etmidr0, 5, 5))
> - drvdata->trcbb = true;
> - else
> - drvdata->trcbb = false;
> -
> + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
> /* TRCCOND, bit[6] Conditional instruction tracing support bit */
> - if (BMVAL(etmidr0, 6, 6))
> - drvdata->trccond = true;
> - else
> - drvdata->trccond = false;
> -
> + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
> /* TRCCCI, bit[7] Cycle counting instruction bit */
> - if (BMVAL(etmidr0, 7, 7))
> - drvdata->trccci = true;
> - else
> - drvdata->trccci = false;
> -
> + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
> /* RETSTACK, bit[9] Return stack bit */
> - if (BMVAL(etmidr0, 9, 9))
> - drvdata->retstack = true;
> - else
> - drvdata->retstack = false;
> -
> + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
> /* NUMEVENT, bits[11:10] Number of events field */
> - drvdata->nr_event = BMVAL(etmidr0, 10, 11);
> + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT);
> /* QSUPP, bits[16:15] Q element support field */
> - drvdata->q_support = BMVAL(etmidr0, 15, 16);
> + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP);
> /* TSSIZE, bits[28:24] Global timestamp size field */
> - drvdata->ts_size = BMVAL(etmidr0, 24, 28);
> + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE);
>
> /* maximum size of resources */
> etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 3c4d69b096ca..2bd8ad953b8e 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -130,6 +130,23 @@
>
> #define TRCRSR_TA BIT(12)
>
> +/*
> + * Bit positions of registers that are defined above, in the sysreg.h style
> + * of _MASK, _SHIFT and BIT().
> + */
> +#define TRCIDR0_INSTP0_SHIFT 1
> +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0)
> +#define TRCIDR0_TRCBB BIT(5)
> +#define TRCIDR0_TRCCOND BIT(6)
> +#define TRCIDR0_TRCCCI BIT(7)
> +#define TRCIDR0_RETSTACK BIT(9)
> +#define TRCIDR0_NUMEVENT_SHIFT 10
> +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0)
> +#define TRCIDR0_QSUPP_SHIFT 15
> +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0)
> +#define TRCIDR0_TSSIZE_SHIFT 24
> +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)
> +
> /*
> * System instructions to access ETM registers.
> * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> index ff1dd2092ac5..1452c6038421 100644
> --- a/drivers/hwtracing/coresight/coresight-priv.h
> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> @@ -36,6 +36,11 @@
>
> #define TIMEOUT_US 100
> #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
> +/*
> + * Extract a field from a register where field is #defined in the form
> + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
> + */
> +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT)
>

The only v minor comment I would have is that this macro could be
REG_FIELD() or REG_FIELD_VAL(), which in my view would make more
natural and obvious reading in the source files where it appears.

e.g.

drvdata->nr_event = REG_FIELD(etmidr0, TRCIDR0_NUMEVENT);

However it ends up, it certainly needs to stay in a common header for
possible use in other drivers (not just ETMv3).

Regards

Mike

> #define ETM_MODE_EXCL_KERN BIT(30)
> #define ETM_MODE_EXCL_USER BIT(31)
> --
> 2.28.0
>


--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

2022-02-09 09:44:15

by Mathieu Poirier

Subject: Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

On Mon, Feb 07, 2022 at 11:14:50AM +0530, Anshuman Khandual wrote:
> Hi James,
>
> These are all ETM4X specific changes. Something like this might be cleaner
> and also more compact. Also would suggest to follow the same for subsequent
> patches as well.
>
> coresight: etm4x: Cleanup TRCIDR0 register accesses
>
> Consistency with sysreg.h could be mentioned in the commit message itself.
>

I agree with the above two comments.

> On 2/3/22 5:35 PM, James Clark wrote:
> > This is a no-op change for style and consistency and has no effect on the
> > binary produced by gcc-11.
>
> This patch adds register definitions, helper macros as well. Please expand
> the commit message to add more details. This is too short, for the change
> it creates. BTW why is it necessary to mention GCC version number here.
>

Here too - I'm not sure adding gcc's version number helps in any way.

> >
> > Signed-off-by: James Clark <[email protected]>
> > ---
> > .../coresight/coresight-etm4x-core.c | 36 +++++--------------
> > drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++
> > drivers/hwtracing/coresight/coresight-priv.h | 5 +++
> > 3 files changed, 30 insertions(+), 28 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > index e2eebd865241..107e81948f76 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> > @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info)
> > etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
> >
> > /* INSTP0, bits[2:1] P0 tracing support field */
> > - if (BMVAL(etmidr0, 1, 2) == 0b11)
> > - drvdata->instrp0 = true;
> > - else
> > - drvdata->instrp0 = false;
> > -
> > + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11);
> > /* TRCBB, bit[5] Branch broadcast tracing support bit */
> > - if (BMVAL(etmidr0, 5, 5))
> > - drvdata->trcbb = true;
> > - else
> > - drvdata->trcbb = false;
> > -
> > + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
> > /* TRCCOND, bit[6] Conditional instruction tracing support bit */
> > - if (BMVAL(etmidr0, 6, 6))
> > - drvdata->trccond = true;
> > - else
> > - drvdata->trccond = false;
> > -
> > + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
> > /* TRCCCI, bit[7] Cycle counting instruction bit */
> > - if (BMVAL(etmidr0, 7, 7))
> > - drvdata->trccci = true;
> > - else
> > - drvdata->trccci = false;
> > -
> > + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
> > /* RETSTACK, bit[9] Return stack bit */
> > - if (BMVAL(etmidr0, 9, 9))
> > - drvdata->retstack = true;
> > - else
> > - drvdata->retstack = false;
> > -
> > + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
> > /* NUMEVENT, bits[11:10] Number of events field */
> > - drvdata->nr_event = BMVAL(etmidr0, 10, 11);
> > + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT);
> > /* QSUPP, bits[16:15] Q element support field */
> > - drvdata->q_support = BMVAL(etmidr0, 15, 16);
> > + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP);
> > /* TSSIZE, bits[28:24] Global timestamp size field */
> > - drvdata->ts_size = BMVAL(etmidr0, 24, 28);
> > + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE);
> >
> > /* maximum size of resources */
> > etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
> > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> > index 3c4d69b096ca..2bd8ad953b8e 100644
> > --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> > @@ -130,6 +130,23 @@
> >
> > #define TRCRSR_TA BIT(12)
> >
> > +/*
> > + * Bit positions of registers that are defined above, in the sysreg.h style
> > + * of _MASK, _SHIFT and BIT().
> > + */
>
> ^^^ not really necessary. Instead the format requirement for below mentioned
> CORESIGHT_REG_VAL() macro might be relevant and should be mentioned.

I'm not sure if you're asking to move the comment further below or remove it
altogether. In any case more comments is always better than less.

>
> > +#define TRCIDR0_INSTP0_SHIFT 1
> > +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0)
> > +#define TRCIDR0_TRCBB BIT(5)
> > +#define TRCIDR0_TRCCOND BIT(6)
> > +#define TRCIDR0_TRCCCI BIT(7)
> > +#define TRCIDR0_RETSTACK BIT(9)
> > +#define TRCIDR0_NUMEVENT_SHIFT 10
> > +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0)
> > +#define TRCIDR0_QSUPP_SHIFT 15
> > +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0)
> > +#define TRCIDR0_TSSIZE_SHIFT 24
> > +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)
> > +
> > /*
> > * System instructions to access ETM registers.
> > * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> > index ff1dd2092ac5..1452c6038421 100644
> > --- a/drivers/hwtracing/coresight/coresight-priv.h
> > +++ b/drivers/hwtracing/coresight/coresight-priv.h
> > @@ -36,6 +36,11 @@
> >
> > #define TIMEOUT_US 100
> > #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
> > +/*
> > + * Extract a field from a register where field is #defined in the form
> > + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
> > + */
>
> Looking at the usage, <register_name> is already embedded in <filed_name>. So
> it requires <field_name>_SHIFT and <field_name>_MASK instead. Unless register
> name should be passed as separate argument (which actually might be better).
>
> REG_VAL(etmidr0, TRCIDR0_TSSIZE) ----> REG_VAL(etmidr0, TRCIDR0, TSSIZE)

I don't have strong preference, I'm good either way.

>
> with some restructuring in the comment ..
>
> /*
> * Extract a field from a coresight register
> *
> * Required fields are defined as macros like the following
> *
> * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
> */
>
> > +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT)
>
> This is too generic to be in a coresight header or it should just be
> named CORESIGHT_REG_VAL() instead, making it more specific for here.
>
> The build should fail in case any required macro definition is absent.
> I guess no more fortification is required in case macros are missing.
>
> However CORESIGHT_REG_VAL() is better placed in <coresight-etm4x.h>
> just before all the dependent SHIFT/MASK register field definition
> starts.
>

Not sure about this... Someone might want to do the same for etmv3 and in that
case we'll end up moving the macro again.

Thanks,
Mathieu

> >
> > #define ETM_MODE_EXCL_KERN BIT(30)
> > #define ETM_MODE_EXCL_USER BIT(31)
> >
>
> - Anshuman

2022-02-09 10:02:17

by Suzuki K Poulose

Subject: Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

On 07/02/2022 05:44, Anshuman Khandual wrote:
> Hi James,
>
> These are all ETM4X specific changes. Something like this might be cleaner
> and also more compact. Also would suggest to follow the same for subsequent
> patches as well.
>
> coresight: etm4x: Cleanup TRCIDR0 register accesses
>
> Consistency with sysreg.h could be mentioned in the commit message itself.
>
> On 2/3/22 5:35 PM, James Clark wrote:
>> This is a no-op change for style and consistency and has no effect on the
>> binary produced by gcc-11.
>
> This patch adds register definitions, helper macros as well. Please expand
> the commit message to add more details. This is too short, for the change
> it creates. BTW why is it necessary to mention GCC version number here.
>
>>
>> Signed-off-by: James Clark <[email protected]>
>> ---
>> .../coresight/coresight-etm4x-core.c | 36 +++++--------------
>> drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++
>> drivers/hwtracing/coresight/coresight-priv.h | 5 +++
>> 3 files changed, 30 insertions(+), 28 deletions(-)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> index e2eebd865241..107e81948f76 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>> @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info)
>> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
>>
>> /* INSTP0, bits[2:1] P0 tracing support field */
>> - if (BMVAL(etmidr0, 1, 2) == 0b11)
>> - drvdata->instrp0 = true;
>> - else
>> - drvdata->instrp0 = false;
>> -
>> + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11);
>> /* TRCBB, bit[5] Branch broadcast tracing support bit */
>> - if (BMVAL(etmidr0, 5, 5))
>> - drvdata->trcbb = true;
>> - else
>> - drvdata->trcbb = false;
>> -
>> + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
>> /* TRCCOND, bit[6] Conditional instruction tracing support bit */
>> - if (BMVAL(etmidr0, 6, 6))
>> - drvdata->trccond = true;
>> - else
>> - drvdata->trccond = false;
>> -
>> + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
>> /* TRCCCI, bit[7] Cycle counting instruction bit */
>> - if (BMVAL(etmidr0, 7, 7))
>> - drvdata->trccci = true;
>> - else
>> - drvdata->trccci = false;
>> -
>> + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
>> /* RETSTACK, bit[9] Return stack bit */
>> - if (BMVAL(etmidr0, 9, 9))
>> - drvdata->retstack = true;
>> - else
>> - drvdata->retstack = false;
>> -
>> + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
>> /* NUMEVENT, bits[11:10] Number of events field */
>> - drvdata->nr_event = BMVAL(etmidr0, 10, 11);
>> + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT);
>> /* QSUPP, bits[16:15] Q element support field */
>> - drvdata->q_support = BMVAL(etmidr0, 15, 16);
>> + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP);
>> /* TSSIZE, bits[28:24] Global timestamp size field */
>> - drvdata->ts_size = BMVAL(etmidr0, 24, 28);
>> + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE);
>>
>> /* maximum size of resources */
>> etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
>> index 3c4d69b096ca..2bd8ad953b8e 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
>> @@ -130,6 +130,23 @@
>>
>> #define TRCRSR_TA BIT(12)
>>
>> +/*
>> + * Bit positions of registers that are defined above, in the sysreg.h style
>> + * of _MASK, _SHIFT and BIT().
>> + */
>
> ^^^ not really necessary. Instead the format requirement for below mentioned
> CORESIGHT_REG_VAL() macro might be relevant and should be mentioned.
>
>> +#define TRCIDR0_INSTP0_SHIFT 1
>> +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0)
>> +#define TRCIDR0_TRCBB BIT(5)
>> +#define TRCIDR0_TRCCOND BIT(6)
>> +#define TRCIDR0_TRCCCI BIT(7)
>> +#define TRCIDR0_RETSTACK BIT(9)
>> +#define TRCIDR0_NUMEVENT_SHIFT 10
>> +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0)
>> +#define TRCIDR0_QSUPP_SHIFT 15
>> +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0)
>> +#define TRCIDR0_TSSIZE_SHIFT 24
>> +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)
>> +
>> /*
>> * System instructions to access ETM registers.
>> * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
>> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
>> index ff1dd2092ac5..1452c6038421 100644
>> --- a/drivers/hwtracing/coresight/coresight-priv.h
>> +++ b/drivers/hwtracing/coresight/coresight-priv.h
>> @@ -36,6 +36,11 @@
>>
>> #define TIMEOUT_US 100
>> #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
>> +/*
>> + * Extract a field from a register where field is #defined in the form
>> + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
>> + */
>
> Looking at the usage, <register_name> is already embedded in <filed_name>. So
> it requires <field_name>_SHIFT and <field_name>_MASK instead. Unless register
> name should be passed as separate argument (which actually might be better).
>
> REG_VAL(etmidr0, TRCIDR0_TSSIZE) ----> REG_VAL(etmidr0, TRCIDR0, TSSIZE)

I don't see much difference here. So I am fine either way.

>
> with some restructuring in the comment ..
>
> /*
> * Extract a field from a coresight register
> *
> * Required fields are defined as macros like the following
> *
> * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
> */
>
>> +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT)
>
> This is too generic to be in a coresight header or it should just be
> named CORESIGHT_REG_VAL() instead, making it more specific for here.
>
> The build should fail in case any required macro definition is absent.
> I guess no more fortification is required in case macros are missing.
>
> However CORESIGHT_REG_VAL() is better placed in <coresight-etm4x.h>
> just before all the dependent SHIFT/MASK register field definition
> starts.

Not necessarily. CORESIGHT_REG_VAL() is a generic function and doesn't
have anything specific to do with etm4x. We could reuse that for
cleaning up other drivers in CoreSight.

Cheers
Suzuki

2022-02-09 13:08:05

by Mike Leach

Subject: Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

Hi James,

When reviewing another patch set I spotted that there is a FIELD_GET
macro already defined for the kernel in include/linux/bitfield.h

Advantage of this is that you only need to define a shifted mask for
each field and the macro handles the extraction and shifting
automatically.
It also ensures does a bunch of compile time sanity checks to ensure
that the masks are in range for the type.

i.e. - define the mask _with_ the shift
#define TRCIDR0_INSTP0_MASK GENMASK(2, 1)

then
drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);

which means all the shift #defines can be dropped

Should we use this and drop the REG_VAL or whatever?

Regards

Mike

On Tue, 8 Feb 2022 at 15:04, Suzuki K Poulose <[email protected]> wrote:
>
> On 07/02/2022 05:44, Anshuman Khandual wrote:
> > Hi James,
> >
> > These are all ETM4X specific changes. Something like this might be cleaner
> > and also more compact. Also would suggest to follow the same for subsequent
> > patches as well.
> >
> > coresight: etm4x: Cleanup TRCIDR0 register accesses
> >
> > Consistency with sysreg.h could be mentioned in the commit message itself.
> >
> > On 2/3/22 5:35 PM, James Clark wrote:
> >> This is a no-op change for style and consistency and has no effect on the
> >> binary produced by gcc-11.
> >
> > This patch adds register definitions, helper macros as well. Please expand
> > the commit message to add more details. This is too short, for the change
> > it creates. BTW why is it necessary to mention GCC version number here.
> >
> >>
> >> Signed-off-by: James Clark <[email protected]>
> >> ---
> >> .../coresight/coresight-etm4x-core.c | 36 +++++--------------
> >> drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++
> >> drivers/hwtracing/coresight/coresight-priv.h | 5 +++
> >> 3 files changed, 30 insertions(+), 28 deletions(-)
> >>
> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> >> index e2eebd865241..107e81948f76 100644
> >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> >> @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info)
> >> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
> >>
> >> /* INSTP0, bits[2:1] P0 tracing support field */
> >> - if (BMVAL(etmidr0, 1, 2) == 0b11)
> >> - drvdata->instrp0 = true;
> >> - else
> >> - drvdata->instrp0 = false;
> >> -
> >> + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11);
> >> /* TRCBB, bit[5] Branch broadcast tracing support bit */
> >> - if (BMVAL(etmidr0, 5, 5))
> >> - drvdata->trcbb = true;
> >> - else
> >> - drvdata->trcbb = false;
> >> -
> >> + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
> >> /* TRCCOND, bit[6] Conditional instruction tracing support bit */
> >> - if (BMVAL(etmidr0, 6, 6))
> >> - drvdata->trccond = true;
> >> - else
> >> - drvdata->trccond = false;
> >> -
> >> + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
> >> /* TRCCCI, bit[7] Cycle counting instruction bit */
> >> - if (BMVAL(etmidr0, 7, 7))
> >> - drvdata->trccci = true;
> >> - else
> >> - drvdata->trccci = false;
> >> -
> >> + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
> >> /* RETSTACK, bit[9] Return stack bit */
> >> - if (BMVAL(etmidr0, 9, 9))
> >> - drvdata->retstack = true;
> >> - else
> >> - drvdata->retstack = false;
> >> -
> >> + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
> >> /* NUMEVENT, bits[11:10] Number of events field */
> >> - drvdata->nr_event = BMVAL(etmidr0, 10, 11);
> >> + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT);
> >> /* QSUPP, bits[16:15] Q element support field */
> >> - drvdata->q_support = BMVAL(etmidr0, 15, 16);
> >> + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP);
> >> /* TSSIZE, bits[28:24] Global timestamp size field */
> >> - drvdata->ts_size = BMVAL(etmidr0, 24, 28);
> >> + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE);
> >>
> >> /* maximum size of resources */
> >> etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> >> index 3c4d69b096ca..2bd8ad953b8e 100644
> >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> >> @@ -130,6 +130,23 @@
> >>
> >> #define TRCRSR_TA BIT(12)
> >>
> >> +/*
> >> + * Bit positions of registers that are defined above, in the sysreg.h style
> >> + * of _MASK, _SHIFT and BIT().
> >> + */
> >
> > ^^^ not really necessary. Instead the format requirement for below mentioned
> > CORESIGHT_REG_VAL() macro might be relevant and should be mentioned.
> >
> >> +#define TRCIDR0_INSTP0_SHIFT 1
> >> +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0)
> >> +#define TRCIDR0_TRCBB BIT(5)
> >> +#define TRCIDR0_TRCCOND BIT(6)
> >> +#define TRCIDR0_TRCCCI BIT(7)
> >> +#define TRCIDR0_RETSTACK BIT(9)
> >> +#define TRCIDR0_NUMEVENT_SHIFT 10
> >> +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0)
> >> +#define TRCIDR0_QSUPP_SHIFT 15
> >> +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0)
> >> +#define TRCIDR0_TSSIZE_SHIFT 24
> >> +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)
> >> +
> >> /*
> >> * System instructions to access ETM registers.
> >> * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
> >> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> >> index ff1dd2092ac5..1452c6038421 100644
> >> --- a/drivers/hwtracing/coresight/coresight-priv.h
> >> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> >> @@ -36,6 +36,11 @@
> >>
> >> #define TIMEOUT_US 100
> >> #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
> >> +/*
> >> + * Extract a field from a register where field is #defined in the form
> >> + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
> >> + */
> >
> > Looking at the usage, <register_name> is already embedded in <filed_name>. So
> > it requires <field_name>_SHIFT and <field_name>_MASK instead. Unless register
> > name should be passed as separate argument (which actually might be better).
> >
> > REG_VAL(etmidr0, TRCIDR0_TSSIZE) ----> REG_VAL(etmidr0, TRCIDR0, TSSIZE)
>
> I don't see much difference here. So I am fine either way.
>
> >
> > with some restructuring in the comment ..
> >
> > /*
> > * Extract a field from a coresight register
> > *
> > * Required fields are defined as macros like the following
> > *
> > * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
> > */
> >
> >> +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT)
> >
> > This is too generic to be in a coresight header or it should just be
> > named CORESIGHT_REG_VAL() instead, making it more specific for here.
> >
> > The build should fail in case any required macro definition is absent.
> > I guess no more fortification is required in case macros are missing.
> >
> > However CORESIGHT_REG_VAL() is better placed in <coresight-etm4x.h>
> > just before all the dependent SHIFT/MASK register field definition
> > starts.
>
> Not necessarily. CORESIGHT_REG_VAL() is a generic function and doesn't
> have anything specific to do with etm4x. We could reuse that for
> cleaning up other drivers in CoreSight.
>
> Cheers
> Suzuki



--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK

2022-02-26 01:46:58

by James Clark

Subject: Re: [PATCH v2 01/15] coresight: Make ETM4x TRCIDR0 register accesses consistent with sysreg.h

On 09/02/2022 09:32, Mike Leach wrote:
> Hi James,
>
> When reviewing another patch set I spotted that there is a FIELD_GET
> macro already defined for the kernel in include/linux/bitfield.h
>
> Advantage of this is that you only need to define a shifted mask for
> each field and the macro handles the extraction and shifting
> automatically.
> It also ensures does a bunch of compile time sanity checks to ensure
> that the masks are in range for the type.
>
> i.e. - define the mask _with_ the shift
> #define TRCIDR0_INSTP0_MASK GENMASK(2, 1)
>
> then
> drvdata->instrp0 = !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) == 0b11);
>
> which means all the shift #defines can be dropped
>
> Should we use this and drop the REG_VAL or whatever?

To me it seems like this is a much better way of doing it because it removes
one source of error with the shift being incorrect. This way it also mirrors
the reference manual more closely.

One possible issue is that it's not really consistent with sysreg.h because
masks there are from the 0 bit and the shift is used. I suppose doing it this
way is still closer to sysreg.h so it's a net benefit.

I checked converting one register to this format and the compiler still emits
the same thing so if we want to we can go ahead and do all of them.
I'm leaning towards this way because this is what I would have done if it was
from scratch. I just did it with the mask and the shift separately for
consistency.


>
> Regards
>
> Mike
>
> On Tue, 8 Feb 2022 at 15:04, Suzuki K Poulose <[email protected]> wrote:
>>
>> On 07/02/2022 05:44, Anshuman Khandual wrote:
>>> Hi James,
>>>
>>> These are all ETM4X specific changes. Something like this might be cleaner
>>> and also more compact. Also would suggest to follow the same for subsequent
>>> patches as well.
>>>
>>> coresight: etm4x: Cleanup TRCIDR0 register accesses
>>>
>>> Consistency with sysreg.h could be mentioned in the commit message itself.
>>>
>>> On 2/3/22 5:35 PM, James Clark wrote:
>>>> This is a no-op change for style and consistency and has no effect on the
>>>> binary produced by gcc-11.
>>>
>>> This patch adds register definitions, helper macros as well. Please expand
>>> the commit message to add more details. This is too short, for the change
>>> it creates. BTW why is it necessary to mention GCC version number here.
>>>
>>>>
>>>> Signed-off-by: James Clark <[email protected]>
>>>> ---
>>>> .../coresight/coresight-etm4x-core.c | 36 +++++--------------
>>>> drivers/hwtracing/coresight/coresight-etm4x.h | 17 +++++++++
>>>> drivers/hwtracing/coresight/coresight-priv.h | 5 +++
>>>> 3 files changed, 30 insertions(+), 28 deletions(-)
>>>>
>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>>> index e2eebd865241..107e81948f76 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
>>>> @@ -1091,41 +1091,21 @@ static void etm4_init_arch_data(void *info)
>>>> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
>>>>
>>>> /* INSTP0, bits[2:1] P0 tracing support field */
>>>> - if (BMVAL(etmidr0, 1, 2) == 0b11)
>>>> - drvdata->instrp0 = true;
>>>> - else
>>>> - drvdata->instrp0 = false;
>>>> -
>>>> + drvdata->instrp0 = !!(REG_VAL(etmidr0, TRCIDR0_INSTP0) == 0b11);
>>>> /* TRCBB, bit[5] Branch broadcast tracing support bit */
>>>> - if (BMVAL(etmidr0, 5, 5))
>>>> - drvdata->trcbb = true;
>>>> - else
>>>> - drvdata->trcbb = false;
>>>> -
>>>> + drvdata->trcbb = !!(etmidr0 & TRCIDR0_TRCBB);
>>>> /* TRCCOND, bit[6] Conditional instruction tracing support bit */
>>>> - if (BMVAL(etmidr0, 6, 6))
>>>> - drvdata->trccond = true;
>>>> - else
>>>> - drvdata->trccond = false;
>>>> -
>>>> + drvdata->trccond = !!(etmidr0 & TRCIDR0_TRCCOND);
>>>> /* TRCCCI, bit[7] Cycle counting instruction bit */
>>>> - if (BMVAL(etmidr0, 7, 7))
>>>> - drvdata->trccci = true;
>>>> - else
>>>> - drvdata->trccci = false;
>>>> -
>>>> + drvdata->trccci = !!(etmidr0 & TRCIDR0_TRCCCI);
>>>> /* RETSTACK, bit[9] Return stack bit */
>>>> - if (BMVAL(etmidr0, 9, 9))
>>>> - drvdata->retstack = true;
>>>> - else
>>>> - drvdata->retstack = false;
>>>> -
>>>> + drvdata->retstack = !!(etmidr0 & TRCIDR0_RETSTACK);
>>>> /* NUMEVENT, bits[11:10] Number of events field */
>>>> - drvdata->nr_event = BMVAL(etmidr0, 10, 11);
>>>> + drvdata->nr_event = REG_VAL(etmidr0, TRCIDR0_NUMEVENT);
>>>> /* QSUPP, bits[16:15] Q element support field */
>>>> - drvdata->q_support = BMVAL(etmidr0, 15, 16);
>>>> + drvdata->q_support = REG_VAL(etmidr0, TRCIDR0_QSUPP);
>>>> /* TSSIZE, bits[28:24] Global timestamp size field */
>>>> - drvdata->ts_size = BMVAL(etmidr0, 24, 28);
>>>> + drvdata->ts_size = REG_VAL(etmidr0, TRCIDR0_TSSIZE);
>>>>
>>>> /* maximum size of resources */
>>>> etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
>>>> index 3c4d69b096ca..2bd8ad953b8e 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
>>>> @@ -130,6 +130,23 @@
>>>>
>>>> #define TRCRSR_TA BIT(12)
>>>>
>>>> +/*
>>>> + * Bit positions of registers that are defined above, in the sysreg.h style
>>>> + * of _MASK, _SHIFT and BIT().
>>>> + */
>>>
>>> ^^^ not really necessary. Instead the format requirement for below mentioned
>>> CORESIGHT_REG_VAL() macro might be relevant and should be mentioned.
>>>
>>>> +#define TRCIDR0_INSTP0_SHIFT 1
>>>> +#define TRCIDR0_INSTP0_MASK GENMASK(1, 0)
>>>> +#define TRCIDR0_TRCBB BIT(5)
>>>> +#define TRCIDR0_TRCCOND BIT(6)
>>>> +#define TRCIDR0_TRCCCI BIT(7)
>>>> +#define TRCIDR0_RETSTACK BIT(9)
>>>> +#define TRCIDR0_NUMEVENT_SHIFT 10
>>>> +#define TRCIDR0_NUMEVENT_MASK GENMASK(1, 0)
>>>> +#define TRCIDR0_QSUPP_SHIFT 15
>>>> +#define TRCIDR0_QSUPP_MASK GENMASK(1, 0)
>>>> +#define TRCIDR0_TSSIZE_SHIFT 24
>>>> +#define TRCIDR0_TSSIZE_MASK GENMASK(4, 0)
>>>> +
>>>> /*
>>>> * System instructions to access ETM registers.
>>>> * See ETMv4.4 spec ARM IHI0064F section 4.3.6 System instructions
>>>> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
>>>> index ff1dd2092ac5..1452c6038421 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-priv.h
>>>> +++ b/drivers/hwtracing/coresight/coresight-priv.h
>>>> @@ -36,6 +36,11 @@
>>>>
>>>> #define TIMEOUT_US 100
>>>> #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
>>>> +/*
>>>> + * Extract a field from a register where field is #defined in the form
>>>> + * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
>>>> + */
>>>
>>> Looking at the usage, <register_name> is already embedded in <filed_name>. So
>>> it requires <field_name>_SHIFT and <field_name>_MASK instead. Unless register
>>> name should be passed as separate argument (which actually might be better).
>>>
>>> REG_VAL(etmidr0, TRCIDR0_TSSIZE) ----> REG_VAL(etmidr0, TRCIDR0, TSSIZE)
>>
>> I don't see much difference here. So I am fine either way.
>>
>>>
>>> with some restructuring in the comment ..
>>>
>>> /*
>>> * Extract a field from a coresight register
>>> *
>>> * Required fields are defined as macros like the following
>>> *
>>> * <register_name>_<field_name>_MASK and <register_name>_<field_name>_SHIFT
>>> */
>>>
>>>> +#define REG_VAL(val, field) ((val & (field##_MASK << field##_SHIFT)) >> field##_SHIFT)
>>>
>>> This is too generic to be in a coresight header or it should just be
>>> named CORESIGHT_REG_VAL() instead, making it more specific for here.
>>>
>>> The build should fail in case any required macro definition is absent.
>>> I guess no more fortification is required in case macros are missing.
>>>
>>> However CORESIGHT_REG_VAL() is better placed in <coresight-etm4x.h>
>>> just before all the dependent SHIFT/MASK register field definition
>>> starts.
>>
>> Not necessarily. CORESIGHT_REG_VAL() is a generic function and doesn't
>> have anything specific to do with etm4x. We could reuse that for
>> cleaning up other drivers in CoreSight.
>>
>> Cheers
>> Suzuki
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