As the sg2042 uses different address for timer and mswi of its clint
device, it should follow the aclint format. For the previous patchs,
it only use only one address for both mtime and mtimer, this is can
not be parsed by OpenSBI. To resolve this, separate these two registers
in the dtb.
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
This patch can be tested with upstream SBI with the following patch:
1. https://lists.infradead.org/pipermail/opensbi/2023-November/005926.html
Changed from v4:
1. left T-HEAD aclint register in the bindings only.
2. improve the bindings commit message.
Changed from v3:
1. add all register in the bindings
Changed from v2:
1. Use reg-names to map the registers.
Changed from v1:
1. change the commit to address the reason for ABI change.
2. remove unnecessary link in the commit.
Inochi Amaoto (2):
dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and
mtimecmp regs
riscv: dts: sophgo: separate sg2042 mtime and mtimecmp to fit aclint
format
.../timer/thead,c900-aclint-mtimer.yaml | 9 ++-
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++--------
2 files changed, 56 insertions(+), 33 deletions(-)
--
2.43.0
The timer registers of aclint don't follow the clint layout and can
be mapped on any different offset. As sg2042 uses separated timer
and mswi for its clint, it should follow the aclint spec and have
separated registers.
The previous patch introduced a new type of T-HEAD aclint timer which
has clint timer layout. Although it has the clint timer layout, it
should follow the aclint spec and uses the separated mtime and mtimecmp
regs. So a ABI change is needed to make the timer fit the aclint spec.
To make T-HEAD aclint timer more closer to the aclint spec, use
regs-names to represent the mtimecmp register, which can avoid hack
for unsupport mtime register of T-HEAD aclint timer.
Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
implement the whole aclint spec. To make this binding T-HEAD specific,
only add reg-name for existed register. For details, see the discussion
in the last link.
Signed-off-by: Inochi Amaoto <[email protected]>
Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@IA1PR20MB4953.namprd20.prod.outlook.com/
---
.../bindings/timer/thead,c900-aclint-mtimer.yaml | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
index fbd235650e52..2e92bcdeb423 100644
--- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
+++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
@@ -17,7 +17,12 @@ properties:
- const: thead,c900-aclint-mtimer
reg:
- maxItems: 1
+ items:
+ - description: MTIMECMP Registers
+
+ reg-names:
+ items:
+ - const: mtimecmp
interrupts-extended:
minItems: 1
@@ -28,6 +33,7 @@ additionalProperties: false
required:
- compatible
- reg
+ - reg-names
- interrupts-extended
examples:
@@ -39,5 +45,6 @@ examples:
<&cpu3intc 7>,
<&cpu4intc 7>;
reg = <0xac000000 0x00010000>;
+ reg-names = "mtimecmp";
};
...
--
2.43.0
Change the timer layout in the dtb to fit the format that needed by
the SBI.
Signed-off-by: Inochi Amaoto <[email protected]>
Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
Reviewed-by: Chen Wang <[email protected]>
---
arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++++++-----------
1 file changed, 48 insertions(+), 32 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 93256540d078..ead1cc35d88b 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -93,144 +93,160 @@ clint_mswi: interrupt-controller@7094000000 {
<&cpu63_intc 3>;
};
- clint_mtimer0: timer@70ac000000 {
+ clint_mtimer0: timer@70ac004000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu0_intc 7>,
<&cpu1_intc 7>,
<&cpu2_intc 7>,
<&cpu3_intc 7>;
};
- clint_mtimer1: timer@70ac010000 {
+ clint_mtimer1: timer@70ac014000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu4_intc 7>,
<&cpu5_intc 7>,
<&cpu6_intc 7>,
<&cpu7_intc 7>;
};
- clint_mtimer2: timer@70ac020000 {
+ clint_mtimer2: timer@70ac024000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu8_intc 7>,
<&cpu9_intc 7>,
<&cpu10_intc 7>,
<&cpu11_intc 7>;
};
- clint_mtimer3: timer@70ac030000 {
+ clint_mtimer3: timer@70ac034000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu12_intc 7>,
<&cpu13_intc 7>,
<&cpu14_intc 7>,
<&cpu15_intc 7>;
};
- clint_mtimer4: timer@70ac040000 {
+ clint_mtimer4: timer@70ac044000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu16_intc 7>,
<&cpu17_intc 7>,
<&cpu18_intc 7>,
<&cpu19_intc 7>;
};
- clint_mtimer5: timer@70ac050000 {
+ clint_mtimer5: timer@70ac054000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu20_intc 7>,
<&cpu21_intc 7>,
<&cpu22_intc 7>,
<&cpu23_intc 7>;
};
- clint_mtimer6: timer@70ac060000 {
+ clint_mtimer6: timer@70ac064000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu24_intc 7>,
<&cpu25_intc 7>,
<&cpu26_intc 7>,
<&cpu27_intc 7>;
};
- clint_mtimer7: timer@70ac070000 {
+ clint_mtimer7: timer@70ac074000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu28_intc 7>,
<&cpu29_intc 7>,
<&cpu30_intc 7>,
<&cpu31_intc 7>;
};
- clint_mtimer8: timer@70ac080000 {
+ clint_mtimer8: timer@70ac084000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu32_intc 7>,
<&cpu33_intc 7>,
<&cpu34_intc 7>,
<&cpu35_intc 7>;
};
- clint_mtimer9: timer@70ac090000 {
+ clint_mtimer9: timer@70ac094000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu36_intc 7>,
<&cpu37_intc 7>,
<&cpu38_intc 7>,
<&cpu39_intc 7>;
};
- clint_mtimer10: timer@70ac0a0000 {
+ clint_mtimer10: timer@70ac0a4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu40_intc 7>,
<&cpu41_intc 7>,
<&cpu42_intc 7>,
<&cpu43_intc 7>;
};
- clint_mtimer11: timer@70ac0b0000 {
+ clint_mtimer11: timer@70ac0b4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu44_intc 7>,
<&cpu45_intc 7>,
<&cpu46_intc 7>,
<&cpu47_intc 7>;
};
- clint_mtimer12: timer@70ac0c0000 {
+ clint_mtimer12: timer@70ac0c4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu48_intc 7>,
<&cpu49_intc 7>,
<&cpu50_intc 7>,
<&cpu51_intc 7>;
};
- clint_mtimer13: timer@70ac0d0000 {
+ clint_mtimer13: timer@70ac0d4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu52_intc 7>,
<&cpu53_intc 7>,
<&cpu54_intc 7>,
<&cpu55_intc 7>;
};
- clint_mtimer14: timer@70ac0e0000 {
+ clint_mtimer14: timer@70ac0e4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu56_intc 7>,
<&cpu57_intc 7>,
<&cpu58_intc 7>,
<&cpu59_intc 7>;
};
- clint_mtimer15: timer@70ac0f0000 {
+ clint_mtimer15: timer@70ac0f4000 {
compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
- reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
+ reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
+ reg-names = "mtimecmp";
interrupts-extended = <&cpu60_intc 7>,
<&cpu61_intc 7>,
<&cpu62_intc 7>,
--
2.43.0
On Mon, Dec 4, 2023 at 5:51 PM Inochi Amaoto <[email protected]> wrote:
>
> Change the timer layout in the dtb to fit the format that needed by
> the SBI.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
> Fixes: 967a94a92aaa ("riscv: dts: add initial Sophgo SG2042 SoC device tree")
> Reviewed-by: Chen Wang <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/sg2042.dtsi | 80 +++++++++++++++-----------
> 1 file changed, 48 insertions(+), 32 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> index 93256540d078..ead1cc35d88b 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
> @@ -93,144 +93,160 @@ clint_mswi: interrupt-controller@7094000000 {
> <&cpu63_intc 3>;
> };
>
> - clint_mtimer0: timer@70ac000000 {
> + clint_mtimer0: timer@70ac004000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac000000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu0_intc 7>,
> <&cpu1_intc 7>,
> <&cpu2_intc 7>,
> <&cpu3_intc 7>;
> };
>
> - clint_mtimer1: timer@70ac010000 {
> + clint_mtimer1: timer@70ac014000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac010000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu4_intc 7>,
> <&cpu5_intc 7>,
> <&cpu6_intc 7>,
> <&cpu7_intc 7>;
> };
>
> - clint_mtimer2: timer@70ac020000 {
> + clint_mtimer2: timer@70ac024000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac020000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu8_intc 7>,
> <&cpu9_intc 7>,
> <&cpu10_intc 7>,
> <&cpu11_intc 7>;
> };
>
> - clint_mtimer3: timer@70ac030000 {
> + clint_mtimer3: timer@70ac034000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac030000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu12_intc 7>,
> <&cpu13_intc 7>,
> <&cpu14_intc 7>,
> <&cpu15_intc 7>;
> };
>
> - clint_mtimer4: timer@70ac040000 {
> + clint_mtimer4: timer@70ac044000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac040000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu16_intc 7>,
> <&cpu17_intc 7>,
> <&cpu18_intc 7>,
> <&cpu19_intc 7>;
> };
>
> - clint_mtimer5: timer@70ac050000 {
> + clint_mtimer5: timer@70ac054000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac050000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu20_intc 7>,
> <&cpu21_intc 7>,
> <&cpu22_intc 7>,
> <&cpu23_intc 7>;
> };
>
> - clint_mtimer6: timer@70ac060000 {
> + clint_mtimer6: timer@70ac064000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac060000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu24_intc 7>,
> <&cpu25_intc 7>,
> <&cpu26_intc 7>,
> <&cpu27_intc 7>;
> };
>
> - clint_mtimer7: timer@70ac070000 {
> + clint_mtimer7: timer@70ac074000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac070000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu28_intc 7>,
> <&cpu29_intc 7>,
> <&cpu30_intc 7>,
> <&cpu31_intc 7>;
> };
>
> - clint_mtimer8: timer@70ac080000 {
> + clint_mtimer8: timer@70ac084000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac080000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu32_intc 7>,
> <&cpu33_intc 7>,
> <&cpu34_intc 7>,
> <&cpu35_intc 7>;
> };
>
> - clint_mtimer9: timer@70ac090000 {
> + clint_mtimer9: timer@70ac094000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac090000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu36_intc 7>,
> <&cpu37_intc 7>,
> <&cpu38_intc 7>,
> <&cpu39_intc 7>;
> };
>
> - clint_mtimer10: timer@70ac0a0000 {
> + clint_mtimer10: timer@70ac0a4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0a0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu40_intc 7>,
> <&cpu41_intc 7>,
> <&cpu42_intc 7>,
> <&cpu43_intc 7>;
> };
>
> - clint_mtimer11: timer@70ac0b0000 {
> + clint_mtimer11: timer@70ac0b4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0b0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu44_intc 7>,
> <&cpu45_intc 7>,
> <&cpu46_intc 7>,
> <&cpu47_intc 7>;
> };
>
> - clint_mtimer12: timer@70ac0c0000 {
> + clint_mtimer12: timer@70ac0c4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0c0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu48_intc 7>,
> <&cpu49_intc 7>,
> <&cpu50_intc 7>,
> <&cpu51_intc 7>;
> };
>
> - clint_mtimer13: timer@70ac0d0000 {
> + clint_mtimer13: timer@70ac0d4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0d0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu52_intc 7>,
> <&cpu53_intc 7>,
> <&cpu54_intc 7>,
> <&cpu55_intc 7>;
> };
>
> - clint_mtimer14: timer@70ac0e0000 {
> + clint_mtimer14: timer@70ac0e4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0e0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu56_intc 7>,
> <&cpu57_intc 7>,
> <&cpu58_intc 7>,
> <&cpu59_intc 7>;
> };
>
> - clint_mtimer15: timer@70ac0f0000 {
> + clint_mtimer15: timer@70ac0f4000 {
> compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
> - reg = <0x00000070 0xac0f0000 0x00000000 0x00007ff8>;
> + reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
> + reg-names = "mtimecmp";
> interrupts-extended = <&cpu60_intc 7>,
> <&cpu61_intc 7>,
> <&cpu62_intc 7>,
> --
> 2.43.0
>
Reviewed-by: Guo Ren <[email protected]>
--
Best Regards
Guo Ren
On Mon, Dec 4, 2023 at 5:51 PM Inochi Amaoto <[email protected]> wrote:
>
> The timer registers of aclint don't follow the clint layout and can
> be mapped on any different offset. As sg2042 uses separated timer
> and mswi for its clint, it should follow the aclint spec and have
> separated registers.
>
> The previous patch introduced a new type of T-HEAD aclint timer which
> has clint timer layout. Although it has the clint timer layout, it
> should follow the aclint spec and uses the separated mtime and mtimecmp
> regs. So a ABI change is needed to make the timer fit the aclint spec.
>
> To make T-HEAD aclint timer more closer to the aclint spec, use
> regs-names to represent the mtimecmp register, which can avoid hack
> for unsupport mtime register of T-HEAD aclint timer.
>
> Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
> implement the whole aclint spec. To make this binding T-HEAD specific,
> only add reg-name for existed register. For details, see the discussion
> in the last link.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
> Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
> Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@IA1PR20MB4953.namprd20.prod.outlook.com/
> ---
> .../bindings/timer/thead,c900-aclint-mtimer.yaml | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
> index fbd235650e52..2e92bcdeb423 100644
> --- a/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
> +++ b/Documentation/devicetree/bindings/timer/thead,c900-aclint-mtimer.yaml
> @@ -17,7 +17,12 @@ properties:
> - const: thead,c900-aclint-mtimer
>
> reg:
> - maxItems: 1
> + items:
> + - description: MTIMECMP Registers
> +
> + reg-names:
> + items:
> + - const: mtimecmp
>
> interrupts-extended:
> minItems: 1
> @@ -28,6 +33,7 @@ additionalProperties: false
> required:
> - compatible
> - reg
> + - reg-names
> - interrupts-extended
>
> examples:
> @@ -39,5 +45,6 @@ examples:
> <&cpu3intc 7>,
> <&cpu4intc 7>;
> reg = <0xac000000 0x00010000>;
> + reg-names = "mtimecmp";
> };
> ...
> --
> 2.43.0
>
Acked-by: Guo Ren <[email protected]>
--
Best Regards
Guo Ren
On Mon, Dec 04, 2023 at 05:51:08PM +0800, Inochi Amaoto wrote:
> The timer registers of aclint don't follow the clint layout and can
> be mapped on any different offset. As sg2042 uses separated timer
> and mswi for its clint, it should follow the aclint spec and have
> separated registers.
>
> The previous patch introduced a new type of T-HEAD aclint timer which
> has clint timer layout. Although it has the clint timer layout, it
> should follow the aclint spec and uses the separated mtime and mtimecmp
> regs. So a ABI change is needed to make the timer fit the aclint spec.
>
> To make T-HEAD aclint timer more closer to the aclint spec, use
> regs-names to represent the mtimecmp register, which can avoid hack
> for unsupport mtime register of T-HEAD aclint timer.
>
> Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
> implement the whole aclint spec. To make this binding T-HEAD specific,
> only add reg-name for existed register. For details, see the discussion
> in the last link.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
> Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
> Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@IA1PR20MB4953.namprd20.prod.outlook.com/
Acked-by: Conor Dooley <[email protected]>
Although, I figure it is going to be me that ends up taking it.
Cheers,
Conor.
On 04/12/2023 17:18, Conor Dooley wrote:
> On Mon, Dec 04, 2023 at 05:51:08PM +0800, Inochi Amaoto wrote:
>> The timer registers of aclint don't follow the clint layout and can
>> be mapped on any different offset. As sg2042 uses separated timer
>> and mswi for its clint, it should follow the aclint spec and have
>> separated registers.
>>
>> The previous patch introduced a new type of T-HEAD aclint timer which
>> has clint timer layout. Although it has the clint timer layout, it
>> should follow the aclint spec and uses the separated mtime and mtimecmp
>> regs. So a ABI change is needed to make the timer fit the aclint spec.
>>
>> To make T-HEAD aclint timer more closer to the aclint spec, use
>> regs-names to represent the mtimecmp register, which can avoid hack
>> for unsupport mtime register of T-HEAD aclint timer.
>>
>> Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
>> implement the whole aclint spec. To make this binding T-HEAD specific,
>> only add reg-name for existed register. For details, see the discussion
>> in the last link.
>>
>> Signed-off-by: Inochi Amaoto <[email protected]>
>> Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
>> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
>> Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>> Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@IA1PR20MB4953.namprd20.prod.outlook.com/
>
> Acked-by: Conor Dooley <[email protected]>
>
> Although, I figure it is going to be me that ends up taking it.
No, I should take it
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On Mon, Dec 04, 2023 at 05:39:09PM +0100, Daniel Lezcano wrote:
> On 04/12/2023 17:18, Conor Dooley wrote:
> > On Mon, Dec 04, 2023 at 05:51:08PM +0800, Inochi Amaoto wrote:
> > > The timer registers of aclint don't follow the clint layout and can
> > > be mapped on any different offset. As sg2042 uses separated timer
> > > and mswi for its clint, it should follow the aclint spec and have
> > > separated registers.
> > >
> > > The previous patch introduced a new type of T-HEAD aclint timer which
> > > has clint timer layout. Although it has the clint timer layout, it
> > > should follow the aclint spec and uses the separated mtime and mtimecmp
> > > regs. So a ABI change is needed to make the timer fit the aclint spec.
> > >
> > > To make T-HEAD aclint timer more closer to the aclint spec, use
> > > regs-names to represent the mtimecmp register, which can avoid hack
> > > for unsupport mtime register of T-HEAD aclint timer.
> > >
> > > Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
> > > implement the whole aclint spec. To make this binding T-HEAD specific,
> > > only add reg-name for existed register. For details, see the discussion
> > > in the last link.
> > >
> > > Signed-off-by: Inochi Amaoto <[email protected]>
> > > Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
> > > Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
> > > Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> > > Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@IA1PR20MB4953.namprd20.prod.outlook.com/
> >
> > Acked-by: Conor Dooley <[email protected]>
> >
> > Although, I figure it is going to be me that ends up taking it.
>
> No, I should take it
Sweet, I'd rather you took it than it went via a DT tree :)
On 04/12/2023 10:51, Inochi Amaoto wrote:
> The timer registers of aclint don't follow the clint layout and can
> be mapped on any different offset. As sg2042 uses separated timer
> and mswi for its clint, it should follow the aclint spec and have
> separated registers.
>
> The previous patch introduced a new type of T-HEAD aclint timer which
> has clint timer layout. Although it has the clint timer layout, it
> should follow the aclint spec and uses the separated mtime and mtimecmp
> regs. So a ABI change is needed to make the timer fit the aclint spec.
>
> To make T-HEAD aclint timer more closer to the aclint spec, use
> regs-names to represent the mtimecmp register, which can avoid hack
> for unsupport mtime register of T-HEAD aclint timer.
>
> Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
> implement the whole aclint spec. To make this binding T-HEAD specific,
> only add reg-name for existed register. For details, see the discussion
> in the last link.
>
> Signed-off-by: Inochi Amaoto <[email protected]>
> Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
> Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@IA1PR20MB4953.namprd20.prod.outlook.com/
> ---
Applied 1/2, thanks
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>On Mon, Dec 04, 2023 at 05:39:09PM +0100, Daniel Lezcano wrote:
>> On 04/12/2023 17:18, Conor Dooley wrote:
>>> On Mon, Dec 04, 2023 at 05:51:08PM +0800, Inochi Amaoto wrote:
>>>> The timer registers of aclint don't follow the clint layout and can
>>>> be mapped on any different offset. As sg2042 uses separated timer
>>>> and mswi for its clint, it should follow the aclint spec and have
>>>> separated registers.
>>>>
>>>> The previous patch introduced a new type of T-HEAD aclint timer which
>>>> has clint timer layout. Although it has the clint timer layout, it
>>>> should follow the aclint spec and uses the separated mtime and mtimecmp
>>>> regs. So a ABI change is needed to make the timer fit the aclint spec.
>>>>
>>>> To make T-HEAD aclint timer more closer to the aclint spec, use
>>>> regs-names to represent the mtimecmp register, which can avoid hack
>>>> for unsupport mtime register of T-HEAD aclint timer.
>>>>
>>>> Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
>>>> implement the whole aclint spec. To make this binding T-HEAD specific,
>>>> only add reg-name for existed register. For details, see the discussion
>>>> in the last link.
>>>>
>>>> Signed-off-by: Inochi Amaoto <[email protected]>
>>>> Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
>>>> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
>>>> Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>>>> Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@IA1PR20MB4953.namprd20.prod.outlook.com/
>>>
>>> Acked-by: Conor Dooley <[email protected]>
>>>
>>> Although, I figure it is going to be me that ends up taking it.
>>
>> No, I should take it
>
>Sweet, I'd rather you took it than it went via a DT tree :)
>
Thanks you both for taking this. This is good news for me.
Hi Conor,
I have already noticed the binding is merged. But the dt patch is not,
I wonder if it is the time to merge this dt change?
Regards,
Inochi