StarFive's JH8100 StarLink Cache Controller flush/invalidates cache using non-
conventional RISC-V Zicbom extension instructions. This driver provides the
cache handling on StarFive RISC-V SoC.
Changes in v3:
- Fix code syntax
- Link to v2: https://lore.kernel.org/all/[email protected]/
Changes in v2:
- Change patch title from 'Add StarFive's StarLink-500 Cache Controller'
- Remove StarFive alternative from errata framework
- Fixes warning from https://lore.kernel.org/oe-kbuild-all/[email protected]/
- Flush completion through atomic timeout function
- Link to v1: https://lore.kernel.org/lkml/[email protected]/
Joshua Yeong (2):
cache: Add StarFive StarLink cache management for StarFive JH8100
dt-bindings: cache: Add docs for StarFive Starlink cache controller
.../cache/starfive,jh8100-starlink-cache.yaml | 66 +++++++++
drivers/cache/Kconfig | 9 ++
drivers/cache/Makefile | 5 +-
drivers/cache/starfive_starlink_cache.c | 135 ++++++++++++++++++
4 files changed, 213 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
create mode 100644 drivers/cache/starfive_starlink_cache.c
--
2.25.1
Joshua Yeong wrote:
> StarFive's JH8100 StarLink Cache Controller flush/invalidates cache using non-
> conventional RISC-V Zicbom extension instructions. This driver provides the
> cache handling on StarFive RISC-V SoC.
Hi Joshua,
As far as I know you didn't tape out the JH8100 yet, and you seem to have
replaced the SiFive cache controller with your own implementation. Can you
exlain a bit more about why you didn't implement the perfectly good Zicbom
standard instead of adding yet another non-standard work-around like this?
/Emil
>
> Changes in v3:
> - Fix code syntax
> - Link to v2: https://lore.kernel.org/all/[email protected]/
>
> Changes in v2:
> - Change patch title from 'Add StarFive's StarLink-500 Cache Controller'
> - Remove StarFive alternative from errata framework
> - Fixes warning from https://lore.kernel.org/oe-kbuild-all/[email protected]/
> - Flush completion through atomic timeout function
> - Link to v1: https://lore.kernel.org/lkml/[email protected]/
>
> Joshua Yeong (2):
> cache: Add StarFive StarLink cache management for StarFive JH8100
> dt-bindings: cache: Add docs for StarFive Starlink cache controller
>
> .../cache/starfive,jh8100-starlink-cache.yaml | 66 +++++++++
> drivers/cache/Kconfig | 9 ++
> drivers/cache/Makefile | 5 +-
> drivers/cache/starfive_starlink_cache.c | 135 ++++++++++++++++++
> 4 files changed, 213 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache.yaml
> create mode 100644 drivers/cache/starfive_starlink_cache.c
>
> --
> 2.25.1
>
>
> _______________________________________________
> linux-riscv mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-riscv
Emil Renner Berthing :
> Joshua Yeong wrote:
> > StarFive's JH8100 StarLink Cache Controller flush/invalidates cache
> > using non- conventional RISC-V Zicbom extension instructions. This
> > driver provides the cache handling on StarFive RISC-V SoC.
>
> Hi Joshua,
>
> As far as I know you didn't tape out the JH8100 yet, and you seem to have
> replaced the SiFive cache controller with your own implementation. Can you
> exlain a bit more about why you didn't implement the perfectly good Zicbom
> standard instead of adding yet another non-standard work-around like this?
>
> /Emil
Hi Emil,
I agree that the Zicbom standard is an important extension and future-
designed SoC should have this. In the V1 patch, I mentioned that the CPU core
used in JH8100 is matured, but unfortunately, it did not support the Zicbom
extension. JH8100 integrates 'Starlink-500' IP (more information homepage),
an in-house designed interconnect between peripherals and CPU to handle
cache management operations.
Regards,
Joshua
>
> > Changes in v3:
> > - Fix code syntax
> > - Link to v2:
> > https://lore.kernel.org/all/20240423072639.143450-1-
> joshua.yeong@starf
> > ivetech.com/
> >
> > Changes in v2:
> > - Change patch title from 'Add StarFive's StarLink-500 Cache Controller'
> > - Remove StarFive alternative from errata framework
> > - Fixes warning from
> > https://lore.kernel.org/oe-kbuild-all/202403151625.boKDjHGr-lkp@intel.
> > com/
> > - Flush completion through atomic timeout function
> > - Link to v1:
> > https://lore.kernel.org/lkml/20240314061205.26143-1-
> joshua.yeong@starf
> > ivetech.com/
> >
> > Joshua Yeong (2):
> > cache: Add StarFive StarLink cache management for StarFive JH8100
> > dt-bindings: cache: Add docs for StarFive Starlink cache controller
> >
> > .../cache/starfive,jh8100-starlink-cache.yaml | 66 +++++++++
> > drivers/cache/Kconfig | 9 ++
> > drivers/cache/Makefile | 5 +-
> > drivers/cache/starfive_starlink_cache.c | 135 ++++++++++++++++++
> > 4 files changed, 213 insertions(+), 2 deletions(-) create mode
> > 100644
> > Documentation/devicetree/bindings/cache/starfive,jh8100-starlink-cache
> > .yaml create mode 100644 drivers/cache/starfive_starlink_cache.c
> >
> > --
> > 2.25.1
> >
> >
> > _______________________________________________
> > linux-riscv mailing list
> > [email protected]
> > http://lists.infradead.org/mailman/listinfo/linux-riscv