The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
it impossible to use the ICAP interface for partial reconfiguration.
This patch changes the driver to only activate PR over PCAP while the
device is actively being accessed by the driver for programming.
This allows both PCAP and ICAP interfaces to be used for PR.
Signed-off-by: Mike Looijmans <[email protected]>
---
drivers/fpga/zynq-fpga.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index 3110e00..f6c205a 100644
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
int err;
u32 intr_status;
+ /* Release 'PR' control back to the ICAP */
+ zynq_fpga_write(priv, CTRL_OFFSET,
+ zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
+
err = clk_enable(priv->clk);
if (err)
return err;
--
1.9.1
Hi Mike,
seems like a good usecase (though uncommon), question below
On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote:
> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
> it impossible to use the ICAP interface for partial reconfiguration.
>
> This patch changes the driver to only activate PR over PCAP while the
> device is actively being accessed by the driver for programming.
>
> This allows both PCAP and ICAP interfaces to be used for PR.
>
> Signed-off-by: Mike Looijmans <[email protected]>
> ---
> drivers/fpga/zynq-fpga.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 3110e00..f6c205a 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
> int err;
> u32 intr_status;
>
> + /* Release 'PR' control back to the ICAP */
> + zynq_fpga_write(priv, CTRL_OFFSET,
> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
> +
Shouldn't that be after the below stanza that enables the clock?
> err = clk_enable(priv->clk);
> if (err)
> return err;
> --
> 1.9.1
>
Cheers,
Moritz
On 23-10-18 11:01, Moritz Fischer wrote:
> Hi Mike,
>
> seems like a good usecase (though uncommon), question below
Usecases for ICAP:
- It's considerably faster than PCAP
- Self-repairing logic (e.g. single-event upsets)
- Being programmed from a remote FPGA
- Programming through another bus (e.g. PCIe)
>
> On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote:
>> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
>> it impossible to use the ICAP interface for partial reconfiguration.
>>
>> This patch changes the driver to only activate PR over PCAP while the
>> device is actively being accessed by the driver for programming.
>>
>> This allows both PCAP and ICAP interfaces to be used for PR.
>>
>> Signed-off-by: Mike Looijmans <[email protected]>
>> ---
>> drivers/fpga/zynq-fpga.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
>> index 3110e00..f6c205a 100644
>> --- a/drivers/fpga/zynq-fpga.c
>> +++ b/drivers/fpga/zynq-fpga.c
>> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
>> int err;
>> u32 intr_status;
>>
>> + /* Release 'PR' control back to the ICAP */
>> + zynq_fpga_write(priv, CTRL_OFFSET,
>> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
>> +
>
> Shouldn't that be after the below stanza that enables the clock?
I'm actually not sure, and I did not encounter any problems while testing
this, but it's easier to just move it than to find out, so I'll go for "yes,
let's enable the clock first".
I'll await a bit more feedback and post a v2 for that.
>
>> err = clk_enable(priv->clk);
>> if (err)
>> return err;
>> --
>> 1.9.1
>>
>
> Cheers,
>
> Moritz
>
Hi Mike,
On Tue, Oct 23, 2018 at 10:53:50AM +0000, Mike Looijmans wrote:
> On 23-10-18 11:01, Moritz Fischer wrote:
> > Hi Mike,
> >
> > seems like a good usecase (though uncommon), question below
>
> Usecases for ICAP:
> - It's considerably faster than PCAP
> - Self-repairing logic (e.g. single-event upsets)
> - Being programmed from a remote FPGA
> - Programming through another bus (e.g. PCIe)
Yeah, I wasn't saying it's a bad usecase, just not super common :)
>
>
> >
> > On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote:
> >> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
> >> it impossible to use the ICAP interface for partial reconfiguration.
> >>
> >> This patch changes the driver to only activate PR over PCAP while the
> >> device is actively being accessed by the driver for programming.
> >>
> >> This allows both PCAP and ICAP interfaces to be used for PR.
> >>
> >> Signed-off-by: Mike Looijmans <[email protected]>
> >> ---
> >> drivers/fpga/zynq-fpga.c | 4 ++++
> >> 1 file changed, 4 insertions(+)
> >>
> >> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> >> index 3110e00..f6c205a 100644
> >> --- a/drivers/fpga/zynq-fpga.c
> >> +++ b/drivers/fpga/zynq-fpga.c
> >> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
> >> int err;
> >> u32 intr_status;
> >>
> >> + /* Release 'PR' control back to the ICAP */
> >> + zynq_fpga_write(priv, CTRL_OFFSET,
> >> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
> >> +
> >
> > Shouldn't that be after the below stanza that enables the clock?
>
> I'm actually not sure, and I did not encounter any problems while testing
> this, but it's easier to just move it than to find out, so I'll go for "yes,
> let's enable the clock first".
> I'll await a bit more feedback and post a v2 for that.
Ok, I had suspected you tested it and probably didn't run into issues,
but just wanted to make sure we think about it. If you don't mind, swap
it around as I suggested just to be safe.
With that change feel free to add my Reviewed-by: Moritz Fischer
<[email protected]> in your v2.
Thanks for the patch,
Moritz
The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
it impossible to use the ICAP interface for partial reconfiguration.
This patch changes the driver to only activate PR over PCAP while the
device is actively being accessed by the driver for programming.
This allows both PCAP and ICAP interfaces to be used for PR.
Signed-off-by: Mike Looijmans <[email protected]>
Reviewed-by: Moritz Fischer <[email protected]>
---
v2: Move the register setting in between the clock enable/disable
drivers/fpga/zynq-fpga.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index 3110e00..ff3a427 100644
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
if (err)
return err;
+ /* Release 'PR' control back to the ICAP */
+ zynq_fpga_write(priv, CTRL_OFFSET,
+ zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
+
err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
intr_status & IXR_PCFG_DONE_MASK,
INIT_POLL_DELAY,
--
1.9.1
On 23. 10. 18 13:04, Moritz Fischer wrote:
> Hi Mike,
>
> On Tue, Oct 23, 2018 at 10:53:50AM +0000, Mike Looijmans wrote:
>> On 23-10-18 11:01, Moritz Fischer wrote:
>>> Hi Mike,
>>>
>>> seems like a good usecase (though uncommon), question below
>>
>> Usecases for ICAP:
>> - It's considerably faster than PCAP
>> - Self-repairing logic (e.g. single-event upsets)
>> - Being programmed from a remote FPGA
>> - Programming through another bus (e.g. PCIe)
>
> Yeah, I wasn't saying it's a bad usecase, just not super common :)
>
>>
>>
>>>
>>> On Tue, Oct 23, 2018 at 08:31:19AM +0200, Mike Looijmans wrote:
>>>> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
>>>> it impossible to use the ICAP interface for partial reconfiguration.
>>>>
>>>> This patch changes the driver to only activate PR over PCAP while the
>>>> device is actively being accessed by the driver for programming.
>>>>
>>>> This allows both PCAP and ICAP interfaces to be used for PR.
>>>>
>>>> Signed-off-by: Mike Looijmans <[email protected]>
>>>> ---
>>>> drivers/fpga/zynq-fpga.c | 4 ++++
>>>> 1 file changed, 4 insertions(+)
>>>>
>>>> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
>>>> index 3110e00..f6c205a 100644
>>>> --- a/drivers/fpga/zynq-fpga.c
>>>> +++ b/drivers/fpga/zynq-fpga.c
>>>> @@ -497,6 +497,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
>>>> int err;
>>>> u32 intr_status;
>>>>
>>>> + /* Release 'PR' control back to the ICAP */
>>>> + zynq_fpga_write(priv, CTRL_OFFSET,
>>>> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
>>>> +
>>>
>>> Shouldn't that be after the below stanza that enables the clock?
>>
>> I'm actually not sure, and I did not encounter any problems while testing
>> this, but it's easier to just move it than to find out, so I'll go for "yes,
>> let's enable the clock first".
>> I'll await a bit more feedback and post a v2 for that.
>
> Ok, I had suspected you tested it and probably didn't run into issues,
> but just wanted to make sure we think about it. If you don't mind, swap
> it around as I suggested just to be safe.
>
> With that change feel free to add my Reviewed-by: Moritz Fischer
> <[email protected]> in your v2.
That clock can be used by something else that's why you didn't observe
any issue. Anyway I have no problem with reverting that setting back
that icap can be used.
In general there should be synchronization mechanism for this. And also
driver "feature" not to enable access from icap for security reason. But
that's something what should be done in other patch.
Thanks,
Michal
Hi Michal,
On Fri, Oct 26, 2018 at 12:54 AM Michal Simek <[email protected]> wrote:
> > Ok, I had suspected you tested it and probably didn't run into issues,
> > but just wanted to make sure we think about it. If you don't mind, swap
> > it around as I suggested just to be safe.
> >
> > With that change feel free to add my Reviewed-by: Moritz Fischer
> > <[email protected]> in your v2.
>
> That clock can be used by something else that's why you didn't observe
> any issue. Anyway I have no problem with reverting that setting back
> that icap can be used.
Ok, thanks for clarification, that was what I assumed :)
> In general there should be synchronization mechanism for this. And also
> driver "feature" not to enable access from icap for security reason. But
> that's something what should be done in other patch.
Yeah I'll have to look at remote notifications for FPGA managers
soon-ish for another
project as discussed at ELCE. Part of that would be synchronization I guess :)
Umhh, based on the secure state read from CTRL_SEC_EN bit, or did you
think along the
lines of "xlnx,no-icap" property that your bootloader / dt would provide?
Cheers,
Moritz
On Wed, Oct 24, 2018 at 2:53 AM Mike Looijmans <[email protected]> wrote:
Hi Mike,
>
> The Xilinx Zynq FPGA driver takes ownership of the PR interface, making
> it impossible to use the ICAP interface for partial reconfiguration.
>
> This patch changes the driver to only activate PR over PCAP while the
> device is actively being accessed by the driver for programming.
>
> This allows both PCAP and ICAP interfaces to be used for PR.
>
> Signed-off-by: Mike Looijmans <[email protected]>
> Reviewed-by: Moritz Fischer <[email protected]>
Acked-by: Alan Tull <[email protected]>
Thanks for submitting!
Alan
> ---
> v2: Move the register setting in between the clock enable/disable
>
> drivers/fpga/zynq-fpga.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 3110e00..ff3a427 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -501,6 +501,10 @@ static int zynq_fpga_ops_write_complete(struct fpga_manager *mgr,
> if (err)
> return err;
>
> + /* Release 'PR' control back to the ICAP */
> + zynq_fpga_write(priv, CTRL_OFFSET,
> + zynq_fpga_read(priv, CTRL_OFFSET) & ~CTRL_PCAP_PR_MASK);
> +
> err = zynq_fpga_poll_timeout(priv, INT_STS_OFFSET, intr_status,
> intr_status & IXR_PCFG_DONE_MASK,
> INIT_POLL_DELAY,
> --
> 1.9.1
>