2012-10-31 06:47:41

by Jonghwan Choi

Subject: [PATCH v2 1/2] thermal: exynos: Fix wrong bit to control tmu core

[0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.

Signed-off-by: Jonghwan Choi <[email protected]>
---
drivers/thermal/exynos_thermal.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/exynos_thermal.c
b/drivers/thermal/exynos_thermal.c
index fd03e85..6ce6667 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -53,8 +53,8 @@
#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
#define EXYNOS_TMU_GAIN_SHIFT 8
#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
-#define EXYNOS_TMU_CORE_ON 3
-#define EXYNOS_TMU_CORE_OFF 2
+#define EXYNOS_TMU_CORE_ON 1
+#define EXYNOS_TMU_CORE_OFF 0
#define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50

/* Exynos4210 specific registers */
--
1.7.4.1

2012-11-08 11:23:48

by Amit Kachhap

Subject: Re: [PATCH v2 1/2] thermal: exynos: Fix wrong bit to control tmu core

Hi

On 31 October 2012 12:17, Jonghwan Choi <[email protected]> wrote:
> [0]bit is used to enable/disable tmu core. [1] bit is a reserved bit.
>
> Signed-off-by: Jonghwan Choi <[email protected]>
> ---
> drivers/thermal/exynos_thermal.c | 4 ++--
> 1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/thermal/exynos_thermal.c
> b/drivers/thermal/exynos_thermal.c
> index fd03e85..6ce6667 100644
> --- a/drivers/thermal/exynos_thermal.c
> +++ b/drivers/thermal/exynos_thermal.c
> @@ -53,8 +53,8 @@
> #define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
> #define EXYNOS_TMU_GAIN_SHIFT 8
> #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
> -#define EXYNOS_TMU_CORE_ON 3
> -#define EXYNOS_TMU_CORE_OFF 2
> +#define EXYNOS_TMU_CORE_ON 1
> +#define EXYNOS_TMU_CORE_OFF 0
Hi Jonghwan,

Only this much change is not sufficient. Also you need to do like below,

diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index eebd4e5..4575144 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -52,9 +52,11 @@

#define EXYNOS_TMU_TRIM_TEMP_MASK 0xff
#define EXYNOS_TMU_GAIN_SHIFT 8
+#define EXYNOS_TMU_GAIN_MASK (0xF << 8)
#define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24
-#define EXYNOS_TMU_CORE_ON 3
-#define EXYNOS_TMU_CORE_OFF 2
+#define EXYNOS_TMU_REF_VOLTAGE_MASK (0x1F << 24)
+#define EXYNOS_TMU_CORE_ON 1
+#define EXYNOS_TMU_CORE_OFF 0
#define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50

/* Exynos4210 specific registers */
@@ -85,7 +87,9 @@
#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 16)
#define EXYNOS_MUX_ADDR_VALUE 6
#define EXYNOS_MUX_ADDR_SHIFT 20
+#define EXYNOS_MUX_ADDR_MASK (0xFF << 16)
#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
+#define EXYNOS_TMU_TRIP_MODE_MASK (0x7 << 13)

#define EFUSE_MIN_VALUE 40
#define EFUSE_MAX_VALUE 100
@@ -658,10 +662,13 @@ static void exynos_tmu_control(struct
platform_device *pdev, bool on)
mutex_lock(&data->lock);
clk_enable(data->clk);

- con = pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
+ con = readl(data->base + EXYNOS_TMU_REG_CONTROL);
+ con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK | EXYNOS_TMU_GAIN_MASK);
+ con |= pdata->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT |
pdata->gain << EXYNOS_TMU_GAIN_SHIFT;

if (data->soc == SOC_ARCH_EXYNOS) {
+ con &= ~(EXYNOS_TMU_TRIP_MODE_MASK | EXYNOS_MUX_ADDR_MASK);
con |= pdata->noise_cancel_mode << EXYNOS_TMU_TRIP_MODE_SHIFT;
con |= (EXYNOS_MUX_ADDR_VALUE << EXYNOS_MUX_ADDR_SHIFT);
}

Thanks,
Amit Daniel

> #define EXYNOS_TMU_DEF_CODE_TO_TEMP_OFFSET 50
>
> /* Exynos4210 specific registers */
> --
> 1.7.4.1
>