This series adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older
SoC but still commonly found on eBay, mostly in Supermicro X9 server boards.
Third-party documentation is available at: https://github.com/neuschaefer/wpcm450/wiki
Patches 1-4 add devicetree bindings for the WPCM450 SoC and its various parts.
Patches 5-7 add arch and driver support. Patches 8 and 9 add a devicetree for
the SoC and a board based on it. Patch 10 finally updates the MAINTAINERS file.
Patch 2 requires "dt-bindings: arm: Convert nuvoton,npcm750 binding to YAML"
(https://lore.kernel.org/lkml/[email protected]/)
v2:
- Various improvements to the AIC irqchip driver, thanks to Marc Zyngier's review
- I dropped the timer patches, which have been applied by Daniel Lezcano
- I dropped the serial patches, which have been applied to tty-next by Greg KH
v1:
- https://lore.kernel.org/lkml/[email protected]/
Jonathan Neuschäfer (10):
dt-bindings: vendor-prefixes: Add Supermicro
dt-bindings: arm: npcm: Add nuvoton,wpcm450 compatible string
dt-bindings: interrupt-controller: Add nuvoton,wpcm450-aic
dt-bindings: watchdog: npcm: Add nuvoton,wpcm450-wdt
ARM: npcm: Introduce Nuvoton WPCM450 SoC
irqchip: Add driver for WPCM450 interrupt controller
watchdog: npcm: Add support for WPCM450
ARM: dts: Add devicetree for Nuvoton WPCM450 BMC chip
ARM: dts: Add devicetree for Supermicro X9SCi-LN4F based on WPCM450
MAINTAINERS: Add entry for Nuvoton WPCM450
.../devicetree/bindings/arm/npcm/npcm.yaml | 6 +
.../nuvoton,wpcm450-aic.yaml | 39 +++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
.../bindings/watchdog/nuvoton,npcm-wdt.txt | 3 +-
MAINTAINERS | 9 +
arch/arm/boot/dts/Makefile | 2 +
.../nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 40 +++++
arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 76 +++++++++
arch/arm/mach-npcm/Kconfig | 13 +-
arch/arm/mach-npcm/Makefile | 1 +
arch/arm/mach-npcm/wpcm450.c | 13 ++
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-wpcm450-aic.c | 161 ++++++++++++++++++
drivers/watchdog/npcm_wdt.c | 1 +
15 files changed, 371 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
create mode 100644 arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts
create mode 100644 arch/arm/boot/dts/nuvoton-wpcm450.dtsi
create mode 100644 arch/arm/mach-npcm/wpcm450.c
create mode 100644 drivers/irqchip/irq-wpcm450-aic.c
--
2.30.2
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally
marketed as Winbond WPCM450.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
This patch requires "dt-bindings: arm: Convert nuvoton,npcm750 binding to YAML"
(https://lore.kernel.org/lkml/[email protected]/)
v2:
- Added Rob's ACK
---
Documentation/devicetree/bindings/arm/npcm/npcm.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
index 894aefb70652a..95e51378089c9 100644
--- a/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
+++ b/Documentation/devicetree/bindings/arm/npcm/npcm.yaml
@@ -14,6 +14,12 @@ properties:
const: '/'
compatible:
oneOf:
+ - description: WPCM450 based boards
+ items:
+ - enum:
+ - supermicro,x9sci-ln4f-bmc # Supermicro X9SCI-LN4F server's BMC
+ - const: nuvoton,wpcm450
+
- description: NPCM750 based boards
items:
- enum:
--
2.30.2
Add a compatible string for the WPCM450 SoC, which has the same watchdog
timer.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v2:
- Added Rob's ACK
---
.../devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
index 6d593003c933b..9059f54dc023d 100644
--- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt
@@ -5,7 +5,8 @@ The watchdog supports a pre-timeout interrupt that fires 10ms before the
expiry.
Required properties:
-- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg).
+- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
+ "nuvoton,wpcm450-wdt" for WPCM450 (Hermon).
- reg : Offset and length of the register set for the device.
- interrupts : Contain the timer interrupt with flags for
falling edge.
--
2.30.2
The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt
controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton
SoCs.
The list of registers if based on the AMI vendor kernel and the
Nuvoton W90N745 datasheet.
Although the hardware supports other interrupt modes, the driver only
supports high-level interrupts at the moment, because other modes could
not be tested so far.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
---
v2:
- Rename IRQS macro to AIC_NUM_IRQS
- Fix IRQ range check
- Use linux/printk.h header instead of linux/console.h
- Add AIC_SCR_PRIORITY_MASK constant
- Add missing register descriptions
- Remove superfluous printk about IRQ flow type mismatch
- Use BIT() macro
- Rename _ack function to _eoi for accuracy, and use handle_fasteoi_irq
---
arch/arm/mach-npcm/Kconfig | 1 +
drivers/irqchip/Kconfig | 6 ++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-wpcm450-aic.c | 161 ++++++++++++++++++++++++++++++
4 files changed, 169 insertions(+)
create mode 100644 drivers/irqchip/irq-wpcm450-aic.c
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
index 658c8efb4ca14..a71cf1d189ae5 100644
--- a/arch/arm/mach-npcm/Kconfig
+++ b/arch/arm/mach-npcm/Kconfig
@@ -10,6 +10,7 @@ config ARCH_WPCM450
bool "Support for WPCM450 BMC (Hermon)"
depends on ARCH_MULTI_V5
select CPU_ARM926T
+ select WPCM450_AIC
select NPCM7XX_TIMER
help
General support for WPCM450 BMC (Hermon).
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e74fa206240a1..baf4efec31c67 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -586,4 +586,10 @@ config MST_IRQ
help
Support MStar Interrupt Controller.
+config WPCM450_AIC
+ bool "Nuvoton WPCM450 Advanced Interrupt Controller"
+ depends on ARCH_WPCM450 || COMPILE_TEST
+ help
+ Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c59b95a0532c9..bef57937e7296 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -113,3 +113,4 @@ obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o
obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
+obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o
diff --git a/drivers/irqchip/irq-wpcm450-aic.c b/drivers/irqchip/irq-wpcm450-aic.c
new file mode 100644
index 0000000000000..f3ac392d5bc87
--- /dev/null
+++ b/drivers/irqchip/irq-wpcm450-aic.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright 2021 Jonathan Neuschäfer
+
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/printk.h>
+
+#include <asm/exception.h>
+
+#define AIC_SCR(x) ((x)*4) /* Source control registers */
+#define AIC_GEN 0x84 /* Interrupt group enable control register */
+#define AIC_GRSR 0x88 /* Interrupt group raw status register */
+#define AIC_IRSR 0x100 /* Interrupt raw status register */
+#define AIC_IASR 0x104 /* Interrupt active status register */
+#define AIC_ISR 0x108 /* Interrupt status register */
+#define AIC_IPER 0x10c /* Interrupt priority encoding register */
+#define AIC_ISNR 0x110 /* Interrupt source number register */
+#define AIC_IMR 0x114 /* Interrupt mask register */
+#define AIC_OISR 0x118 /* Output interrupt status register */
+#define AIC_MECR 0x120 /* Mask enable command register */
+#define AIC_MDCR 0x124 /* Mask disable command register */
+#define AIC_SSCR 0x128 /* Source set command register */
+#define AIC_SCCR 0x12c /* Source clear command register */
+#define AIC_EOSCR 0x130 /* End of service command register */
+
+#define AIC_SCR_SRCTYPE_LOW_LEVEL (0 << 6)
+#define AIC_SCR_SRCTYPE_HIGH_LEVEL (1 << 6)
+#define AIC_SCR_SRCTYPE_NEG_EDGE (2 << 6)
+#define AIC_SCR_SRCTYPE_POS_EDGE (3 << 6)
+#define AIC_SCR_PRIORITY(x) (x)
+#define AIC_SCR_PRIORITY_MASK 0x7
+
+#define AIC_NUM_IRQS 32
+
+struct wpcm450_aic {
+ void __iomem *regs;
+ struct irq_domain *domain;
+};
+
+static struct wpcm450_aic *aic;
+
+static void wpcm450_aic_init_hw(void)
+{
+ int i;
+
+ /* Disable (mask) all interrupts */
+ writel(0xffffffff, aic->regs + AIC_MDCR);
+
+ /*
+ * Make sure the interrupt controller is ready to serve new interrupts.
+ * Reading from IPER indicates that the nIRQ signal may be deasserted,
+ * and writing to EOSCR indicates that interrupt handling has finished.
+ */
+ readl(aic->regs + AIC_IPER);
+ writel(0, aic->regs + AIC_EOSCR);
+
+ /* Initialize trigger mode and priority of each interrupt source */
+ for (i = 0; i < AIC_NUM_IRQS; i++)
+ writel(AIC_SCR_SRCTYPE_HIGH_LEVEL | AIC_SCR_PRIORITY(7),
+ aic->regs + AIC_SCR(i));
+}
+
+static void __exception_irq_entry wpcm450_aic_handle_irq(struct pt_regs *regs)
+{
+ int hwirq;
+
+ /* Determine the interrupt source */
+ /* Read IPER to signal that nIRQ can be de-asserted */
+ hwirq = readl(aic->regs + AIC_IPER) / 4;
+
+ handle_domain_irq(aic->domain, hwirq, regs);
+}
+
+static void wpcm450_aic_eoi(struct irq_data *d)
+{
+ /* Signal end-of-service */
+ writel(0, aic->regs + AIC_EOSCR);
+}
+
+static void wpcm450_aic_mask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq);
+
+ /* Disable (mask) the interrupt */
+ writel(mask, aic->regs + AIC_MDCR);
+}
+
+static void wpcm450_aic_unmask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq);
+
+ /* Enable (unmask) the interrupt */
+ writel(mask, aic->regs + AIC_MECR);
+}
+
+static int wpcm450_aic_set_type(struct irq_data *d, unsigned int flow_type)
+{
+ /*
+ * The hardware supports high/low level, as well as rising/falling edge
+ * modes, and the DT binding accommodates for that, but as long as
+ * other modes than high level mode are not used and can't be tested,
+ * they are rejected in this driver.
+ */
+ if ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH)
+ return -EINVAL;
+
+ return 0;
+}
+
+static struct irq_chip wpcm450_aic_chip = {
+ .name = "wpcm450-aic",
+ .irq_eoi = wpcm450_aic_eoi,
+ .irq_mask = wpcm450_aic_mask,
+ .irq_unmask = wpcm450_aic_unmask,
+ .irq_set_type = wpcm450_aic_set_type,
+};
+
+static int wpcm450_aic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq)
+{
+ if (hwirq >= AIC_NUM_IRQS)
+ return -EPERM;
+
+ irq_set_chip_and_handler(irq, &wpcm450_aic_chip, handle_fasteoi_irq);
+ irq_set_chip_data(irq, aic);
+ irq_set_probe(irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops wpcm450_aic_ops = {
+ .map = wpcm450_aic_map,
+ .xlate = irq_domain_xlate_twocell,
+};
+
+static int __init wpcm450_aic_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ if (parent)
+ return -EINVAL;
+
+ aic = kzalloc(sizeof(*aic), GFP_KERNEL);
+ if (!aic)
+ return -ENOMEM;
+
+ aic->regs = of_iomap(node, 0);
+ if (!aic->regs) {
+ pr_err("Failed to map WPCM450 AIC registers\n");
+ return -ENOMEM;
+ }
+
+ wpcm450_aic_init_hw();
+
+ set_handle_irq(wpcm450_aic_handle_irq);
+
+ aic->domain = irq_domain_add_linear(node, AIC_NUM_IRQS, &wpcm450_aic_ops, aic);
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(wpcm450_aic, "nuvoton,wpcm450-aic", wpcm450_aic_of_init);
--
2.30.2
The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt
controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton
SoCs.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v2:
- Added Rob's ACK
---
.../nuvoton,wpcm450-aic.yaml | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
new file mode 100644
index 0000000000000..9ce6804bdb999
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/nuvoton,wpcm450-aic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton WPCM450 Advanced Interrupt Controller bindings
+
+maintainers:
+ - Jonathan Neuschäfer <[email protected]>
+
+properties:
+ '#interrupt-cells':
+ const: 2
+
+ compatible:
+ const: nuvoton,wpcm450-aic
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - '#interrupt-cells'
+ - compatible
+ - reg
+ - interrupt-controller
+
+examples:
+ - |
+ aic: interrupt-controller@b8002000 {
+ compatible = "nuvoton,wpcm450-aic";
+ reg = <0xb8002000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
--
2.30.2
I am adding myself as the maintainer of WPCM450-related code.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
---
v2:
- Instead of expanding the NPCM entry, I'm adding a new one only for
WPCM450.
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index d92f85ca831d3..661770e8e6fc1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2194,6 +2194,15 @@ F: drivers/*/*npcm*
F: drivers/*/*/*npcm*
F: include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
+ARM/NUVOTON WPCM450 ARCHITECTURE
+M: Jonathan Neuschäfer <[email protected]>
+L: [email protected] (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/*/*wpcm*
+F: arch/arm/boot/dts/nuvoton-wpcm450*
+F: arch/arm/mach-npcm/wpcm450.c
+F: drivers/*/*wpcm*
+
ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
L: [email protected] (subscribers-only)
S: Orphan
--
2.30.2
The Supermicro X9SCi-LN4F is a server mainboard featuring the WPCM450
BMC. This patch adds a minimal devicetree for Linux running on the BMC.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
---
v2:
- Group wpcm450 devicetree with npcm7xx devicetrees in the Makefile
---
arch/arm/boot/dts/Makefile | 2 +
.../nuvoton-wpcm450-supermicro-x9sci-ln4f.dts | 40 +++++++++++++++++++
2 files changed, 42 insertions(+)
create mode 100644 arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 8e5d4ab4e75e6..5a9d99d5443e4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -333,6 +333,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \
dtb-$(CONFIG_ARCH_LPC32XX) += \
lpc3250-ea3250.dtb \
lpc3250-phy3250.dtb
+dtb-$(CONFIG_ARCH_WPCM450) += \
+ nuvoton-wpcm450-supermicro-x9sci-ln4f.dtb
dtb-$(CONFIG_ARCH_NPCM7XX) += \
nuvoton-npcm730-gsj.dtb \
nuvoton-npcm730-kudo.dtb \
diff --git a/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts
new file mode 100644
index 0000000000000..83f27fbf4e939
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-wpcm450-supermicro-x9sci-ln4f.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+// Copyright 2021 Jonathan Neuschäfer
+
+/dts-v1/;
+
+/* The last 16 MiB are dedicated to the GPU */
+/memreserve/ 0x07000000 0x01000000;
+
+#include "nuvoton-wpcm450.dtsi"
+
+/ {
+ model = "Supermicro X9SCi-LN4F BMC";
+ compatible = "supermicro,x9sci-ln4f-bmc", "nuvoton,wpcm450";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0 0x08000000>; /* 128 MiB */
+ };
+};
+
+&serial0 {
+ /*
+ * Debug serial port. TX is exposed on the right pad of unpopulated
+ * resistor R1247, RX on the right pad of R1162.
+ */
+ status = "okay";
+};
+
+&serial1 {
+ /* "Serial over LAN" port. Connected to ttyS2 of the host system. */
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
--
2.30.2
Add a compatible string for WPCM450, which has essentially the same
watchdog mechanism as NPCM750.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
---
v2:
- Added patch description
---
drivers/watchdog/npcm_wdt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/watchdog/npcm_wdt.c b/drivers/watchdog/npcm_wdt.c
index 765577f11c8db..28a24caa2627c 100644
--- a/drivers/watchdog/npcm_wdt.c
+++ b/drivers/watchdog/npcm_wdt.c
@@ -229,6 +229,7 @@ static int npcm_wdt_probe(struct platform_device *pdev)
#ifdef CONFIG_OF
static const struct of_device_id npcm_wdt_match[] = {
+ {.compatible = "nuvoton,wpcm450-wdt"},
{.compatible = "nuvoton,npcm750-wdt"},
{},
};
--
2.30.2
Super Micro Computer, Inc. (https://www.supermicro.com/en/), commonly
known as Supermicro, is a manufacturer of server hardware.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
v2:
- Added Rob's ACK
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index f6064d84a424d..ec6d6ccfbbb3b 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1085,6 +1085,8 @@ patternProperties:
description: Shenzhen Sunchip Technology Co., Ltd
"^SUNW,.*":
description: Sun Microsystems, Inc
+ "^supermicro,.*":
+ description: Super Micro Computer, Inc.
"^silvaco,.*":
description: Silvaco, Inc.
"^swir,.*":
--
2.30.2
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally
marketed as Winbond WPCM450.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
---
v2:
- Reorder lines in Makefile by model number (WPCM450 < NPCM7xx)
---
arch/arm/mach-npcm/Kconfig | 12 +++++++++++-
arch/arm/mach-npcm/Makefile | 1 +
arch/arm/mach-npcm/wpcm450.c | 13 +++++++++++++
3 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-npcm/wpcm450.c
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
index 7f7002dc2b21f..658c8efb4ca14 100644
--- a/arch/arm/mach-npcm/Kconfig
+++ b/arch/arm/mach-npcm/Kconfig
@@ -1,11 +1,21 @@
# SPDX-License-Identifier: GPL-2.0-only
menuconfig ARCH_NPCM
bool "Nuvoton NPCM Architecture"
- depends on ARCH_MULTI_V7
+ depends on ARCH_MULTI_V5 || ARCH_MULTI_V7
select PINCTRL
if ARCH_NPCM
+config ARCH_WPCM450
+ bool "Support for WPCM450 BMC (Hermon)"
+ depends on ARCH_MULTI_V5
+ select CPU_ARM926T
+ select NPCM7XX_TIMER
+ help
+ General support for WPCM450 BMC (Hermon).
+
+ Winbond/Nuvoton WPCM450 BMC based on the ARM926EJ-S.
+
config ARCH_NPCM7XX
bool "Support for NPCM7xx BMC (Poleg)"
depends on ARCH_MULTI_V7
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
index 1bc3a70bfab8b..8d61fcd42fb19 100644
--- a/arch/arm/mach-npcm/Makefile
+++ b/arch/arm/mach-npcm/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
AFLAGS_headsmp.o += -march=armv7-a
+obj-$(CONFIG_ARCH_WPCM450) += wpcm450.o
obj-$(CONFIG_ARCH_NPCM7XX) += npcm7xx.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
diff --git a/arch/arm/mach-npcm/wpcm450.c b/arch/arm/mach-npcm/wpcm450.c
new file mode 100644
index 0000000000000..f17b3dab45af3
--- /dev/null
+++ b/arch/arm/mach-npcm/wpcm450.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright 2021 Jonathan Neuschäfer
+
+#include <asm/mach/arch.h>
+
+static const char *const wpcm450_dt_match[] = {
+ "nuvoton,wpcm450",
+ NULL
+};
+
+DT_MACHINE_START(WPCM450_DT, "WPCM450 chip")
+ .dt_compat = wpcm450_dt_match,
+MACHINE_END
--
2.30.2
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally
marketed as Winbond WPCM450.
This patch adds a devicetree with basic functionality.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
---
v2:
- no changes
---
arch/arm/boot/dts/nuvoton-wpcm450.dtsi | 76 ++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 arch/arm/boot/dts/nuvoton-wpcm450.dtsi
diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
new file mode 100644
index 0000000000000..d7cbeb1874840
--- /dev/null
+++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+// Copyright 2021 Jonathan Neuschäfer
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ compatible = "nuvoton,wpcm450";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,arm926ej-s";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ clk24m: clock-24mhz {
+ /* 24 MHz dummy clock */
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&aic>;
+ ranges;
+
+ serial0: serial@b8000000 {
+ compatible = "nuvoton,wpcm450-uart";
+ reg = <0xb8000000 0x20>;
+ reg-shift = <2>;
+ interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk24m>;
+ status = "disabled";
+ };
+
+ serial1: serial@b8000100 {
+ compatible = "nuvoton,wpcm450-uart";
+ reg = <0xb8000100 0x20>;
+ reg-shift = <2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk24m>;
+ status = "disabled";
+ };
+
+ timer0: timer@b8001000 {
+ compatible = "nuvoton,wpcm450-timer";
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb8001000 0x1c>;
+ clocks = <&clk24m>;
+ };
+
+ watchdog0: watchdog@b800101c {
+ compatible = "nuvoton,wpcm450-wdt";
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xb800101c 0x4>;
+ clocks = <&clk24m>;
+ status = "disabled";
+ };
+
+ aic: interrupt-controller@b8002000 {
+ compatible = "nuvoton,wpcm450-aic";
+ reg = <0xb8002000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
--
2.30.2
On Tue, Apr 6, 2021 at 2:09 PM Jonathan Neuschäfer
<[email protected]> wrote:
>
> This series adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older
> SoC but still commonly found on eBay, mostly in Supermicro X9 server boards.
>
> Third-party documentation is available at: https://github.com/neuschaefer/wpcm450/wiki
>
> Patches 1-4 add devicetree bindings for the WPCM450 SoC and its various parts.
> Patches 5-7 add arch and driver support. Patches 8 and 9 add a devicetree for
> the SoC and a board based on it. Patch 10 finally updates the MAINTAINERS file.
>
> Patch 2 requires "dt-bindings: arm: Convert nuvoton,npcm750 binding to YAML"
> (https://lore.kernel.org/lkml/[email protected]/)
Hi Jonathan,
It appears these patches are doing roughly the right thing, and we may still
be able to get them into v5.13, but I'm not sure what your plan for maintaining
them is. The two options are that you either send your patches to be picked up
by Joel, or you send everything directly to [email protected] once it's fully
reviewed.
I only noticed your series when patch 9/10 made it into the [email protected]
patchwork because of the Cc, but none of the other ones did.
If you end up with the second option, we can go through what this involves
off-list.
Regarding the Cc:[email protected], please add that only for patches that
are already reviewed and ready to be picked up, ideally with a cover letter
that describes what the plan is for merging. If you need me to review the
platform code, use my [email protected] or [email protected] addresses.
Arnd
On Tue, Apr 06, 2021 at 05:15:01PM +0200, Arnd Bergmann wrote:
> On Tue, Apr 6, 2021 at 2:09 PM Jonathan Neuschäfer
> <[email protected]> wrote:
> >
> > This series adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older
> > SoC but still commonly found on eBay, mostly in Supermicro X9 server boards.
> >
> > Third-party documentation is available at: https://github.com/neuschaefer/wpcm450/wiki
> >
> > Patches 1-4 add devicetree bindings for the WPCM450 SoC and its various parts.
> > Patches 5-7 add arch and driver support. Patches 8 and 9 add a devicetree for
> > the SoC and a board based on it. Patch 10 finally updates the MAINTAINERS file.
> >
> > Patch 2 requires "dt-bindings: arm: Convert nuvoton,npcm750 binding to YAML"
> > (https://lore.kernel.org/lkml/[email protected]/)
>
> Hi Jonathan,
>
> It appears these patches are doing roughly the right thing, and we may still
> be able to get them into v5.13, but I'm not sure what your plan for maintaining
> them is. The two options are that you either send your patches to be picked up
> by Joel, or you send everything directly to [email protected] once it's fully
> reviewed.
The route via Joel sounds alright with me. I've Cc'd him on this version
of the series.
> I only noticed your series when patch 9/10 made it into the [email protected]
> patchwork because of the Cc, but none of the other ones did.
>
> If you end up with the second option, we can go through what this involves
> off-list.
>
> Regarding the Cc:[email protected], please add that only for patches that
> are already reviewed and ready to be picked up, ideally with a cover letter
> that describes what the plan is for merging. If you need me to review the
> platform code, use my [email protected] or [email protected] addresses.
Ah sorry, [email protected] slipped in automatically because of get_maintainers.pl.
The platform code[1] is rather simple, essentially just hooking up the
nuvoton,wpcm450 compatible string.
Thanks,
Jonathan
[1]: https://lore.kernel.org/lkml/[email protected]/
On Tue, 06 Apr 2021 13:09:17 +0100,
Jonathan Neuschäfer <[email protected]> wrote:
>
> The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt
> controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton
> SoCs.
>
> The list of registers if based on the AMI vendor kernel and the
> Nuvoton W90N745 datasheet.
>
> Although the hardware supports other interrupt modes, the driver only
> supports high-level interrupts at the moment, because other modes could
> not be tested so far.
>
> Signed-off-by: Jonathan Neuschäfer <[email protected]>
> ---
>
> v2:
> - Rename IRQS macro to AIC_NUM_IRQS
> - Fix IRQ range check
> - Use linux/printk.h header instead of linux/console.h
> - Add AIC_SCR_PRIORITY_MASK constant
> - Add missing register descriptions
> - Remove superfluous printk about IRQ flow type mismatch
> - Use BIT() macro
> - Rename _ack function to _eoi for accuracy, and use handle_fasteoi_irq
> ---
> arch/arm/mach-npcm/Kconfig | 1 +
> drivers/irqchip/Kconfig | 6 ++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-wpcm450-aic.c | 161 ++++++++++++++++++++++++++++++
> 4 files changed, 169 insertions(+)
> create mode 100644 drivers/irqchip/irq-wpcm450-aic.c
>
> diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
> index 658c8efb4ca14..a71cf1d189ae5 100644
> --- a/arch/arm/mach-npcm/Kconfig
> +++ b/arch/arm/mach-npcm/Kconfig
> @@ -10,6 +10,7 @@ config ARCH_WPCM450
> bool "Support for WPCM450 BMC (Hermon)"
> depends on ARCH_MULTI_V5
> select CPU_ARM926T
> + select WPCM450_AIC
> select NPCM7XX_TIMER
> help
> General support for WPCM450 BMC (Hermon).
I can't take this patch with this particular hunk, as I don't have
this file in my tree. I can either drop this line, or delay the
merging of this patch to a later point in time.
The driver otherwise looks ready.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
On Tue, 6 Apr 2021 14:09:11 +0200, Jonathan Neuschäfer wrote:
> This series adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older
> SoC but still commonly found on eBay, mostly in Supermicro X9 server boards.
>
> Third-party documentation is available at: https://github.com/neuschaefer/wpcm450/wiki
>
> Patches 1-4 add devicetree bindings for the WPCM450 SoC and its various parts.
> Patches 5-7 add arch and driver support. Patches 8 and 9 add a devicetree for
> the SoC and a board based on it. Patch 10 finally updates the MAINTAINERS file.
>
> [...]
Applied to irq/irqchip-next, thanks!
[03/10] dt-bindings: interrupt-controller: Add nuvoton, wpcm450-aic
commit: 7c18715546203a09f859dac2fe3ea8aceec5f235
[06/10] irqchip: Add driver for WPCM450 interrupt controller
commit: fead4dd496631707549f414b4059afb86ea8fb80
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: 7c18715546203a09f859dac2fe3ea8aceec5f235
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/7c18715546203a09f859dac2fe3ea8aceec5f235
Author: Jonathan Neuschäfer <[email protected]>
AuthorDate: Tue, 06 Apr 2021 14:09:14 +02:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Wed, 07 Apr 2021 13:26:00 +01:00
dt-bindings: interrupt-controller: Add nuvoton, wpcm450-aic
The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt
controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton
SoCs.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml | 39 +++++++++++++++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml b/Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
new file mode 100644
index 0000000..9ce6804
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/nuvoton,wpcm450-aic.yaml
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/nuvoton,wpcm450-aic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton WPCM450 Advanced Interrupt Controller bindings
+
+maintainers:
+ - Jonathan Neuschäfer <[email protected]>
+
+properties:
+ '#interrupt-cells':
+ const: 2
+
+ compatible:
+ const: nuvoton,wpcm450-aic
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - '#interrupt-cells'
+ - compatible
+ - reg
+ - interrupt-controller
+
+examples:
+ - |
+ aic: interrupt-controller@b8002000 {
+ compatible = "nuvoton,wpcm450-aic";
+ reg = <0xb8002000 0x1000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
On Wed, Apr 07, 2021 at 12:11:21PM +0100, Marc Zyngier wrote:
> On Tue, 06 Apr 2021 13:09:17 +0100,
> Jonathan Neuschäfer <[email protected]> wrote:
...
> > diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
> > index 658c8efb4ca14..a71cf1d189ae5 100644
> > --- a/arch/arm/mach-npcm/Kconfig
> > +++ b/arch/arm/mach-npcm/Kconfig
> > @@ -10,6 +10,7 @@ config ARCH_WPCM450
> > bool "Support for WPCM450 BMC (Hermon)"
> > depends on ARCH_MULTI_V5
> > select CPU_ARM926T
> > + select WPCM450_AIC
> > select NPCM7XX_TIMER
> > help
> > General support for WPCM450 BMC (Hermon).
>
> I can't take this patch with this particular hunk, as I don't have
> this file in my tree. I can either drop this line, or delay the
> merging of this patch to a later point in time.
Hmm, indeed. Please apply the patch without this hunk. I'll reintroduce
it in another patch.
>
> The driver otherwise looks ready.
Good.
Thanks,
Jonathan
The following commit has been merged into the irq/irqchip-next branch of irqchip:
Commit-ID: fead4dd496631707549f414b4059afb86ea8fb80
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/fead4dd496631707549f414b4059afb86ea8fb80
Author: Jonathan Neuschäfer <[email protected]>
AuthorDate: Tue, 06 Apr 2021 14:09:17 +02:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Wed, 07 Apr 2021 13:26:00 +01:00
irqchip: Add driver for WPCM450 interrupt controller
The WPCM450 AIC ("Advanced Interrupt Controller") is the interrupt
controller found in the Nuvoton WPCM450 SoC and other Winbond/Nuvoton
SoCs.
The list of registers if based on the AMI vendor kernel and the
Nuvoton W90N745 datasheet.
Although the hardware supports other interrupt modes, the driver only
supports high-level interrupts at the moment, because other modes could
not be tested so far.
Signed-off-by: Jonathan Neuschäfer <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/Kconfig | 6 +-
drivers/irqchip/Makefile | 1 +-
drivers/irqchip/irq-wpcm450-aic.c | 161 +++++++++++++++++++++++++++++-
3 files changed, 168 insertions(+)
create mode 100644 drivers/irqchip/irq-wpcm450-aic.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 15536e3..38ad9dc 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -577,4 +577,10 @@ config MST_IRQ
help
Support MStar Interrupt Controller.
+config WPCM450_AIC
+ bool "Nuvoton WPCM450 Advanced Interrupt Controller"
+ depends on ARCH_WPCM450 || COMPILE_TEST
+ help
+ Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
+
endmenu
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index c59b95a..bef5793 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -113,3 +113,4 @@ obj-$(CONFIG_LOONGSON_PCH_MSI) += irq-loongson-pch-msi.o
obj-$(CONFIG_MST_IRQ) += irq-mst-intc.o
obj-$(CONFIG_SL28CPLD_INTC) += irq-sl28cpld.o
obj-$(CONFIG_MACH_REALTEK_RTL) += irq-realtek-rtl.o
+obj-$(CONFIG_WPCM450_AIC) += irq-wpcm450-aic.o
diff --git a/drivers/irqchip/irq-wpcm450-aic.c b/drivers/irqchip/irq-wpcm450-aic.c
new file mode 100644
index 0000000..f3ac392
--- /dev/null
+++ b/drivers/irqchip/irq-wpcm450-aic.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// Copyright 2021 Jonathan Neuschäfer
+
+#include <linux/irqchip.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/printk.h>
+
+#include <asm/exception.h>
+
+#define AIC_SCR(x) ((x)*4) /* Source control registers */
+#define AIC_GEN 0x84 /* Interrupt group enable control register */
+#define AIC_GRSR 0x88 /* Interrupt group raw status register */
+#define AIC_IRSR 0x100 /* Interrupt raw status register */
+#define AIC_IASR 0x104 /* Interrupt active status register */
+#define AIC_ISR 0x108 /* Interrupt status register */
+#define AIC_IPER 0x10c /* Interrupt priority encoding register */
+#define AIC_ISNR 0x110 /* Interrupt source number register */
+#define AIC_IMR 0x114 /* Interrupt mask register */
+#define AIC_OISR 0x118 /* Output interrupt status register */
+#define AIC_MECR 0x120 /* Mask enable command register */
+#define AIC_MDCR 0x124 /* Mask disable command register */
+#define AIC_SSCR 0x128 /* Source set command register */
+#define AIC_SCCR 0x12c /* Source clear command register */
+#define AIC_EOSCR 0x130 /* End of service command register */
+
+#define AIC_SCR_SRCTYPE_LOW_LEVEL (0 << 6)
+#define AIC_SCR_SRCTYPE_HIGH_LEVEL (1 << 6)
+#define AIC_SCR_SRCTYPE_NEG_EDGE (2 << 6)
+#define AIC_SCR_SRCTYPE_POS_EDGE (3 << 6)
+#define AIC_SCR_PRIORITY(x) (x)
+#define AIC_SCR_PRIORITY_MASK 0x7
+
+#define AIC_NUM_IRQS 32
+
+struct wpcm450_aic {
+ void __iomem *regs;
+ struct irq_domain *domain;
+};
+
+static struct wpcm450_aic *aic;
+
+static void wpcm450_aic_init_hw(void)
+{
+ int i;
+
+ /* Disable (mask) all interrupts */
+ writel(0xffffffff, aic->regs + AIC_MDCR);
+
+ /*
+ * Make sure the interrupt controller is ready to serve new interrupts.
+ * Reading from IPER indicates that the nIRQ signal may be deasserted,
+ * and writing to EOSCR indicates that interrupt handling has finished.
+ */
+ readl(aic->regs + AIC_IPER);
+ writel(0, aic->regs + AIC_EOSCR);
+
+ /* Initialize trigger mode and priority of each interrupt source */
+ for (i = 0; i < AIC_NUM_IRQS; i++)
+ writel(AIC_SCR_SRCTYPE_HIGH_LEVEL | AIC_SCR_PRIORITY(7),
+ aic->regs + AIC_SCR(i));
+}
+
+static void __exception_irq_entry wpcm450_aic_handle_irq(struct pt_regs *regs)
+{
+ int hwirq;
+
+ /* Determine the interrupt source */
+ /* Read IPER to signal that nIRQ can be de-asserted */
+ hwirq = readl(aic->regs + AIC_IPER) / 4;
+
+ handle_domain_irq(aic->domain, hwirq, regs);
+}
+
+static void wpcm450_aic_eoi(struct irq_data *d)
+{
+ /* Signal end-of-service */
+ writel(0, aic->regs + AIC_EOSCR);
+}
+
+static void wpcm450_aic_mask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq);
+
+ /* Disable (mask) the interrupt */
+ writel(mask, aic->regs + AIC_MDCR);
+}
+
+static void wpcm450_aic_unmask(struct irq_data *d)
+{
+ unsigned int mask = BIT(d->hwirq);
+
+ /* Enable (unmask) the interrupt */
+ writel(mask, aic->regs + AIC_MECR);
+}
+
+static int wpcm450_aic_set_type(struct irq_data *d, unsigned int flow_type)
+{
+ /*
+ * The hardware supports high/low level, as well as rising/falling edge
+ * modes, and the DT binding accommodates for that, but as long as
+ * other modes than high level mode are not used and can't be tested,
+ * they are rejected in this driver.
+ */
+ if ((flow_type & IRQ_TYPE_SENSE_MASK) != IRQ_TYPE_LEVEL_HIGH)
+ return -EINVAL;
+
+ return 0;
+}
+
+static struct irq_chip wpcm450_aic_chip = {
+ .name = "wpcm450-aic",
+ .irq_eoi = wpcm450_aic_eoi,
+ .irq_mask = wpcm450_aic_mask,
+ .irq_unmask = wpcm450_aic_unmask,
+ .irq_set_type = wpcm450_aic_set_type,
+};
+
+static int wpcm450_aic_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hwirq)
+{
+ if (hwirq >= AIC_NUM_IRQS)
+ return -EPERM;
+
+ irq_set_chip_and_handler(irq, &wpcm450_aic_chip, handle_fasteoi_irq);
+ irq_set_chip_data(irq, aic);
+ irq_set_probe(irq);
+
+ return 0;
+}
+
+static const struct irq_domain_ops wpcm450_aic_ops = {
+ .map = wpcm450_aic_map,
+ .xlate = irq_domain_xlate_twocell,
+};
+
+static int __init wpcm450_aic_of_init(struct device_node *node,
+ struct device_node *parent)
+{
+ if (parent)
+ return -EINVAL;
+
+ aic = kzalloc(sizeof(*aic), GFP_KERNEL);
+ if (!aic)
+ return -ENOMEM;
+
+ aic->regs = of_iomap(node, 0);
+ if (!aic->regs) {
+ pr_err("Failed to map WPCM450 AIC registers\n");
+ return -ENOMEM;
+ }
+
+ wpcm450_aic_init_hw();
+
+ set_handle_irq(wpcm450_aic_handle_irq);
+
+ aic->domain = irq_domain_add_linear(node, AIC_NUM_IRQS, &wpcm450_aic_ops, aic);
+
+ return 0;
+}
+
+IRQCHIP_DECLARE(wpcm450_aic, "nuvoton,wpcm450-aic", wpcm450_aic_of_init);
Hi "irqchip-bot,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tip/irq/core]
[also build test ERROR on linux/master linus/master v5.12-rc6 next-20210407]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/irqchip-bot-for-Jonathan-Neusch-fer/irqchip-Add-driver-for-WPCM450-interrupt-controller/20210407-203932
base: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git 883ccef355b910398b99dfaf96d40557479a7e9b
config: riscv-allyesconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/8d413120619cd8ca14f38e623fad9e0acc44397c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review irqchip-bot-for-Jonathan-Neusch-fer/irqchip-Add-driver-for-WPCM450-interrupt-controller/20210407-203932
git checkout 8d413120619cd8ca14f38e623fad9e0acc44397c
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
>> drivers/irqchip/irq-wpcm450-aic.c:9:10: fatal error: asm/exception.h: No such file or directory
9 | #include <asm/exception.h>
| ^~~~~~~~~~~~~~~~~
compilation terminated.
vim +9 drivers/irqchip/irq-wpcm450-aic.c
8
> 9 #include <asm/exception.h>
10
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
On Tue, 6 Apr 2021 at 21:59, Jonathan Neuschäfer <[email protected]> wrote:
>
> On Tue, Apr 06, 2021 at 05:15:01PM +0200, Arnd Bergmann wrote:
> > On Tue, Apr 6, 2021 at 2:09 PM Jonathan Neuschäfer
> > <[email protected]> wrote:
> > >
> > > This series adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older
> > > SoC but still commonly found on eBay, mostly in Supermicro X9 server boards.
> > >
> > > Third-party documentation is available at: https://github.com/neuschaefer/wpcm450/wiki
> > >
> > > Patches 1-4 add devicetree bindings for the WPCM450 SoC and its various parts.
> > > Patches 5-7 add arch and driver support. Patches 8 and 9 add a devicetree for
> > > the SoC and a board based on it. Patch 10 finally updates the MAINTAINERS file.
> > >
> > > Patch 2 requires "dt-bindings: arm: Convert nuvoton,npcm750 binding to YAML"
> > > (https://lore.kernel.org/lkml/[email protected]/)
> >
> > Hi Jonathan,
> >
> > It appears these patches are doing roughly the right thing, and we may still
> > be able to get them into v5.13, but I'm not sure what your plan for maintaining
> > them is. The two options are that you either send your patches to be picked up
> > by Joel, or you send everything directly to [email protected] once it's fully
> > reviewed.
>
> The route via Joel sounds alright with me. I've Cc'd him on this version
> of the series.
I've had a look at the series and it looks good to me:
Reviewed-by: Joel Stanley <[email protected]>
Nice work Jonathan.
I'll put this in it's own branch along with the bindings change it
depends on and send a pull request to Arnd for v5.13.
Cheers,
Joel
On Fri, Apr 09, 2021 at 04:37:34AM +0000, Joel Stanley wrote:
> On Tue, 6 Apr 2021 at 21:59, Jonathan Neuschäfer <[email protected]> wrote:
> >
> > On Tue, Apr 06, 2021 at 05:15:01PM +0200, Arnd Bergmann wrote:
> > > On Tue, Apr 6, 2021 at 2:09 PM Jonathan Neuschäfer
> > > <[email protected]> wrote:
> > > >
> > > > This series adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older
> > > > SoC but still commonly found on eBay, mostly in Supermicro X9 server boards.
> > > >
> > > > Third-party documentation is available at: https://github.com/neuschaefer/wpcm450/wiki
> > > >
> > > > Patches 1-4 add devicetree bindings for the WPCM450 SoC and its various parts.
> > > > Patches 5-7 add arch and driver support. Patches 8 and 9 add a devicetree for
> > > > the SoC and a board based on it. Patch 10 finally updates the MAINTAINERS file.
> > > >
> > > > Patch 2 requires "dt-bindings: arm: Convert nuvoton,npcm750 binding to YAML"
> > > > (https://lore.kernel.org/lkml/[email protected]/)
> > >
> > > Hi Jonathan,
> > >
> > > It appears these patches are doing roughly the right thing, and we may still
> > > be able to get them into v5.13, but I'm not sure what your plan for maintaining
> > > them is. The two options are that you either send your patches to be picked up
> > > by Joel, or you send everything directly to [email protected] once it's fully
> > > reviewed.
> >
> > The route via Joel sounds alright with me. I've Cc'd him on this version
> > of the series.
>
> I've had a look at the series and it looks good to me:
>
> Reviewed-by: Joel Stanley <[email protected]>
>
> Nice work Jonathan.
>
> I'll put this in it's own branch along with the bindings change it
> depends on and send a pull request to Arnd for v5.13.
Thanks a bunch!
A few patches are going through other branches (IRQ bindings+driver;
watchdog bindings+driver probably, I guess). That leaves the following
patches to go into your branch, AFAIUI:
[PATCH v2 01/10] dt-bindings: vendor-prefixes: Add Supermicro
[PATCH v2 02/10] dt-bindings: arm: npcm: Add nuvoton,wpcm450 compatible string
[PATCH v2 05/10] ARM: npcm: Introduce Nuvoton WPCM450 SoC
[PATCH v2 08/10] ARM: dts: Add devicetree for Nuvoton WPCM450 BMC chip
[PATCH v2 09/10] ARM: dts: Add devicetree for Supermicro X9SCi-LN4F based on WPCM450
[PATCH v2 10/10] MAINTAINERS: Add entry for Nuvoton WPCM450
Jonathan
On Fri, Apr 9, 2021 at 9:58 AM Jonathan Neuschäfer
<[email protected]> wrote:
> On Fri, Apr 09, 2021 at 04:37:34AM +0000, Joel Stanley wrote:
> > On Tue, 6 Apr 2021 at 21:59, Jonathan Neuschäfer <[email protected]> wrote:
> > I've had a look at the series and it looks good to me:
> >
> > Reviewed-by: Joel Stanley <[email protected]>
> >
> > Nice work Jonathan.
> >
> > I'll put this in it's own branch along with the bindings change it
> > depends on and send a pull request to Arnd for v5.13.
>
> Thanks a bunch!
>
> A few patches are going through other branches (IRQ bindings+driver;
> watchdog bindings+driver probably, I guess). That leaves the following
> patches to go into your branch, AFAIUI:
>
> [PATCH v2 01/10] dt-bindings: vendor-prefixes: Add Supermicro
> [PATCH v2 02/10] dt-bindings: arm: npcm: Add nuvoton,wpcm450 compatible string
> [PATCH v2 05/10] ARM: npcm: Introduce Nuvoton WPCM450 SoC
> [PATCH v2 08/10] ARM: dts: Add devicetree for Nuvoton WPCM450 BMC chip
> [PATCH v2 09/10] ARM: dts: Add devicetree for Supermicro X9SCi-LN4F based on WPCM450
> [PATCH v2 10/10] MAINTAINERS: Add entry for Nuvoton WPCM450
Actually for an initial merge, we sometimes just put all the patches into one
branch in the soc tree to avoid conflicts. Unfortunately we already have a
(trivial) conflict now anyway since I merged the irqchip driver for the Apple
M1 SoC through the soc tree but the wpcm irqchip through the irqchip tree.
You did nothing wrong here, this would have just been a way to make the
initial merge a bit easier, and have a tree that is more easily bisectible
when one branch in the merge window contains all the code that is
needed for booting.
Arnd