Hello,
This series adds devicetree node for MAIN CPSW2G instance of CPSW
Ethernet Switch on TI's J721S2 SoC. Also, a devicetree overlay is added
in order to enable MAIN CPSW2G in RGMII-RXID mode using the GESI
Expansion Board connected to the J7 Common-Processor-Board.
Regards,
Siddharth.
---
NOTE: This series is based on linux-next tagged next-20230725.
v2:
https://lore.kernel.org/r/[email protected]/
Changes since v2:
- Collect Reviewed-by tag from Ravi Gunasekaran <[email protected]>.
- Rename main_cpsw_mdio_pins_default and rgmii1_pins_default to:
main_cpsw_mdio_default_pins and rgmii1_default_pins respectively.
- Rename main-cpsw-mdio-pins-default and rgmii1-pins-default to:
main-cpsw-mdio-default-pins and rgmii1-default-pins respectively.
- The above changes are performed to follow the updated json-schema
patch at:
https://lore.kernel.org/all/[email protected]/
- Rebase series on next-20230725.
v1:
https://lore.kernel.org/r/[email protected]/
Changes since v1:
- Rebase series on next-20230710.
RFC:
https://lore.kernel.org/r/[email protected]/
Changes since RFC:
- Add GESI board product link in the device-tree overlay file.
Kishon Vijay Abraham I (2):
arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node
arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
arch/arm64/boot/dts/ti/Makefile | 2 +
.../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 +++++++++++++++
3 files changed, 156 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
--
2.34.1
From: Kishon Vijay Abraham I <[email protected]>
The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
to enable this.
Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
directly from U-Boot.
Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Signed-off-by: Siddharth Vadapalli <[email protected]>
Reviewed-by: Ravi Gunasekaran <[email protected]>
---
arch/arm64/boot/dts/ti/Makefile | 2 +
.../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
2 files changed, 87 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 6dd7b6f1d6ab..019a8be19b93 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
# Boards with J721s2 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
# Boards with J784s4 SoC
dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
@@ -58,3 +59,4 @@ dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb
# Enable support for device-tree overlays
DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@
+DTC_FLAGS_k3-j721s2-common-proc-board += -@
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
new file mode 100644
index 000000000000..b78feea31b54
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for MAIN CPSW2G using GESI Expansion Board with J7 common processor board.
+ *
+ * GESI Board Product Link: https://www.ti.com/tool/J7EXPCXEVM
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+#include "k3-pinctrl.h"
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c200000/ethernet-ports/port@1";
+ };
+};
+
+&main_pmx0 {
+ main_cpsw_mdio_default_pins: main-cpsw-mdio-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0c0, PIN_OUTPUT, 6) /* (T28) MCASP1_AXR0.MDIO0_MDC */
+ J721S2_IOPAD(0x0bc, PIN_INPUT, 6) /* (V28) MCASP1_AFSX.MDIO0_MDIO */
+ >;
+ };
+
+ rgmii1_default_pins: rgmii1-default-pins {
+ pinctrl-single,pins = <
+ J721S2_IOPAD(0x0b8, PIN_INPUT, 6) /* (AA24) MCASP1_ACLKX.RGMII1_RD0 */
+ J721S2_IOPAD(0x0a0, PIN_INPUT, 6) /* (AB25) MCASP0_AXR12.RGMII1_RD1 */
+ J721S2_IOPAD(0x0a4, PIN_INPUT, 6) /* (T23) MCASP0_AXR13.RGMII1_RD2 */
+ J721S2_IOPAD(0x0a8, PIN_INPUT, 6) /* (U24) MCASP0_AXR14.RGMII1_RD3 */
+ J721S2_IOPAD(0x0b0, PIN_INPUT, 6) /* (AD26) MCASP1_AXR3.RGMII1_RXC */
+ J721S2_IOPAD(0x0ac, PIN_INPUT, 6) /* (AC25) MCASP0_AXR15.RGMII1_RX_CTL */
+ J721S2_IOPAD(0x08c, PIN_OUTPUT, 6) /* (T25) MCASP0_AXR7.RGMII1_TD0 */
+ J721S2_IOPAD(0x090, PIN_OUTPUT, 6) /* (W24) MCASP0_AXR8.RGMII1_TD1 */
+ J721S2_IOPAD(0x094, PIN_OUTPUT, 6) /* (AA25) MCASP0_AXR9.RGMII1_TD2 */
+ J721S2_IOPAD(0x098, PIN_OUTPUT, 6) /* (V25) MCASP0_AXR10.RGMII1_TD3 */
+ J721S2_IOPAD(0x0b4, PIN_OUTPUT, 6) /* (U25) MCASP1_AXR4.RGMII1_TXC */
+ J721S2_IOPAD(0x09c, PIN_OUTPUT, 6) /* (T24) MCASP0_AXR11.RGMII1_TX_CTL */
+ >;
+ };
+};
+
+&exp1 {
+ p15 {
+ /* P15 - EXP_MUX2 */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "EXP_MUX2";
+ };
+};
+
+&main_cpsw {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii1_default_pins>;
+};
+
+&main_cpsw_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw_mdio_default_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&main_cpsw_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&main_cpsw_phy0>;
+};
--
2.34.1
Hi Siddharth Vadapalli,
On Wed, 26 Jul 2023 12:24:05 +0530, Siddharth Vadapalli wrote:
> This series adds devicetree node for MAIN CPSW2G instance of CPSW
> Ethernet Switch on TI's J721S2 SoC. Also, a devicetree overlay is added
> in order to enable MAIN CPSW2G in RGMII-RXID mode using the GESI
> Expansion Board connected to the J7 Common-Processor-Board.
>
> Regards,
> Siddharth.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G devicetree node
commit: d6ffe1b4b8c1cdc0ae36b6bc65b11d336aecbb72
[2/2] arm64: dts: ti: k3-j721s2: Add overlay to enable main CPSW2G with GESI
commit: cac04e27f093c3cafdc10c03b6f50e1578ef8cbc
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
On Wed, Jul 26, 2023 at 1:54 AM Siddharth Vadapalli <[email protected]> wrote:
>
> From: Kishon Vijay Abraham I <[email protected]>
>
> The MAIN CPSW2G instance of CPSW on J721S2 SoC can be enabled with the GESI
> Expansion Board connected to the J7 Common-Proc-Board. Use the overlay
> to enable this.
>
> Add alias for the MAIN CPSW2G port to enable kernel to fetch MAC address
> directly from U-Boot.
>
> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
> Signed-off-by: Siddharth Vadapalli <[email protected]>
> Reviewed-by: Ravi Gunasekaran <[email protected]>
> ---
> arch/arm64/boot/dts/ti/Makefile | 2 +
> .../dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 85 +++++++++++++++++++
> 2 files changed, 87 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index 6dd7b6f1d6ab..019a8be19b93 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -51,6 +51,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
> # Boards with J721s2 SoC
> dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb
> dtb-$(CONFIG_ARCH_K3) += k3-j721s2-common-proc-board.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-gesi-exp-board.dtbo
Overlays need to be applied to something. That's done like this:
foo-dtbs := base.dtb k3-am62x-sk-hdmi-audio.dtbo
dtb-y += foo.dtb
Please send a fix for this.
Rob