Add a compatible for the UART on the ARTPEC-8 SoC.
Signed-off-by: Vincent Whitchurch <[email protected]>
---
Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
index 6aceba4a5f79..6f11f2c92f64 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
@@ -20,6 +20,7 @@ properties:
items:
- enum:
- apple,s5l-uart
+ - axis,artpec8-uart
- samsung,s3c2410-uart
- samsung,s3c2412-uart
- samsung,s3c2440-uart
--
2.34.1
On Mon, Mar 7, 2022 at 2:51 AM Vincent Whitchurch
<[email protected]> wrote:
>
> Add a compatible for the UART on the ARTPEC-8 SoC.
Yes, the diff says that already. Perhaps some explanation why you are
adding another vendor SoC to Samsung UART and how the h/w is
different. I can only guess based on having just gone thru this with
Apple.
>
> Signed-off-by: Vincent Whitchurch <[email protected]>
> ---
> Documentation/devicetree/bindings/serial/samsung_uart.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> index 6aceba4a5f79..6f11f2c92f64 100644
> --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> @@ -20,6 +20,7 @@ properties:
> items:
> - enum:
> - apple,s5l-uart
> + - axis,artpec8-uart
> - samsung,s3c2410-uart
> - samsung,s3c2412-uart
> - samsung,s3c2440-uart
> --
> 2.34.1
>
On Tue, Mar 08, 2022 at 04:41:45PM +0100, Rob Herring wrote:
> On Mon, Mar 7, 2022 at 2:51 AM Vincent Whitchurch
> <[email protected]> wrote:
> >
> > Add a compatible for the UART on the ARTPEC-8 SoC.
>
> Yes, the diff says that already. Perhaps some explanation why you are
> adding another vendor SoC to Samsung UART and how the h/w is
> different. I can only guess based on having just gone thru this with
> Apple.
The IP has been customized for the ARTPEC-8 SoC but is closely related
to the variants used on the Exynos chips. I can add this information to
the commit message.
The choice of the vendor prefix is similar to the solution chosen in
this patch:
https://lore.kernel.org/lkml/[email protected]/