v2 -- Dropped commit concerning CRS.
-- Chanded new prop 'brcm,aspm-en-l0s' to 'aspm-no-l0s'.
-- Capitalize first letter in commit subject line; spelling.
v1 -- original
Jim Quinlan (4):
PCI: brcmstb: Don't clk_put() a managed clock
PCI: brcmstb: Fix window register offset from 4 to 8
dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s'
PCI: brcmstb: Disable L0s component of ASPM if requested
.../bindings/pci/brcm,stb-pcie.yaml | 4 ++++
drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++----
2 files changed, 19 insertions(+), 4 deletions(-)
--
2.17.1
From: Jim Quinlan <[email protected]>
clk_put() was being invoked on a clock obtained by
devm_clk_get_optional().
Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 6d79d14527a6..454917ee9241 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -899,7 +899,6 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie)
brcm_msi_remove(pcie);
brcm_pcie_turn_off(pcie);
clk_disable_unprepare(pcie->clk);
- clk_put(pcie->clk);
}
static int brcm_pcie_remove(struct platform_device *pdev)
--
2.17.1
From: Jim Quinlan <[email protected]>
The outbound memory window registers were being referenced
with an incorrect stride offset. This probably wasn't noticed
previously as there was likely only one such window employed.
Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
---
drivers/pci/controller/pcie-brcmstb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 454917ee9241..5b0dec5971b8 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -54,11 +54,11 @@
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
#define PCIE_MEM_WIN0_LO(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
#define PCIE_MEM_WIN0_HI(win) \
- PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
+ PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
--
2.17.1
From: Jim Quinlan <[email protected]>
For various reasons, one may want to disable the ASPM L0s
capability.
Signed-off-by: Jim Quinlan <[email protected]>
---
Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 77d3e81a437b..084e4cf68b95 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -56,6 +56,10 @@ properties:
description: Indicates usage of spread-spectrum clocking.
type: boolean
+ aspm-no-l0s:
+ description: Disables ASPM L0s capability.
+ type: boolean
+
required:
- reg
- dma-ranges
--
2.17.1
From: Jim Quinlan <[email protected]>
Some informal internal experiments has shown that the BrcmSTB ASPM L0s
savings may introduce an undesirable noise signal on some customers'
boards. In addition, L0s was found lacking in realized power savings,
especially relative to the L1 ASPM component. This is BrcmSTB's
experience and may not hold for others. At any rate, if the
'aspm-no-l0s' property is present L0s will be disabled.
Signed-off-by: Jim Quinlan <[email protected]>
Acked-by: Florian Fainelli <[email protected]>
---
drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 5b0dec5971b8..73020b4ff090 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -41,6 +41,9 @@
#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
+#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
+
#define PCIE_RC_DL_MDIO_ADDR 0x1100
#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
@@ -693,7 +696,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
int num_out_wins = 0;
u16 nlw, cls, lnksta;
int i, ret;
- u32 tmp;
+ u32 tmp, aspm_support;
/* Reset the bridge */
brcm_pcie_bridge_sw_init_set(pcie, 1);
@@ -803,6 +806,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
num_out_wins++;
}
+ /* Don't advertise L0s capability if 'aspm-no-l0s' */
+ aspm_support = PCIE_LINK_STATE_L1;
+ if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
+ aspm_support |= PCIE_LINK_STATE_L0S;
+ tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+ u32p_replace_bits(&tmp, aspm_support,
+ PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
+ writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
+
/*
* For config space accesses on the RC, show the right class for
* a PCIe-PCIe bridge (the default setting is to be EP mode).
--
2.17.1
On Fri, May 1, 2020 at 9:29 AM Jim Quinlan <[email protected]> wrote:
>
> From: Jim Quinlan <[email protected]>
>
> For various reasons, one may want to disable the ASPM L0s
> capability.
>
> Signed-off-by: Jim Quinlan <[email protected]>
> ---
> Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> index 77d3e81a437b..084e4cf68b95 100644
> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
> @@ -56,6 +56,10 @@ properties:
> description: Indicates usage of spread-spectrum clocking.
> type: boolean
>
> + aspm-no-l0s:
> + description: Disables ASPM L0s capability.
> + type: boolean
Copied from rockchip-pcie-host.txt? Let's make this a standard
property. It should be documented here[1].
Then this doc just needs 'aspm-no-l0s: true' to indicate you are using it.
Rob
[1] https://github.com/devicetree-org/dt-schema/blob/master/schemas/pci/pci-bus.yaml
On Fri, 2020-05-01 at 10:28 -0400, Jim Quinlan wrote:
> From: Jim Quinlan <[email protected]>
>
> The outbound memory window registers were being referenced
> with an incorrect stride offset. This probably wasn't noticed
> previously as there was likely only one such window employed.
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Acked-by: Florian Fainelli <[email protected]>
>
> Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller
> driver")
> ---
Acked-by: Nicolas Saenz Julienne <[email protected]>
Regards,
Nicolas
> drivers/pci/controller/pcie-brcmstb.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c
> b/drivers/pci/controller/pcie-brcmstb.c
> index 454917ee9241..5b0dec5971b8 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -54,11 +54,11 @@
>
> #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
> #define PCIE_MEM_WIN0_LO(win) \
> - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 4)
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
>
> #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
> #define PCIE_MEM_WIN0_HI(win) \
> - PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 4)
> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
>
> #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
> #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
On Fri, 2020-05-01 at 10:28 -0400, Jim Quinlan wrote:
> From: Jim Quinlan <[email protected]>
>
> clk_put() was being invoked on a clock obtained by
> devm_clk_get_optional().
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Acked-by: Florian Fainelli <[email protected]>
> ---
Acked-by: Nicolas Saenz Julienne <[email protected]>
Regards,
Nicolas
> drivers/pci/controller/pcie-brcmstb.c | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c
> b/drivers/pci/controller/pcie-brcmstb.c
> index 6d79d14527a6..454917ee9241 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -899,7 +899,6 @@ static void __brcm_pcie_remove(struct brcm_pcie *pcie)
> brcm_msi_remove(pcie);
> brcm_pcie_turn_off(pcie);
> clk_disable_unprepare(pcie->clk);
> - clk_put(pcie->clk);
> }
>
> static int brcm_pcie_remove(struct platform_device *pdev)
On Fri, 2020-05-01 at 10:28 -0400, Jim Quinlan wrote:
> From: Jim Quinlan <[email protected]>
>
> Some informal internal experiments has shown that the BrcmSTB ASPM L0s
> savings may introduce an undesirable noise signal on some customers'
> boards. In addition, L0s was found lacking in realized power savings,
> especially relative to the L1 ASPM component. This is BrcmSTB's
> experience and may not hold for others. At any rate, if the
> 'aspm-no-l0s' property is present L0s will be disabled.
>
> Signed-off-by: Jim Quinlan <[email protected]>
> Acked-by: Florian Fainelli <[email protected]>
Modulo the new generic dt property:
Acked-by: Nicolas Saenz Julienne <[email protected]>
Regards,
Nicolas
> ---
> drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/pcie-brcmstb.c
> b/drivers/pci/controller/pcie-brcmstb.c
> index 5b0dec5971b8..73020b4ff090 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -41,6 +41,9 @@
> #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
> #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
>
> +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
> +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
> +
> #define PCIE_RC_DL_MDIO_ADDR 0x1100
> #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
> #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
> @@ -693,7 +696,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> int num_out_wins = 0;
> u16 nlw, cls, lnksta;
> int i, ret;
> - u32 tmp;
> + u32 tmp, aspm_support;
>
> /* Reset the bridge */
> brcm_pcie_bridge_sw_init_set(pcie, 1);
> @@ -803,6 +806,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
> num_out_wins++;
> }
>
> + /* Don't advertise L0s capability if 'aspm-no-l0s' */
> + aspm_support = PCIE_LINK_STATE_L1;
> + if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
> + aspm_support |= PCIE_LINK_STATE_L0S;
> + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> + u32p_replace_bits(&tmp, aspm_support,
> + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
> + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
> +
> /*
> * For config space accesses on the RC, show the right class for
> * a PCIe-PCIe bridge (the default setting is to be EP mode).