Adds device tree binding documentation for clocks in the
MT7621 SOC.
Signed-off-by: Sergio Paracuellos <[email protected]>
---
.../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
new file mode 100644
index 000000000000..6aca4c1a4a46
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+ - Sergio Paracuellos <[email protected]>
+
+description: |
+ The MT7621 has a PLL controller from where the cpu clock is provided
+ as well as derived clocks for the bus and the peripherals. It also
+ can gate SoC device clocks.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ All these identifiers could be found in:
+ [1]: <include/dt-bindings/clock/mt7621-clk.h>.
+
+ The mt7621 clock node should be the child of a syscon node with the
+ required property:
+
+ - compatible: Should be one of the following:
+ "mediatek,mt7621-sysc", "syscon"
+
+ Refer to the bindings described in
+ Documentation/devicetree/bindings/mfd/syscon.yaml
+
+properties:
+ compatible:
+ const: mediatek,mt7621-clk
+
+ "#clock-cells":
+ description:
+ The first cell indicates the clock gate number, see [1] for available
+ clocks.
+ const: 1
+
+ clock-output-names:
+ maxItems: 8
+
+required:
+ - compatible
+ - '#clock-cells'
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt7621-clk.h>
+
+ sysc: sysc@0 {
+ compatible = "mediatek,mt7621-sysc", "syscon";
+ reg = <0x0 0x100>;
+
+ pll {
+ compatible = "mediatek,mt7621-clk";
+ #clock-cells = <1>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
+ };
+ };
--
2.25.1
Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> Adds device tree binding documentation for clocks in the
> MT7621 SOC.
>
> Signed-off-by: Sergio Paracuellos <[email protected]>
> ---
> .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
>
Rob?
> diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> new file mode 100644
> index 000000000000..6aca4c1a4a46
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MT7621 Clock Device Tree Bindings
> +
> +maintainers:
> + - Sergio Paracuellos <[email protected]>
> +
> +description: |
> + The MT7621 has a PLL controller from where the cpu clock is provided
> + as well as derived clocks for the bus and the peripherals. It also
> + can gate SoC device clocks.
> +
> + Each clock is assigned an identifier and client nodes use this identifier
> + to specify the clock which they consume.
> +
> + All these identifiers could be found in:
> + [1]: <include/dt-bindings/clock/mt7621-clk.h>.
> +
> + The mt7621 clock node should be the child of a syscon node with the
> + required property:
> +
> + - compatible: Should be one of the following:
> + "mediatek,mt7621-sysc", "syscon"
> +
> + Refer to the bindings described in
> + Documentation/devicetree/bindings/mfd/syscon.yaml
> +
> +properties:
> + compatible:
> + const: mediatek,mt7621-clk
> +
> + "#clock-cells":
> + description:
> + The first cell indicates the clock gate number, see [1] for available
> + clocks.
> + const: 1
> +
> + clock-output-names:
> + maxItems: 8
> +
> +required:
> + - compatible
> + - '#clock-cells'
> + - clock-output-names
Why is clock-output-names required? Hopefully it is not required.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt7621-clk.h>
> +
> + sysc: sysc@0 {
syscon@0? I don't think sysc is a standard node name.
> + compatible = "mediatek,mt7621-sysc", "syscon";
> + reg = <0x0 0x100>;
> +
> + pll {
clock-controller? Why can't the parent device be the clk provider and
have #clock-cells?
> + compatible = "mediatek,mt7621-clk";
> + #clock-cells = <1>;
> + clock-output-names = "xtal", "cpu", "bus",
> + "50m", "125m", "150m",
> + "250m", "270m";
> + };
> + };
Hi Stephen,
Thanks for the review!
On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd <[email protected]> wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos <[email protected]>
> > ---
> > .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++++++++++++++++++
> > 1 file changed, 67 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> >
>
> Rob?
>
> > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > new file mode 100644
> > index 000000000000..6aca4c1a4a46
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > @@ -0,0 +1,67 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MT7621 Clock Device Tree Bindings
> > +
> > +maintainers:
> > + - Sergio Paracuellos <[email protected]>
> > +
> > +description: |
> > + The MT7621 has a PLL controller from where the cpu clock is provided
> > + as well as derived clocks for the bus and the peripherals. It also
> > + can gate SoC device clocks.
> > +
> > + Each clock is assigned an identifier and client nodes use this identifier
> > + to specify the clock which they consume.
> > +
> > + All these identifiers could be found in:
> > + [1]: <include/dt-bindings/clock/mt7621-clk.h>.
> > +
> > + The mt7621 clock node should be the child of a syscon node with the
> > + required property:
> > +
> > + - compatible: Should be one of the following:
> > + "mediatek,mt7621-sysc", "syscon"
> > +
> > + Refer to the bindings described in
> > + Documentation/devicetree/bindings/mfd/syscon.yaml
> > +
> > +properties:
> > + compatible:
> > + const: mediatek,mt7621-clk
> > +
> > + "#clock-cells":
> > + description:
> > + The first cell indicates the clock gate number, see [1] for available
> > + clocks.
> > + const: 1
> > +
> > + clock-output-names:
> > + maxItems: 8
> > +
> > +required:
> > + - compatible
> > + - '#clock-cells'
> > + - clock-output-names
>
> Why is clock-output-names required? Hopefully it is not required.
Not really, can be removed from here.
>
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt7621-clk.h>
> > +
> > + sysc: sysc@0 {
>
> syscon@0? I don't think sysc is a standard node name.
Ok, I will change this into syscon@0 in both bindings and device tree file.
>
> > + compatible = "mediatek,mt7621-sysc", "syscon";
> > + reg = <0x0 0x100>;
> > +
> > + pll {
>
> clock-controller? Why can't the parent device be the clk provider and
> have #clock-cells?
>
I don't get your point, sorry. Can you please explain this a bit more
or point to me to an example to understand the real meaning of this?
> > + compatible = "mediatek,mt7621-clk";
> > + #clock-cells = <1>;
> > + clock-output-names = "xtal", "cpu", "bus",
> > + "50m", "125m", "150m",
> > + "250m", "270m";
> > + };
> > + };
Best regards,
Sergio Paracuellos
On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd <[email protected]> wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> >
> > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd <[email protected]> wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > >
> > > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > new file mode 100644
> > > > index 000000000000..6aca4c1a4a46
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > >
> > > > + compatible = "mediatek,mt7621-sysc", "syscon";
> > > > + reg = <0x0 0x100>;
> > > > +
> > > > + pll {
> > >
> > > clock-controller? Why can't the parent device be the clk provider and
> > > have #clock-cells?
> > >
> >
> > I don't get your point, sorry. Can you please explain this a bit more
> > or point to me to an example to understand the real meaning of this?
>
> It looks like this is a made up child node of syscon so that a driver
> can probe in the kernel. It would be more DT friendly to create a
> platform device from the parent node's driver, or just register the clks
> with the framework directly in that driver.
We cannot create a platform device because we need clocks available in
'plat_time_init' before setting up the timer for the GIC.
The only way I see to avoid this syscon and having this as a child
node is to use architecture operations in
'arch/mips/include/asm/mach-ralink/ralink_regs.h'
instead of getting a phandle using the regmap is being currently used...
Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd <[email protected]> wrote:
> >
> > Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> > >
> > > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd <[email protected]> wrote:
> > > >
> > > > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > > >
> > > > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > > new file mode 100644
> > > > > index 000000000000..6aca4c1a4a46
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > >
> > > > > + compatible = "mediatek,mt7621-sysc", "syscon";
> > > > > + reg = <0x0 0x100>;
> > > > > +
> > > > > + pll {
> > > >
> > > > clock-controller? Why can't the parent device be the clk provider and
> > > > have #clock-cells?
> > > >
> > >
> > > I don't get your point, sorry. Can you please explain this a bit more
> > > or point to me to an example to understand the real meaning of this?
> >
> > It looks like this is a made up child node of syscon so that a driver
> > can probe in the kernel. It would be more DT friendly to create a
> > platform device from the parent node's driver, or just register the clks
> > with the framework directly in that driver.
>
> We cannot create a platform device because we need clocks available in
> 'plat_time_init' before setting up the timer for the GIC.
> The only way I see to avoid this syscon and having this as a child
> node is to use architecture operations in
> 'arch/mips/include/asm/mach-ralink/ralink_regs.h'
> instead of getting a phandle using the regmap is being currently used...
Can that be done with
CLK_OF_DECLARE_DRIVER("mediatek,mt7621-sysc", my_timer_clk_init)
? Is the syscon used anywhere besides by the clk driver?
On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd <[email protected]> wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> > On Thu, Dec 17, 2020 at 11:07 AM Stephen Boyd <[email protected]> wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-12-17 02:01:39)
> > > >
> > > > On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd <[email protected]> wrote:
> > > > >
> > > > > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > > > >
> > > > > > diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > > > new file mode 100644
> > > > > > index 000000000000..6aca4c1a4a46
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > > > >
> > > > > > + compatible = "mediatek,mt7621-sysc", "syscon";
> > > > > > + reg = <0x0 0x100>;
> > > > > > +
> > > > > > + pll {
> > > > >
> > > > > clock-controller? Why can't the parent device be the clk provider and
> > > > > have #clock-cells?
> > > > >
> > > >
> > > > I don't get your point, sorry. Can you please explain this a bit more
> > > > or point to me to an example to understand the real meaning of this?
> > >
> > > It looks like this is a made up child node of syscon so that a driver
> > > can probe in the kernel. It would be more DT friendly to create a
> > > platform device from the parent node's driver, or just register the clks
> > > with the framework directly in that driver.
> >
> > We cannot create a platform device because we need clocks available in
> > 'plat_time_init' before setting up the timer for the GIC.
> > The only way I see to avoid this syscon and having this as a child
> > node is to use architecture operations in
> > 'arch/mips/include/asm/mach-ralink/ralink_regs.h'
> > instead of getting a phandle using the regmap is being currently used...
>
> Can that be done with
>
> CLK_OF_DECLARE_DRIVER("mediatek,mt7621-sysc", my_timer_clk_init)
>
> ? Is the syscon used anywhere besides by the clk driver?
Yes, for example all the gates use them to access SYSC_REG_CLKCFG1 in
all of their 'mt7621_gate_ops' and also in all 'recalc_rate' functions
where SYSC_REG_SYSTEM_CONFIG0, is readed.
Quoting Sergio Paracuellos (2020-12-17 02:38:37)
> On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd <[email protected]> wrote:
> >
> > Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> > > node is to use architecture operations in
> > > 'arch/mips/include/asm/mach-ralink/ralink_regs.h'
> > > instead of getting a phandle using the regmap is being currently used...
> >
> > Can that be done with
> >
> > CLK_OF_DECLARE_DRIVER("mediatek,mt7621-sysc", my_timer_clk_init)
> >
> > ? Is the syscon used anywhere besides by the clk driver?
>
> Yes, for example all the gates use them to access SYSC_REG_CLKCFG1 in
> all of their 'mt7621_gate_ops' and also in all 'recalc_rate' functions
> where SYSC_REG_SYSTEM_CONFIG0, is readed.
That sounds like it's only used by the clk provider/driver? Any other
code uses the syscon?
On Thu, Dec 17, 2020 at 11:50 AM Stephen Boyd <[email protected]> wrote:
>
> Quoting Sergio Paracuellos (2020-12-17 02:38:37)
> > On Thu, Dec 17, 2020 at 11:32 AM Stephen Boyd <[email protected]> wrote:
> > >
> > > Quoting Sergio Paracuellos (2020-12-17 02:14:10)
> > > > node is to use architecture operations in
> > > > 'arch/mips/include/asm/mach-ralink/ralink_regs.h'
> > > > instead of getting a phandle using the regmap is being currently used...
> > >
> > > Can that be done with
> > >
> > > CLK_OF_DECLARE_DRIVER("mediatek,mt7621-sysc", my_timer_clk_init)
> > >
> > > ? Is the syscon used anywhere besides by the clk driver?
> >
> > Yes, for example all the gates use them to access SYSC_REG_CLKCFG1 in
> > all of their 'mt7621_gate_ops' and also in all 'recalc_rate' functions
> > where SYSC_REG_SYSTEM_CONFIG0, is readed.
>
> That sounds like it's only used by the clk provider/driver? Any other
> code uses the syscon?
The only child node for the syscon for this platform is the clock
driver now, I introduced it in this series, so no other driver is
using this syscon now. All of them use global arch operations in
'arch/mips/include/asm/mach-ralink/ralink_regs.h'.
On Thu, Dec 17, 2020 at 2:58 AM Stephen Boyd <[email protected]> wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos <[email protected]>
> > ---
> > .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++++++++++++++++++
> > 1 file changed, 67 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> >
>
> Rob?
Send to the DT list please.
But I agree with Stephen's comment. Either make the syscon complete
(fully describe the h/w, not just what you need ATM) to show the need
for child nodes or get rid of the child nodes.
Rob
Hi Rob,
On Thu, Dec 17, 2020 at 4:05 PM Rob Herring <[email protected]> wrote:
>
> On Thu, Dec 17, 2020 at 2:58 AM Stephen Boyd <[email protected]> wrote:
> >
> > Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > > Adds device tree binding documentation for clocks in the
> > > MT7621 SOC.
> > >
> > > Signed-off-by: Sergio Paracuellos <[email protected]>
> > > ---
> > > .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++++++++++++++++++
> > > 1 file changed, 67 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
> > >
> >
> > Rob?
>
> Send to the DT list please.
Sorry, there was a typo '[email protected]' in CC list.
>
> But I agree with Stephen's comment. Either make the syscon complete
> (fully describe the h/w, not just what you need ATM) to show the need
> for child nodes or get rid of the child nodes.
Got it. Will try to do something better and send v5.
>
> Rob
Thanks,
Sergio Paracuellos