AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
supports up to 80 pins.
In the current driver design, the max number of sgpio pins is hardcoded
in macro MAX_NR_HW_SGPIO and the value is 80.
For supporting sgpio master interfaces of AST2600 SoC, the patch series
contains the following enhancement:
- Convert txt dt-bindings to yaml.
- Update aspeed-g6 dtsi to support the enhanced sgpio.
- Support muiltiple SGPIO master interfaces.
- Support up to 128 pins by dts ngpios property.
- Pair input/output GPIOs instead of using 0 as GPIO input pin base and
MAX_NR_HW_SGPIO as GPIO output pin base.
- Support wdt reset tolerance.
- Fix irq_chip issues which causes multiple sgpio devices use the same
irq_chip data.
- Replace all of_*() APIs with device_*().
Changes from v5:
* Squash v5 patch-05 and patch-06 to one patch.
* Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
input/output pin base are determined by ngpios.
For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
pin order is as follows:
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
With the new design, pin order is changed as follows:
Input:
0 2 4 6 ... 18(ngpios * 2 - 2)
Output:
1 3 5 7 ... 19(ngpios * 2 - 1)
* Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
ast2600-sgpiom.
* Fix coding style issues.
Changes from v4:
* Remove ngpios from dtsi
* Add ast2400 and ast2500 platform data.
* Remove unused macros.
* Add ngpios check in a separate patch.
* Fix coding style issues.
Changes from v3:
* Split dt-bindings patch to 2 patches
* Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
* Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
* Correct the typo in commit messages.
* Fix coding style issues.
* Replace all of_*() APIs with device_*().
Changes from v2:
* Remove maximum/minimum of ngpios from bindings.
* Remove max-ngpios from bindings and dtsi.
* Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
driver.
* Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
number of available gpio pins are different.
* Modify functions to pass aspeed_sgpio struct instead of passing
max_ngpios.
* Split sgpio driver patch to 3 patches
Changes from v1:
* Fix yaml format issues.
* Fix issues reported by kernel test robot.
Please help to review.
Thanks,
Steven
Steven Lee (9):
dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
dt-bindings: aspeed-sgpio: Add ast2600 sgpio
ARM: dts: aspeed-g6: Add SGPIO node.
ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
gpio: gpio-aspeed-sgpio: Add set_config function
gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
gpio: gpio-aspeed-sgpio: Use generic device property APIs
gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
.../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
5 files changed, 215 insertions(+), 115 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
--
2.17.1
sgpio-aspeed bindings should be converted to yaml format.
Signed-off-by: Steven Lee <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../bindings/gpio/aspeed,sgpio.yaml | 75 +++++++++++++++++++
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 ------------
2 files changed, 75 insertions(+), 46 deletions(-)
create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
new file mode 100644
index 000000000000..b2ae211411ff
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Aspeed SGPIO controller
+
+maintainers:
+ - Andrew Jeffery <[email protected]>
+
+description:
+ This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
+ featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
+ support the following options
+ - Support interrupt option for each input port and various interrupt
+ sensitivity option (level-high, level-low, edge-high, edge-low)
+ - Support reset tolerance option for each output port
+ - Directly connected to APB bus and its shift clock is from APB bus clock
+ divided by a programmable value.
+ - Co-work with external signal-chained TTL components (74LV165/74LV595)
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2400-sgpio
+ - aspeed,ast2500-sgpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ clocks:
+ maxItems: 1
+
+ ngpios: true
+
+ bus-frequency: true
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - interrupts
+ - interrupt-controller
+ - ngpios
+ - clocks
+ - bus-frequency
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed-clock.h>
+ sgpio: sgpio@1e780200 {
+ #gpio-cells = <2>;
+ compatible = "aspeed,ast2500-sgpio";
+ gpio-controller;
+ interrupts = <40>;
+ reg = <0x1e780200 0x0100>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ interrupt-controller;
+ ngpios = <80>;
+ bus-frequency = <12000000>;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
deleted file mode 100644
index be329ea4794f..000000000000
--- a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Aspeed SGPIO controller Device Tree Bindings
---------------------------------------------
-
-This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
-featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
-support the following options:
-- Support interrupt option for each input port and various interrupt
- sensitivity option (level-high, level-low, edge-high, edge-low)
-- Support reset tolerance option for each output port
-- Directly connected to APB bus and its shift clock is from APB bus clock
- divided by a programmable value.
-- Co-work with external signal-chained TTL components (74LV165/74LV595)
-
-Required properties:
-
-- compatible : Should be one of
- "aspeed,ast2400-sgpio", "aspeed,ast2500-sgpio"
-- #gpio-cells : Should be 2, see gpio.txt
-- reg : Address and length of the register set for the device
-- gpio-controller : Marks the device node as a GPIO controller
-- interrupts : Interrupt specifier, see interrupt-controller/interrupts.txt
-- interrupt-controller : Mark the GPIO controller as an interrupt-controller
-- ngpios : number of *hardware* GPIO lines, see gpio.txt. This will expose
- 2 software GPIOs per hardware GPIO: one for hardware input, one for hardware
- output. Up to 80 pins, must be a multiple of 8.
-- clocks : A phandle to the APB clock for SGPM clock division
-- bus-frequency : SGPM CLK frequency
-
-The sgpio and interrupt properties are further described in their respective
-bindings documentation:
-
-- Documentation/devicetree/bindings/gpio/gpio.txt
-- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
- Example:
- sgpio: sgpio@1e780200 {
- #gpio-cells = <2>;
- compatible = "aspeed,ast2500-sgpio";
- gpio-controller;
- interrupts = <40>;
- reg = <0x1e780200 0x0100>;
- clocks = <&syscon ASPEED_CLK_APB>;
- interrupt-controller;
- ngpios = <8>;
- bus-frequency = <12000000>;
- };
--
2.17.1
AST2600 supports 2 SGPIO master interfaces one with 128 pins another one
with 80 pins.
Signed-off-by: Steven Lee <[email protected]>
---
arch/arm/boot/dts/aspeed-g6.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index f96607b7b4e2..1b47be1704f8 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -377,6 +377,34 @@
#interrupt-cells = <2>;
};
+ sgpiom0: sgpiom@1e780500 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2600-sgpiom";
+ reg = <0x1e780500 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ interrupt-controller;
+ bus-frequency = <12000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm1_default>;
+ status = "disabled";
+ };
+
+ sgpiom1: sgpiom@1e780600 {
+ #gpio-cells = <2>;
+ gpio-controller;
+ compatible = "aspeed,ast2600-sgpiom";
+ reg = <0x1e780600 0x100>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_APB2>;
+ interrupt-controller;
+ bus-frequency = <12000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sgpm2_default>;
+ status = "disabled";
+ };
+
gpio1: gpio@1e780800 {
#gpio-cells = <2>;
gpio-controller;
--
2.17.1
Remove ngpios property from sgpio node as it should be defined in the
platform dts.
Signed-off-by: Steven Lee <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
---
arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 329eaeef66fb..73ca1ec6fc24 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -352,7 +352,6 @@
reg = <0x1e780200 0x0100>;
clocks = <&syscon ASPEED_CLK_APB>;
interrupt-controller;
- ngpios = <8>;
bus-frequency = <12000000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sgpm_default>;
--
2.17.1
The maximum number of gpio pins of SoC is hardcoded as 80 and the gpio pin
count mask for GPIO Configuration register is hardcode as GENMASK(9,6).
However, AST2600 has 2 sgpio master interfaces, one of them supports up
to 128 gpio pins and pin count mask of GPIO Configuration Register is 5
bits.
The patch adds ast2600 compatibles, removes MAX_NR_HW_SGPIO and
corresponding design to make the gpio input/output pin base are determined
by ngpios.
The patch also removed hardcoded pin mask and adds ast2400, ast2500,
ast2600 platform data that include gpio pin count mask for GPIO
Configuration Register.
The original pin order is as follows:
(suppose MAX_NR_HW_SGPIO is 80 and ngpios is 10 as well)
Input:
0 1 2 3 ... 9
Output:
80 81 82 ... 89
The new pin order is as follows:
Input:
0 2 4 6 ... 18
Output:
1 3 5 7 ... 19
SGPIO pin id and input/output pin mapping is as follows:
SGPIO0(0,1), SGPIO1(2,3), ..., SGPIO79(158,159)
For example:
Access SGPIO5(10,11)
Get SGPIO pin 5 (suppose sgpio chip id is 2)
gpioget 2 10
Set SGPIO pin 5 (suppose sgpio chip id is 2)
gpioset 2 11=1
gpioset 2 11=0
Signed-off-by: Steven Lee <[email protected]>
---
drivers/gpio/gpio-aspeed-sgpio.c | 101 ++++++++++++++-----------------
1 file changed, 47 insertions(+), 54 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 64e54f8c30d2..8f6bacd23e13 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -17,23 +17,15 @@
#include <linux/spinlock.h>
#include <linux/string.h>
-/*
- * MAX_NR_HW_GPIO represents the number of actual hardware-supported GPIOs (ie,
- * slots within the clocked serial GPIO data). Since each HW GPIO is both an
- * input and an output, we provide MAX_NR_HW_GPIO * 2 lines on our gpiochip
- * device.
- *
- * We use SGPIO_OUTPUT_OFFSET to define the split between the inputs and
- * outputs; the inputs start at line 0, the outputs start at OUTPUT_OFFSET.
- */
-#define MAX_NR_HW_SGPIO 80
-#define SGPIO_OUTPUT_OFFSET MAX_NR_HW_SGPIO
-
#define ASPEED_SGPIO_CTRL 0x54
-#define ASPEED_SGPIO_PINS_MASK GENMASK(9, 6)
#define ASPEED_SGPIO_CLK_DIV_MASK GENMASK(31, 16)
#define ASPEED_SGPIO_ENABLE BIT(0)
+#define ASPEED_SGPIO_PINS_SHIFT 6
+
+struct aspeed_sgpio_pdata {
+ const u32 pin_mask;
+};
struct aspeed_sgpio {
struct gpio_chip chip;
@@ -41,7 +33,6 @@ struct aspeed_sgpio {
spinlock_t lock;
void __iomem *base;
int irq;
- int n_sgpio;
};
struct aspeed_sgpio_bank {
@@ -75,7 +66,13 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
.val_regs = 0x0038,
.rdata_reg = 0x0078,
.irq_regs = 0x003C,
- .names = { "I", "J" },
+ .names = { "I", "J", "K", "L" },
+ },
+ {
+ .val_regs = 0x0090,
+ .rdata_reg = 0x007C,
+ .irq_regs = 0x0094,
+ .names = { "M", "N", "O", "P" },
},
};
@@ -121,9 +118,9 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
}
}
-#define GPIO_BANK(x) ((x % SGPIO_OUTPUT_OFFSET) >> 5)
-#define GPIO_OFFSET(x) ((x % SGPIO_OUTPUT_OFFSET) & 0x1f)
-#define GPIO_BIT(x) BIT(GPIO_OFFSET(x))
+#define GPIO_BANK(x) ((x) >> 6)
+#define GPIO_OFFSET(x) ((x) & GENMASK(5, 0))
+#define GPIO_BIT(x) BIT(GPIO_OFFSET(x) >> 1)
static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
{
@@ -138,39 +135,25 @@ static const struct aspeed_sgpio_bank *to_bank(unsigned int offset)
static int aspeed_sgpio_init_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask, unsigned int ngpios)
{
- struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
- int n = sgpio->n_sgpio;
- int c = SGPIO_OUTPUT_OFFSET - n;
-
- WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
-
- /* input GPIOs in the lower range */
- bitmap_set(valid_mask, 0, n);
- bitmap_clear(valid_mask, n, c);
-
- /* output GPIOS above SGPIO_OUTPUT_OFFSET */
- bitmap_set(valid_mask, SGPIO_OUTPUT_OFFSET, n);
- bitmap_clear(valid_mask, SGPIO_OUTPUT_OFFSET + n, c);
-
+ bitmap_set(valid_mask, 0, ngpios);
return 0;
}
static void aspeed_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask, unsigned int ngpios)
{
- struct aspeed_sgpio *sgpio = gpiochip_get_data(gc);
- int n = sgpio->n_sgpio;
+ unsigned int i;
- WARN_ON(ngpios < MAX_NR_HW_SGPIO * 2);
-
- /* input GPIOs in the lower range */
- bitmap_set(valid_mask, 0, n);
- bitmap_clear(valid_mask, n, ngpios - n);
+ /* input GPIOs are even bits */
+ for (i = 0; i < ngpios; i++) {
+ if (i % 2)
+ clear_bit(i, valid_mask);
+ }
}
static bool aspeed_sgpio_is_input(unsigned int offset)
{
- return offset < SGPIO_OUTPUT_OFFSET;
+ return !(offset % 2);
}
static int aspeed_sgpio_get(struct gpio_chip *gc, unsigned int offset)
@@ -466,9 +449,18 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
return 0;
}
+static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
+ .pin_mask = GENMASK(9, 6),
+};
+
+static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
+ .pin_mask = GENMASK(10, 6),
+};
+
static const struct of_device_id aspeed_sgpio_of_table[] = {
- { .compatible = "aspeed,ast2400-sgpio" },
- { .compatible = "aspeed,ast2500-sgpio" },
+ { .compatible = "aspeed,ast2400-sgpio", .data = &ast2400_sgpio_pdata, },
+ { .compatible = "aspeed,ast2500-sgpio", .data = &ast2400_sgpio_pdata, },
+ { .compatible = "aspeed,ast2600-sgpiom", .data = &ast2600_sgpiom_pdata, },
{}
};
@@ -476,10 +468,11 @@ MODULE_DEVICE_TABLE(of, aspeed_sgpio_of_table);
static int __init aspeed_sgpio_probe(struct platform_device *pdev)
{
+ u32 nr_gpios, sgpio_freq, sgpio_clk_div, gpio_cnt_regval, pin_mask;
+ const struct aspeed_sgpio_pdata *pdata;
struct aspeed_sgpio *gpio;
- u32 nr_gpios, sgpio_freq, sgpio_clk_div;
- int rc;
unsigned long apb_freq;
+ int rc;
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio)
@@ -489,16 +482,17 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
if (IS_ERR(gpio->base))
return PTR_ERR(gpio->base);
+ pdata = device_get_match_data(&pdev->dev);
+ if (!pdata)
+ return -EINVAL;
+
+ pin_mask = pdata->pin_mask;
+
rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
if (rc < 0) {
dev_err(&pdev->dev, "Could not read ngpios property\n");
return -EINVAL;
- } else if (nr_gpios > MAX_NR_HW_SGPIO) {
- dev_err(&pdev->dev, "Number of GPIOs exceeds the maximum of %d: %d\n",
- MAX_NR_HW_SGPIO, nr_gpios);
- return -EINVAL;
}
- gpio->n_sgpio = nr_gpios;
rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
if (rc < 0) {
@@ -531,15 +525,14 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
if (sgpio_clk_div > (1 << 16) - 1)
return -EINVAL;
- iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) |
- FIELD_PREP(ASPEED_SGPIO_PINS_MASK, (nr_gpios / 8)) |
- ASPEED_SGPIO_ENABLE,
- gpio->base + ASPEED_SGPIO_CTRL);
+ gpio_cnt_regval = ((nr_gpios / 8) << ASPEED_SGPIO_PINS_SHIFT) & pin_mask;
+ iowrite32(FIELD_PREP(ASPEED_SGPIO_CLK_DIV_MASK, sgpio_clk_div) | gpio_cnt_regval |
+ ASPEED_SGPIO_ENABLE, gpio->base + ASPEED_SGPIO_CTRL);
spin_lock_init(&gpio->lock);
gpio->chip.parent = &pdev->dev;
- gpio->chip.ngpio = MAX_NR_HW_SGPIO * 2;
+ gpio->chip.ngpio = nr_gpios * 2;
gpio->chip.init_valid_mask = aspeed_sgpio_init_valid_mask;
gpio->chip.direction_input = aspeed_sgpio_dir_in;
gpio->chip.direction_output = aspeed_sgpio_dir_out;
--
2.17.1
The current design initializes irq->chip from a global irqchip struct,
which causes multiple sgpio devices use the same irq_chip.
The patch moves irq_chip to aspeed_sgpio struct for initializing
irq_chip from their private gpio struct.
Signed-off-by: Steven Lee <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
---
drivers/gpio/gpio-aspeed-sgpio.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 9b809c28f842..6b3695197c97 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -29,6 +29,7 @@ struct aspeed_sgpio_pdata {
struct aspeed_sgpio {
struct gpio_chip chip;
+ struct irq_chip intc;
struct clk *pclk;
spinlock_t lock;
void __iomem *base;
@@ -403,14 +404,6 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc)
chained_irq_exit(ic, desc);
}
-static struct irq_chip aspeed_sgpio_irqchip = {
- .name = "aspeed-sgpio",
- .irq_ack = aspeed_sgpio_irq_ack,
- .irq_mask = aspeed_sgpio_irq_mask,
- .irq_unmask = aspeed_sgpio_irq_unmask,
- .irq_set_type = aspeed_sgpio_set_type,
-};
-
static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
struct platform_device *pdev)
{
@@ -433,8 +426,14 @@ static int aspeed_sgpio_setup_irqs(struct aspeed_sgpio *gpio,
iowrite32(0xffffffff, bank_reg(gpio, bank, reg_irq_status));
}
+ gpio->intc.name = dev_name(&pdev->dev);
+ gpio->intc.irq_ack = aspeed_sgpio_irq_ack;
+ gpio->intc.irq_mask = aspeed_sgpio_irq_mask;
+ gpio->intc.irq_unmask = aspeed_sgpio_irq_unmask;
+ gpio->intc.irq_set_type = aspeed_sgpio_set_type;
+
irq = &gpio->chip.irq;
- irq->chip = &aspeed_sgpio_irqchip;
+ irq->chip = &gpio->intc;
irq->init_valid_mask = aspeed_sgpio_irq_init_valid_mask;
irq->handler = handle_bad_irq;
irq->default_type = IRQ_TYPE_NONE;
--
2.17.1
AST SoC supports *retain pin state* function when wdt reset.
The patch adds set_config function for handling sgpio reset tolerance
register.
Signed-off-by: Steven Lee <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
---
drivers/gpio/gpio-aspeed-sgpio.c | 54 +++++++++++++++++++++++++++++---
1 file changed, 50 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 8f6bacd23e13..9b809c28f842 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -36,9 +36,10 @@ struct aspeed_sgpio {
};
struct aspeed_sgpio_bank {
- uint16_t val_regs;
- uint16_t rdata_reg;
- uint16_t irq_regs;
+ u16 val_regs;
+ u16 rdata_reg;
+ u16 irq_regs;
+ u16 tolerance_regs;
const char names[4][3];
};
@@ -54,24 +55,28 @@ static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
.val_regs = 0x0000,
.rdata_reg = 0x0070,
.irq_regs = 0x0004,
+ .tolerance_regs = 0x0018,
.names = { "A", "B", "C", "D" },
},
{
.val_regs = 0x001C,
.rdata_reg = 0x0074,
.irq_regs = 0x0020,
+ .tolerance_regs = 0x0034,
.names = { "E", "F", "G", "H" },
},
{
.val_regs = 0x0038,
.rdata_reg = 0x0078,
.irq_regs = 0x003C,
+ .tolerance_regs = 0x0050,
.names = { "I", "J", "K", "L" },
},
{
.val_regs = 0x0090,
.rdata_reg = 0x007C,
.irq_regs = 0x0094,
+ .tolerance_regs = 0x00A8,
.names = { "M", "N", "O", "P" },
},
};
@@ -84,6 +89,7 @@ enum aspeed_sgpio_reg {
reg_irq_type1,
reg_irq_type2,
reg_irq_status,
+ reg_tolerance,
};
#define GPIO_VAL_VALUE 0x00
@@ -112,6 +118,8 @@ static void __iomem *bank_reg(struct aspeed_sgpio *gpio,
return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2;
case reg_irq_status:
return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS;
+ case reg_tolerance:
+ return gpio->base + bank->tolerance_regs;
default:
/* acturally if code runs to here, it's an error case */
BUG();
@@ -453,6 +461,44 @@ static const struct aspeed_sgpio_pdata ast2400_sgpio_pdata = {
.pin_mask = GENMASK(9, 6),
};
+static int aspeed_sgpio_reset_tolerance(struct gpio_chip *chip,
+ unsigned int offset, bool enable)
+{
+ struct aspeed_sgpio *gpio = gpiochip_get_data(chip);
+ unsigned long flags;
+ void __iomem *reg;
+ u32 val;
+
+ reg = bank_reg(gpio, to_bank(offset), reg_tolerance);
+
+ spin_lock_irqsave(&gpio->lock, flags);
+
+ val = readl(reg);
+
+ if (enable)
+ val |= GPIO_BIT(offset);
+ else
+ val &= ~GPIO_BIT(offset);
+
+ writel(val, reg);
+
+ spin_unlock_irqrestore(&gpio->lock, flags);
+
+ return 0;
+}
+
+static int aspeed_sgpio_set_config(struct gpio_chip *chip, unsigned int offset,
+ unsigned long config)
+{
+ unsigned long param = pinconf_to_config_param(config);
+ u32 arg = pinconf_to_config_argument(config);
+
+ if (param == PIN_CONFIG_PERSIST_STATE)
+ return aspeed_sgpio_reset_tolerance(chip, offset, arg);
+
+ return -ENOTSUPP;
+}
+
static const struct aspeed_sgpio_pdata ast2600_sgpiom_pdata = {
.pin_mask = GENMASK(10, 6),
};
@@ -541,7 +587,7 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
gpio->chip.free = NULL;
gpio->chip.get = aspeed_sgpio_get;
gpio->chip.set = aspeed_sgpio_set;
- gpio->chip.set_config = NULL;
+ gpio->chip.set_config = aspeed_sgpio_set_config;
gpio->chip.label = dev_name(&pdev->dev);
gpio->chip.base = -1;
--
2.17.1
Replace all of_property_read_u32() with device_property_read_u32().
Signed-off-by: Steven Lee <[email protected]>
Acked-by: Andrew Jeffery <[email protected]>
---
drivers/gpio/gpio-aspeed-sgpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index 6b3695197c97..b3d05fc724f0 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -533,13 +533,13 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
pin_mask = pdata->pin_mask;
- rc = of_property_read_u32(pdev->dev.of_node, "ngpios", &nr_gpios);
+ rc = device_property_read_u32(&pdev->dev, "ngpios", &nr_gpios);
if (rc < 0) {
dev_err(&pdev->dev, "Could not read ngpios property\n");
return -EINVAL;
}
- rc = of_property_read_u32(pdev->dev.of_node, "bus-frequency", &sgpio_freq);
+ rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
if (rc < 0) {
dev_err(&pdev->dev, "Could not read bus-frequency property\n");
return -EINVAL;
--
2.17.1
Add an else-if condition in the probe function to check whether ngpios is
multiple of 8.
Per AST datasheet, numbers of available serial GPIO pins in Serial GPIO
Configuration Register must be n bytes. For instance, if n = 1, it means
AST SoC supports 8 GPIO pins.
Signed-off-by: Steven Lee <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
---
drivers/gpio/gpio-aspeed-sgpio.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c
index b3d05fc724f0..191b82a2560c 100644
--- a/drivers/gpio/gpio-aspeed-sgpio.c
+++ b/drivers/gpio/gpio-aspeed-sgpio.c
@@ -537,6 +537,10 @@ static int __init aspeed_sgpio_probe(struct platform_device *pdev)
if (rc < 0) {
dev_err(&pdev->dev, "Could not read ngpios property\n");
return -EINVAL;
+ } else if (nr_gpios % 8) {
+ dev_err(&pdev->dev, "Number of GPIOs not multiple of 8: %d\n",
+ nr_gpios);
+ return -EINVAL;
}
rc = device_property_read_u32(&pdev->dev, "bus-frequency", &sgpio_freq);
--
2.17.1
AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
with 80 pins. Add ast2600-sgpiom compatibles and update descriptions to
introduce the max number of available gpio pins that AST2600 supported.
Signed-off-by: Steven Lee <[email protected]>
---
Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
index b2ae211411ff..46bb121360dc 100644
--- a/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
@@ -10,9 +10,10 @@ maintainers:
- Andrew Jeffery <[email protected]>
description:
- This SGPIO controller is for ASPEED AST2500 SoC, it supports up to 80 full
- featured Serial GPIOs. Each of the Serial GPIO pins can be programmed to
- support the following options
+ This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
+ AST2600 have two sgpio master one with 128 pins another one with 80 pins,
+ AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
+ GPIO pins can be programmed to support the following options
- Support interrupt option for each input port and various interrupt
sensitivity option (level-high, level-low, edge-high, edge-low)
- Support reset tolerance option for each output port
@@ -25,6 +26,7 @@ properties:
enum:
- aspeed,ast2400-sgpio
- aspeed,ast2500-sgpio
+ - aspeed,ast2600-sgpiom
reg:
maxItems: 1
--
2.17.1
On Mon, 12 Jul 2021 18:03:09 +0800, Steven Lee wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins. Add ast2600-sgpiom compatibles and update descriptions to
> introduce the max number of available gpio pins that AST2600 supported.
>
> Signed-off-by: Steven Lee <[email protected]>
> ---
> Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <[email protected]> wrote:
>
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
> supports up to 80 pins.
> In the current driver design, the max number of sgpio pins is hardcoded
> in macro MAX_NR_HW_SGPIO and the value is 80.
>
> For supporting sgpio master interfaces of AST2600 SoC, the patch series
> contains the following enhancement:
> - Convert txt dt-bindings to yaml.
> - Update aspeed-g6 dtsi to support the enhanced sgpio.
> - Support muiltiple SGPIO master interfaces.
> - Support up to 128 pins by dts ngpios property.
> - Pair input/output GPIOs instead of using 0 as GPIO input pin base and
> MAX_NR_HW_SGPIO as GPIO output pin base.
> - Support wdt reset tolerance.
> - Fix irq_chip issues which causes multiple sgpio devices use the same
> irq_chip data.
> - Replace all of_*() APIs with device_*().
>
> Changes from v5:
> * Squash v5 patch-05 and patch-06 to one patch.
> * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
> input/output pin base are determined by ngpios.
> For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
> pin order is as follows:
> Input:
> 0 1 2 3 ... 9
> Output:
> 80 81 82 ... 89
>
> With the new design, pin order is changed as follows:
> Input:
> 0 2 4 6 ... 18(ngpios * 2 - 2)
> Output:
> 1 3 5 7 ... 19(ngpios * 2 - 1)
> * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
> ast2600-sgpiom.
> * Fix coding style issues.
>
> Changes from v4:
> * Remove ngpios from dtsi
> * Add ast2400 and ast2500 platform data.
> * Remove unused macros.
> * Add ngpios check in a separate patch.
> * Fix coding style issues.
>
> Changes from v3:
> * Split dt-bindings patch to 2 patches
> * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
> * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
> * Correct the typo in commit messages.
> * Fix coding style issues.
> * Replace all of_*() APIs with device_*().
>
> Changes from v2:
> * Remove maximum/minimum of ngpios from bindings.
> * Remove max-ngpios from bindings and dtsi.
> * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
> driver.
> * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
> number of available gpio pins are different.
> * Modify functions to pass aspeed_sgpio struct instead of passing
> max_ngpios.
> * Split sgpio driver patch to 3 patches
>
> Changes from v1:
> * Fix yaml format issues.
> * Fix issues reported by kernel test robot.
>
> Please help to review.
>
> Thanks,
> Steven
>
> Steven Lee (9):
> dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
> dt-bindings: aspeed-sgpio: Add ast2600 sgpio
> ARM: dts: aspeed-g6: Add SGPIO node.
> ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
> gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
> gpio: gpio-aspeed-sgpio: Add set_config function
> gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
> gpio: gpio-aspeed-sgpio: Use generic device property APIs
> gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
>
> .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
> .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
> arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
> arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
> drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
> 5 files changed, 215 insertions(+), 115 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
>
> --
> 2.17.1
>
The series looks good to me. Can the DTS and GPIO patches go into
v5.15 separately?
Bart
The 07/21/2021 21:27, Bartosz Golaszewski wrote:
> On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <[email protected]> wrote:
> >
> > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
> > supports up to 80 pins.
> > In the current driver design, the max number of sgpio pins is hardcoded
> > in macro MAX_NR_HW_SGPIO and the value is 80.
> >
> > For supporting sgpio master interfaces of AST2600 SoC, the patch series
> > contains the following enhancement:
> > - Convert txt dt-bindings to yaml.
> > - Update aspeed-g6 dtsi to support the enhanced sgpio.
> > - Support muiltiple SGPIO master interfaces.
> > - Support up to 128 pins by dts ngpios property.
> > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and
> > MAX_NR_HW_SGPIO as GPIO output pin base.
> > - Support wdt reset tolerance.
> > - Fix irq_chip issues which causes multiple sgpio devices use the same
> > irq_chip data.
> > - Replace all of_*() APIs with device_*().
> >
> > Changes from v5:
> > * Squash v5 patch-05 and patch-06 to one patch.
> > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
> > input/output pin base are determined by ngpios.
> > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
> > pin order is as follows:
> > Input:
> > 0 1 2 3 ... 9
> > Output:
> > 80 81 82 ... 89
> >
> > With the new design, pin order is changed as follows:
> > Input:
> > 0 2 4 6 ... 18(ngpios * 2 - 2)
> > Output:
> > 1 3 5 7 ... 19(ngpios * 2 - 1)
> > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
> > ast2600-sgpiom.
> > * Fix coding style issues.
> >
> > Changes from v4:
> > * Remove ngpios from dtsi
> > * Add ast2400 and ast2500 platform data.
> > * Remove unused macros.
> > * Add ngpios check in a separate patch.
> > * Fix coding style issues.
> >
> > Changes from v3:
> > * Split dt-bindings patch to 2 patches
> > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
> > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
> > * Correct the typo in commit messages.
> > * Fix coding style issues.
> > * Replace all of_*() APIs with device_*().
> >
> > Changes from v2:
> > * Remove maximum/minimum of ngpios from bindings.
> > * Remove max-ngpios from bindings and dtsi.
> > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
> > driver.
> > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
> > number of available gpio pins are different.
> > * Modify functions to pass aspeed_sgpio struct instead of passing
> > max_ngpios.
> > * Split sgpio driver patch to 3 patches
> >
> > Changes from v1:
> > * Fix yaml format issues.
> > * Fix issues reported by kernel test robot.
> >
> > Please help to review.
> >
> > Thanks,
> > Steven
> >
> > Steven Lee (9):
> > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
> > dt-bindings: aspeed-sgpio: Add ast2600 sgpio
> > ARM: dts: aspeed-g6: Add SGPIO node.
> > ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
> > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
> > gpio: gpio-aspeed-sgpio: Add set_config function
> > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
> > gpio: gpio-aspeed-sgpio: Use generic device property APIs
> > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
> >
> > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
> > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
> > arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
> > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
> > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
> > 5 files changed, 215 insertions(+), 115 deletions(-)
> > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> >
> > --
> > 2.17.1
> >
>
> The series looks good to me. Can the DTS and GPIO patches go into
> v5.15 separately?
>
Hi Bart,
Thanks for the review.
Shall we do anything to make the patches go into v5.15 or wait for picking-up?
Steven
> Bart
On Fri, Jul 23, 2021 at 5:16 AM Steven Lee <[email protected]> wrote:
>
> The 07/21/2021 21:27, Bartosz Golaszewski wrote:
> > On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <[email protected]> wrote:
> > >
> > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
> > > supports up to 80 pins.
> > > In the current driver design, the max number of sgpio pins is hardcoded
> > > in macro MAX_NR_HW_SGPIO and the value is 80.
> > >
> > > For supporting sgpio master interfaces of AST2600 SoC, the patch series
> > > contains the following enhancement:
> > > - Convert txt dt-bindings to yaml.
> > > - Update aspeed-g6 dtsi to support the enhanced sgpio.
> > > - Support muiltiple SGPIO master interfaces.
> > > - Support up to 128 pins by dts ngpios property.
> > > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and
> > > MAX_NR_HW_SGPIO as GPIO output pin base.
> > > - Support wdt reset tolerance.
> > > - Fix irq_chip issues which causes multiple sgpio devices use the same
> > > irq_chip data.
> > > - Replace all of_*() APIs with device_*().
> > >
> > > Changes from v5:
> > > * Squash v5 patch-05 and patch-06 to one patch.
> > > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
> > > input/output pin base are determined by ngpios.
> > > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
> > > pin order is as follows:
> > > Input:
> > > 0 1 2 3 ... 9
> > > Output:
> > > 80 81 82 ... 89
> > >
> > > With the new design, pin order is changed as follows:
> > > Input:
> > > 0 2 4 6 ... 18(ngpios * 2 - 2)
> > > Output:
> > > 1 3 5 7 ... 19(ngpios * 2 - 1)
> > > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
> > > ast2600-sgpiom.
> > > * Fix coding style issues.
> > >
> > > Changes from v4:
> > > * Remove ngpios from dtsi
> > > * Add ast2400 and ast2500 platform data.
> > > * Remove unused macros.
> > > * Add ngpios check in a separate patch.
> > > * Fix coding style issues.
> > >
> > > Changes from v3:
> > > * Split dt-bindings patch to 2 patches
> > > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
> > > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
> > > * Correct the typo in commit messages.
> > > * Fix coding style issues.
> > > * Replace all of_*() APIs with device_*().
> > >
> > > Changes from v2:
> > > * Remove maximum/minimum of ngpios from bindings.
> > > * Remove max-ngpios from bindings and dtsi.
> > > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
> > > driver.
> > > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
> > > number of available gpio pins are different.
> > > * Modify functions to pass aspeed_sgpio struct instead of passing
> > > max_ngpios.
> > > * Split sgpio driver patch to 3 patches
> > >
> > > Changes from v1:
> > > * Fix yaml format issues.
> > > * Fix issues reported by kernel test robot.
> > >
> > > Please help to review.
> > >
> > > Thanks,
> > > Steven
> > >
> > > Steven Lee (9):
> > > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
> > > dt-bindings: aspeed-sgpio: Add ast2600 sgpio
> > > ARM: dts: aspeed-g6: Add SGPIO node.
> > > ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
> > > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
> > > gpio: gpio-aspeed-sgpio: Add set_config function
> > > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
> > > gpio: gpio-aspeed-sgpio: Use generic device property APIs
> > > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
> > >
> > > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
> > > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
> > > arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
> > > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
> > > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
> > > 5 files changed, 215 insertions(+), 115 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> > >
> > > --
> > > 2.17.1
> > >
> >
> > The series looks good to me. Can the DTS and GPIO patches go into
> > v5.15 separately?
> >
>
> Hi Bart,
>
> Thanks for the review.
> Shall we do anything to make the patches go into v5.15 or wait for picking-up?
>
> Steven
>
> > Bart
It's more of a question to the relevant SoC maintainers.
Joel, Andrew: can I take the GPIO patches through the GPIO tree and
you'll take the ARM patches separately into v5.15?
Bartosz
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <[email protected]> wrote:
> sgpio-aspeed bindings should be converted to yaml format.
>
> Signed-off-by: Steven Lee <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <[email protected]> wrote:
> AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> with 80 pins. Add ast2600-sgpiom compatibles and update descriptions to
> introduce the max number of available gpio pins that AST2600 supported.
>
> Signed-off-by: Steven Lee <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee <[email protected]> wrote:
> The maximum number of gpio pins of SoC is hardcoded as 80 and the gpio pin
> count mask for GPIO Configuration register is hardcode as GENMASK(9,6).
> However, AST2600 has 2 sgpio master interfaces, one of them supports up
> to 128 gpio pins and pin count mask of GPIO Configuration Register is 5
> bits.
>
> The patch adds ast2600 compatibles, removes MAX_NR_HW_SGPIO and
> corresponding design to make the gpio input/output pin base are determined
> by ngpios.
> The patch also removed hardcoded pin mask and adds ast2400, ast2500,
> ast2600 platform data that include gpio pin count mask for GPIO
> Configuration Register.
>
> The original pin order is as follows:
> (suppose MAX_NR_HW_SGPIO is 80 and ngpios is 10 as well)
> Input:
> 0 1 2 3 ... 9
> Output:
> 80 81 82 ... 89
>
> The new pin order is as follows:
> Input:
> 0 2 4 6 ... 18
> Output:
> 1 3 5 7 ... 19
>
> SGPIO pin id and input/output pin mapping is as follows:
> SGPIO0(0,1), SGPIO1(2,3), ..., SGPIO79(158,159)
>
> For example:
> Access SGPIO5(10,11)
> Get SGPIO pin 5 (suppose sgpio chip id is 2)
> gpioget 2 10
>
> Set SGPIO pin 5 (suppose sgpio chip id is 2)
> gpioset 2 11=1
> gpioset 2 11=0
>
> Signed-off-by: Steven Lee <[email protected]>
Nice use of match data. This is exactly how it shall be done.
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee <[email protected]> wrote:
> AST SoC supports *retain pin state* function when wdt reset.
> The patch adds set_config function for handling sgpio reset tolerance
> register.
>
> Signed-off-by: Steven Lee <[email protected]>
> Reviewed-by: Andrew Jeffery <[email protected]>
Excellent reuse of existing pin config property.
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee <[email protected]> wrote:
> The current design initializes irq->chip from a global irqchip struct,
> which causes multiple sgpio devices use the same irq_chip.
> The patch moves irq_chip to aspeed_sgpio struct for initializing
> irq_chip from their private gpio struct.
>
> Signed-off-by: Steven Lee <[email protected]>
> Reviewed-by: Andrew Jeffery <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee <[email protected]> wrote:
> Add an else-if condition in the probe function to check whether ngpios is
> multiple of 8.
> Per AST datasheet, numbers of available serial GPIO pins in Serial GPIO
> Configuration Register must be n bytes. For instance, if n = 1, it means
> AST SoC supports 8 GPIO pins.
>
> Signed-off-by: Steven Lee <[email protected]>
> Reviewed-by: Andrew Jeffery <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Mon, Jul 12, 2021 at 12:04 PM Steven Lee <[email protected]> wrote:
> Replace all of_property_read_u32() with device_property_read_u32().
>
> Signed-off-by: Steven Lee <[email protected]>
> Acked-by: Andrew Jeffery <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Yours,
Linus Walleij
On Fri, 23 Jul 2021, at 17:00, Bartosz Golaszewski wrote:
> On Fri, Jul 23, 2021 at 5:16 AM Steven Lee <[email protected]> wrote:
> >
> > The 07/21/2021 21:27, Bartosz Golaszewski wrote:
> > > On Mon, Jul 12, 2021 at 12:03 PM Steven Lee <[email protected]> wrote:
> > > >
> > > > AST2600 SoC has 2 SGPIO master interfaces one with 128 pins another one
> > > > with 80 pins, AST2500/AST2400 SoC has 1 SGPIO master interface that
> > > > supports up to 80 pins.
> > > > In the current driver design, the max number of sgpio pins is hardcoded
> > > > in macro MAX_NR_HW_SGPIO and the value is 80.
> > > >
> > > > For supporting sgpio master interfaces of AST2600 SoC, the patch series
> > > > contains the following enhancement:
> > > > - Convert txt dt-bindings to yaml.
> > > > - Update aspeed-g6 dtsi to support the enhanced sgpio.
> > > > - Support muiltiple SGPIO master interfaces.
> > > > - Support up to 128 pins by dts ngpios property.
> > > > - Pair input/output GPIOs instead of using 0 as GPIO input pin base and
> > > > MAX_NR_HW_SGPIO as GPIO output pin base.
> > > > - Support wdt reset tolerance.
> > > > - Fix irq_chip issues which causes multiple sgpio devices use the same
> > > > irq_chip data.
> > > > - Replace all of_*() APIs with device_*().
> > > >
> > > > Changes from v5:
> > > > * Squash v5 patch-05 and patch-06 to one patch.
> > > > * Remove MAX_NR_HW_SGPIO and corresponding design to make the gpio
> > > > input/output pin base are determined by ngpios.
> > > > For example, if MAX_NR_HW_SGPIO is 80 and ngpios is 10, the original
> > > > pin order is as follows:
> > > > Input:
> > > > 0 1 2 3 ... 9
> > > > Output:
> > > > 80 81 82 ... 89
> > > >
> > > > With the new design, pin order is changed as follows:
> > > > Input:
> > > > 0 2 4 6 ... 18(ngpios * 2 - 2)
> > > > Output:
> > > > 1 3 5 7 ... 19(ngpios * 2 - 1)
> > > > * Replace ast2600-sgpiom-128 and ast2600-sgpiom-80 compatibles by
> > > > ast2600-sgpiom.
> > > > * Fix coding style issues.
> > > >
> > > > Changes from v4:
> > > > * Remove ngpios from dtsi
> > > > * Add ast2400 and ast2500 platform data.
> > > > * Remove unused macros.
> > > > * Add ngpios check in a separate patch.
> > > > * Fix coding style issues.
> > > >
> > > > Changes from v3:
> > > > * Split dt-bindings patch to 2 patches
> > > > * Rename ast2600-sgpiom1 compatible with ast2600-sgiom-128
> > > > * Rename ast2600-sgpiom2 compatible with ast2600-sgiom-80
> > > > * Correct the typo in commit messages.
> > > > * Fix coding style issues.
> > > > * Replace all of_*() APIs with device_*().
> > > >
> > > > Changes from v2:
> > > > * Remove maximum/minimum of ngpios from bindings.
> > > > * Remove max-ngpios from bindings and dtsi.
> > > > * Remove ast2400-sgpiom and ast2500-sgpiom compatibles from dts and
> > > > driver.
> > > > * Add ast2600-sgpiom1 and ast2600-sgpiom2 compatibles as their max
> > > > number of available gpio pins are different.
> > > > * Modify functions to pass aspeed_sgpio struct instead of passing
> > > > max_ngpios.
> > > > * Split sgpio driver patch to 3 patches
> > > >
> > > > Changes from v1:
> > > > * Fix yaml format issues.
> > > > * Fix issues reported by kernel test robot.
> > > >
> > > > Please help to review.
> > > >
> > > > Thanks,
> > > > Steven
> > > >
> > > > Steven Lee (9):
> > > > dt-bindings: aspeed-sgpio: Convert txt bindings to yaml.
> > > > dt-bindings: aspeed-sgpio: Add ast2600 sgpio
> > > > ARM: dts: aspeed-g6: Add SGPIO node.
> > > > ARM: dts: aspeed-g5: Remove ngpios from sgpio node.
> > > > gpio: gpio-aspeed-sgpio: Add AST2600 sgpio support
> > > > gpio: gpio-aspeed-sgpio: Add set_config function
> > > > gpio: gpio-aspeed-sgpio: Move irq_chip to aspeed-sgpio struct
> > > > gpio: gpio-aspeed-sgpio: Use generic device property APIs
> > > > gpio: gpio-aspeed-sgpio: Return error if ngpios is not multiple of 8.
> > > >
> > > > .../bindings/gpio/aspeed,sgpio.yaml | 77 ++++++++
> > > > .../devicetree/bindings/gpio/sgpio-aspeed.txt | 46 -----
> > > > arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
> > > > arch/arm/boot/dts/aspeed-g6.dtsi | 28 +++
> > > > drivers/gpio/gpio-aspeed-sgpio.c | 178 +++++++++++-------
> > > > 5 files changed, 215 insertions(+), 115 deletions(-)
> > > > create mode 100644 Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
> > > > delete mode 100644 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
> > > >
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > The series looks good to me. Can the DTS and GPIO patches go into
> > > v5.15 separately?
> > >
> >
> > Hi Bart,
> >
> > Thanks for the review.
> > Shall we do anything to make the patches go into v5.15 or wait for picking-up?
> >
> > Steven
> >
> > > Bart
>
> It's more of a question to the relevant SoC maintainers.
>
> Joel, Andrew: can I take the GPIO patches through the GPIO tree and
> you'll take the ARM patches separately into v5.15?
I think that should be okay. I'll poke Joel.
Andrew
On Tue, 3 Aug 2021 at 04:49, Andrew Jeffery <[email protected]> wrote:
> On Fri, 23 Jul 2021, at 17:00, Bartosz Golaszewski wrote:
> > Joel, Andrew: can I take the GPIO patches through the GPIO tree and
> > you'll take the ARM patches separately into v5.15?
>
> I think that should be okay. I'll poke Joel.
Yes, that's fine. I have merged the first four patches into the aspeed tree.
Cheers,
Joel
On Tue, Aug 3, 2021 at 7:58 AM Joel Stanley <[email protected]> wrote:
>
> On Tue, 3 Aug 2021 at 04:49, Andrew Jeffery <[email protected]> wrote:
> > On Fri, 23 Jul 2021, at 17:00, Bartosz Golaszewski wrote:
> > > Joel, Andrew: can I take the GPIO patches through the GPIO tree and
> > > you'll take the ARM patches separately into v5.15?
> >
> > I think that should be okay. I'll poke Joel.
>
> Yes, that's fine. I have merged the first four patches into the aspeed tree.
>
> Cheers,
>
> Joel
Thanks, I applied patches 5-9 to the GPIO tree.
Bart