2023-09-12 11:37:51

by claudiu beznea

Subject: [PATCH 11/37] clk: renesas: rzg2l: simplify a bit the logic in rzg2l_mod_clock_endisable()

From: Claudiu Beznea <[email protected]>

The bitmask << 16 is anyway set on both branches of if thus move it
before the if and set the lower bits of registers only in case clock is
enabled.

Signed-off-by: Claudiu Beznea <[email protected]>
---
drivers/clk/renesas/rzg2l-cpg.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 44226682db2c..6c289223a4e2 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -914,10 +914,9 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable)
enable ? "ON" : "OFF");
spin_lock_irqsave(&priv->rmw_lock, flags);

+ value = bitmask << 16;
if (enable)
- value = (bitmask << 16) | bitmask;
- else
- value = bitmask << 16;
+ value |= bitmask;
writel(value, priv->base + CLK_ON_R(reg));

spin_unlock_irqrestore(&priv->rmw_lock, flags);
--
2.39.2

2023-09-14 13:08:48

by Geert Uytterhoeven

Subject: Re: [PATCH 11/37] clk: renesas: rzg2l: simplify a bit the logic in rzg2l_mod_clock_endisable()

On Tue, Sep 12, 2023 at 6:52 AM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> The bitmask << 16 is anyway set on both branches of if thus move it
> before the if and set the lower bits of registers only in case clock is
> enabled.
>
> Signed-off-by: Claudiu Beznea <[email protected]>

Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-clk-for-v6.7.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds