From: Marian Mihailescu <[email protected]>
A specific clock rate table is added for VPLL so it is possible
to set frequency of the VPLL output clock that used by the g3d clock.
Cc: Andrzej Hajda <[email protected]>
Cc: Chanwoo Choi <[email protected]>
Signed-off-by: Marian Mihailescu <[email protected]>
Signed-off-by: Anand Moon <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 34cce3c5898f..34156bdfd0d2 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1303,6 +1303,18 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
};
+static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] __initconst = {
+ PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
+ PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
+ PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
+ PLL_35XX_RATE(24 * MHZ, 480000000U, 320, 4, 2),
+ PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
+ PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
+ PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
+ PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
+ PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
+};
+
static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
[apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
APLL_CON0, NULL),
@@ -1428,6 +1440,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
}
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
--
2.17.1
This allows changing the VPLL output frequency through the g3d subsystem
clock tree leaf clocks.
Cc: Andrzej Hajda <[email protected]>
Cc: Chanwoo Choi <[email protected]>
Signed-off-by: Anand Moon <[email protected]>
---
drivers/clk/samsung/clk-exynos5420.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 34156bdfd0d2..6bf1b2e89106 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -647,7 +647,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
- MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
+ MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
+ CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
--
2.17.1
Add missing Netwwork on chip for g3d bus node using VDD_INI
for Exynos542x SoC.
- CLK_DOUT_ACLK_G3D for G3D's AXI
Cc: Chanwoo Choi <[email protected]>
Signed-off-by: Anand Moon <[email protected]>
---
arch/arm/boot/dts/exynos5420.dtsi | 57 +++++++++++++++++--
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 ++
2 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index aaff15880761..bc7203bb1282 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -1047,6 +1047,14 @@
status = "disabled";
};
+ bus_g3d: bus_g3d {
+ compatible = "samsung,exynos-bus";
+ clocks = <&clock CLK_DOUT_ACLK_G3D>;
+ clock-names = "bus";
+ operating-points-v2 = <&bus_g3d_opp_table>;
+ status = "disabled";
+ };
+
bus_jpeg: bus_jpeg {
compatible = "samsung,exynos-bus";
clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
@@ -1245,7 +1253,44 @@
};
};
- bus_jpeg_opp_table: opp_table11 {
+ bus_g3d_opp_table: opp_table11 {
+ compatible = "operating-points-v2";
+
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp@543000000 {
+ opp-hz = /bits/ 64 <543000000>;
+ opp-microvolt = <987500>;
+ };
+ opp@480000000 {
+ opp-hz = /bits/ 64 <480000000>;
+ opp-microvolt = <950000>;
+ };
+ opp@420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <937500>;
+ };
+ opp@350000000 {
+ opp-hz = /bits/ 64 <350000000>;
+ opp-microvolt = <900000>;
+ };
+ opp@266000000 {
+ opp-hz = /bits/ 64 <266000000>;
+ opp-microvolt = <862500>;
+ };
+ opp@177000000 {
+ opp-hz = /bits/ 64 <177000000>;
+ opp-microvolt = <862500>;
+ };
+ opp@100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ opp-microvolt = <862500>;
+ };
+ };
+
+ bus_jpeg_opp_table: opp_table12 {
compatible = "operating-points-v2";
opp00 {
@@ -1262,7 +1307,7 @@
};
};
- bus_jpeg_apb_opp_table: opp_table12 {
+ bus_jpeg_apb_opp_table: opp_table13 {
compatible = "operating-points-v2";
opp00 {
@@ -1279,7 +1324,7 @@
};
};
- bus_disp1_fimd_opp_table: opp_table13 {
+ bus_disp1_fimd_opp_table: opp_table14 {
compatible = "operating-points-v2";
opp00 {
@@ -1290,7 +1335,7 @@
};
};
- bus_disp1_opp_table: opp_table14 {
+ bus_disp1_opp_table: opp_table15 {
compatible = "operating-points-v2";
opp00 {
@@ -1304,7 +1349,7 @@
};
};
- bus_gscl_opp_table: opp_table15 {
+ bus_gscl_opp_table: opp_table16 {
compatible = "operating-points-v2";
opp00 {
@@ -1318,7 +1363,7 @@
};
};
- bus_mscl_opp_table: opp_table16 {
+ bus_mscl_opp_table: opp_table17 {
compatible = "operating-points-v2";
opp00 {
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 2fac4baf1eb4..6e39e4594502 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -89,6 +89,11 @@
status = "okay";
};
+&bus_g3d {
+ devfreq = <&bus_wcore>;
+ status = "okay";
+};
+
&bus_jpeg {
devfreq = <&bus_wcore>;
status = "okay";
--
2.17.1
Hi Anand,
CLK_DOUT_ACLK_G3D is the clock for GPU h/w and it requires the buck4_reg("vdd_g3d").
bus_wcore uses the buck3_reg("vdd_int"). bus_wcore and bus_g3d don't share the
same voltage line. It is wrong to make 'bus_g3d' as the child of 'bus_wcore'
because of using the different regulator.
CLK_DOUT_ACLK_G3D and buck4_reg should be controlled from MALI driver
with DEVFREQ framework. Unfortunately, MALI driver is not posted to mainline.
On 2018년 11월 23일 18:44, Anand Moon wrote:
> Add missing Netwwork on chip for g3d bus node using VDD_INI
> for Exynos542x SoC.
>
> - CLK_DOUT_ACLK_G3D for G3D's AXI
>
> Cc: Chanwoo Choi <[email protected]>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 57 +++++++++++++++++--
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 ++
> 2 files changed, 56 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index aaff15880761..bc7203bb1282 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -1047,6 +1047,14 @@
> status = "disabled";
> };
>
> + bus_g3d: bus_g3d {
> + compatible = "samsung,exynos-bus";
> + clocks = <&clock CLK_DOUT_ACLK_G3D>;
> + clock-names = "bus";
> + operating-points-v2 = <&bus_g3d_opp_table>;
> + status = "disabled";
> + };
> +
> bus_jpeg: bus_jpeg {
> compatible = "samsung,exynos-bus";
> clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
> @@ -1245,7 +1253,44 @@
> };
> };
>
> - bus_jpeg_opp_table: opp_table11 {
> + bus_g3d_opp_table: opp_table11 {
> + compatible = "operating-points-v2";
> +
> + opp@600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <1025000>;
> + };
> + opp@543000000 {
> + opp-hz = /bits/ 64 <543000000>;
> + opp-microvolt = <987500>;
> + };
> + opp@480000000 {
> + opp-hz = /bits/ 64 <480000000>;
> + opp-microvolt = <950000>;
> + };
> + opp@420000000 {
> + opp-hz = /bits/ 64 <420000000>;
> + opp-microvolt = <937500>;
> + };
> + opp@350000000 {
> + opp-hz = /bits/ 64 <350000000>;
> + opp-microvolt = <900000>;
> + };
> + opp@266000000 {
> + opp-hz = /bits/ 64 <266000000>;
> + opp-microvolt = <862500>;
> + };
> + opp@177000000 {
> + opp-hz = /bits/ 64 <177000000>;
> + opp-microvolt = <862500>;
> + };
> + opp@100000000 {
> + opp-hz = /bits/ 64 <100000000>;
> + opp-microvolt = <862500>;
> + };
> + };
> +
> + bus_jpeg_opp_table: opp_table12 {
> compatible = "operating-points-v2";
>
> opp00 {
> @@ -1262,7 +1307,7 @@
> };
> };
>
> - bus_jpeg_apb_opp_table: opp_table12 {
> + bus_jpeg_apb_opp_table: opp_table13 {
> compatible = "operating-points-v2";
>
> opp00 {
> @@ -1279,7 +1324,7 @@
> };
> };
>
> - bus_disp1_fimd_opp_table: opp_table13 {
> + bus_disp1_fimd_opp_table: opp_table14 {
> compatible = "operating-points-v2";
>
> opp00 {
> @@ -1290,7 +1335,7 @@
> };
> };
>
> - bus_disp1_opp_table: opp_table14 {
> + bus_disp1_opp_table: opp_table15 {
> compatible = "operating-points-v2";
>
> opp00 {
> @@ -1304,7 +1349,7 @@
> };
> };
>
> - bus_gscl_opp_table: opp_table15 {
> + bus_gscl_opp_table: opp_table16 {
> compatible = "operating-points-v2";
>
> opp00 {
> @@ -1318,7 +1363,7 @@
> };
> };
>
> - bus_mscl_opp_table: opp_table16 {
> + bus_mscl_opp_table: opp_table17 {
> compatible = "operating-points-v2";
>
> opp00 {
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index 2fac4baf1eb4..6e39e4594502 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -89,6 +89,11 @@
> status = "okay";
> };
>
> +&bus_g3d {
> + devfreq = <&bus_wcore>;
> + status = "okay";
> +};
> +
> &bus_jpeg {
> devfreq = <&bus_wcore>;
> status = "okay";
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi,
On 2018년 11월 23일 18:44, Anand Moon wrote:
> From: Marian Mihailescu <[email protected]>
>
> A specific clock rate table is added for VPLL so it is possible
> to set frequency of the VPLL output clock that used by the g3d clock.
>
> Cc: Andrzej Hajda <[email protected]>
> Cc: Chanwoo Choi <[email protected]>
> Signed-off-by: Marian Mihailescu <[email protected]>
> Signed-off-by: Anand Moon <[email protected]>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 34cce3c5898f..34156bdfd0d2 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -1303,6 +1303,18 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
> PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
> };
>
> +static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] __initconst = {
> + PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
> + PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
> + PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
> + PLL_35XX_RATE(24 * MHZ, 480000000U, 320, 4, 2),
> + PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
> + PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
> + PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
> + PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
> + PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
> +};
VPLL has the same PMS table with apll/kpll/bpll. You don't need to add new
'exynos5420_vpll_24mhz_tbl' table. Just adding the missing frequency entries
to 'exynos5420_pll2550x_24mhz_tbl' table.
> +
> static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
> [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
> APLL_CON0, NULL),
> @@ -1428,6 +1440,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
> exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
> exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> + exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
> }
>
> samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
Hi Chanwoo,
On Mon, 26 Nov 2018 at 13:08, Chanwoo Choi <[email protected]> wrote:
>
> Hi Anand,
>
> CLK_DOUT_ACLK_G3D is the clock for GPU h/w and it requires the buck4_reg("vdd_g3d").
>
> bus_wcore uses the buck3_reg("vdd_int"). bus_wcore and bus_g3d don't share the
> same voltage line. It is wrong to make 'bus_g3d' as the child of 'bus_wcore'
> because of using the different regulator.
>
> CLK_DOUT_ACLK_G3D and buck4_reg should be controlled from MALI driver
> with DEVFREQ framework. Unfortunately, MALI driver is not posted to mainline.
>
>
Thanks for your clarification, I missed this point. mali gpu is linked
to buck4_reg
Next time I will ask for the expert how to proceed on some changes.
Best Regards
-Anand
Hi Chanwoo,
On Mon, 26 Nov 2018 at 13:18, Chanwoo Choi <[email protected]> wrote:
>
> Hi,
>
> On 2018년 11월 23일 18:44, Anand Moon wrote:
> > From: Marian Mihailescu <[email protected]>
> >
> > A specific clock rate table is added for VPLL so it is possible
> > to set frequency of the VPLL output clock that used by the g3d clock.
> >
> > Cc: Andrzej Hajda <[email protected]>
> > Cc: Chanwoo Choi <[email protected]>
> > Signed-off-by: Marian Mihailescu <[email protected]>
> > Signed-off-by: Anand Moon <[email protected]>
> > ---
> > drivers/clk/samsung/clk-exynos5420.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> > index 34cce3c5898f..34156bdfd0d2 100644
> > --- a/drivers/clk/samsung/clk-exynos5420.c
> > +++ b/drivers/clk/samsung/clk-exynos5420.c
> > @@ -1303,6 +1303,18 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
> > PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
> > };
> >
> > +static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] __initconst = {
> > + PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
> > + PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
> > + PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
> > + PLL_35XX_RATE(24 * MHZ, 480000000U, 320, 4, 2),
> > + PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
> > + PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
> > + PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
> > + PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
> > + PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
> > +};
>
> VPLL has the same PMS table with apll/kpll/bpll. You don't need to add new
> 'exynos5420_vpll_24mhz_tbl' table. Just adding the missing frequency entries
> to 'exynos5420_pll2550x_24mhz_tbl' table.
>
Thanks for your input. I will leave this for the expert to fix this.
> > +
> > static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
> > [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
> > APLL_CON0, NULL),
> > @@ -1428,6 +1440,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
> > exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
> > exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> > exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
> > + exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
> > }
> >
> > samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
> >
>
>
> --
> Best Regards,
> Chanwoo Choi
> Samsung Electronics
Best Regards
-Anand