Hi,
This patchset adds initial rudimentary support for the StarFive
designware mobile storage host controller driver. And this driver will
be used in StarFive's VisionFive 2 board. The main purpose of adding
this driver is to accommodate the ultra-high speed mode of eMMC.
The last patch should be applied after the patchset [1]:
[1] https://lore.kernel.org/all/[email protected]/
Changes v5->v6:
- Rebased to 6.3-rc1.
- Changed file name to starfive,jh7110.yaml.
- Modified commit description.
- Added syscon node dts patch to other dependent modules.
Changes v4->v5:
- Added a incremental updates to fix a bug that prev_err is uninitialized.
- Dropped the merged patches.
- Dropped the dts patch.
- Sorted compatible alphabetically in yaml.
Changes v3->v4:
- Added documentation to describe StarFive System Controller Registers.
- Added aon_syscon and stg_syscon node.
- Fixed some checkpatch errors/warnings.
Changes v2->v3:
- Wraped commit message according to Linux coding style.
- Rephrased the description of the patches.
- Changed the description of syscon regsiter.
- Dropped redundant properties.
Changes v1->v2:
- Renamed the dt-binding 'starfive,jh7110-sdio.yaml' to 'starfive,jh7110-mmc.yaml'.
- Changed the type of 'starfive,syscon' and modify its description.
- Deleted unused head files like '#include <linux/gpio.h>'.
- Added comment for the 'rise_point' and 'fall_point'.
- Changed the API 'num_caps' to 'common_caps'.
- Changed the node name 'sys_syscon' to 'syscon'.
- Changed the node name 'sdio' to 'mmc'.
The patch series is based on v6.3.
William Qiu (2):
dt-bindings: soc: starfive: Add StarFive syscon doc
riscv: dts: starfive: Add syscon node
.../soc/starfive/starfive,jh7110-syscon.yaml | 41 +++++++++++++++++++
MAINTAINERS | 5 +++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++
3 files changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
--
2.34.1
Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc.
Signed-off-by: William Qiu <[email protected]>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index d484ecdf93f7..49dd62276b0d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -362,6 +362,11 @@ i2c2: i2c@10050000 {
status = "disabled";
};
+ stg_syscon: syscon@10240000 {
+ compatible = "starfive,jh7110-stg-syscon", "syscon";
+ reg = <0x0 0x10240000 0x0 0x1000>;
+ };
+
uart3: serial@12000000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x12000000 0x0 0x10000>;
@@ -466,6 +471,11 @@ syscrg: clock-controller@13020000 {
#reset-cells = <1>;
};
+ sys_syscon: syscon@13030000 {
+ compatible = "starfive,jh7110-sys-syscon", "syscon";
+ reg = <0x0 0x13030000 0x0 0x1000>;
+ };
+
sysgpio: pinctrl@13040000 {
compatible = "starfive,jh7110-sys-pinctrl";
reg = <0x0 0x13040000 0x0 0x10000>;
@@ -495,6 +505,11 @@ aoncrg: clock-controller@17000000 {
#reset-cells = <1>;
};
+ aon_syscon: syscon@17010000 {
+ compatible = "starfive,jh7110-aon-syscon", "syscon";
+ reg = <0x0 0x17010000 0x0 0x1000>;
+ };
+
aongpio: pinctrl@17020000 {
compatible = "starfive,jh7110-aon-pinctrl";
reg = <0x0 0x17020000 0x0 0x10000>;
--
2.34.1
Reviewed-by: Conor Dooley <[email protected]>
On Wed, 15 Mar 2023 at 06:58, William Qiu <[email protected]> wrote:
>
> Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc.
>
> Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index d484ecdf93f7..49dd62276b0d 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -362,6 +362,11 @@ i2c2: i2c@10050000 {
> status = "disabled";
> };
>
> + stg_syscon: syscon@10240000 {
> + compatible = "starfive,jh7110-stg-syscon", "syscon";
> + reg = <0x0 0x10240000 0x0 0x1000>;
> + };
> +
> uart3: serial@12000000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x0 0x12000000 0x0 0x10000>;
> @@ -466,6 +471,11 @@ syscrg: clock-controller@13020000 {
> #reset-cells = <1>;
> };
>
> + sys_syscon: syscon@13030000 {
> + compatible = "starfive,jh7110-sys-syscon", "syscon";
> + reg = <0x0 0x13030000 0x0 0x1000>;
> + };
> +
> sysgpio: pinctrl@13040000 {
> compatible = "starfive,jh7110-sys-pinctrl";
> reg = <0x0 0x13040000 0x0 0x10000>;
> @@ -495,6 +505,11 @@ aoncrg: clock-controller@17000000 {
> #reset-cells = <1>;
> };
>
> + aon_syscon: syscon@17010000 {
> + compatible = "starfive,jh7110-aon-syscon", "syscon";
> + reg = <0x0 0x17010000 0x0 0x1000>;
> + };
> +
> aongpio: pinctrl@17020000 {
> compatible = "starfive,jh7110-aon-pinctrl";
> reg = <0x0 0x17020000 0x0 0x10000>;
> --
> 2.34.1
>