This short patch series adds the ability to sample the interrupted
machine state for each hardware sample.
To test this patchset,
Eg:
$perf record -I ls // record machine state at interrupt
$perf script -D //read the perf.data file
Sample output obtained for this patchset/ output looks like as follows:
331557004666 0x1988 [0x188]: PERF_RECORD_SAMPLE(IP, 0x1): 4807/4807: 0xc0000000001ddf60 period: 1 addr: 0
... intr regs: mask 0x7ffffffffff ABI 64-bit
.... gpr0 0xc0000000001e6a74
.... gpr1 0xc0000000ff33b9a0
.... gpr2 0xc000000001523000
.... gpr3 0xc000000ffa9deb60
.... gpr4 0xc0000000ff971e00
.... gpr5 0x4d32564532
.... gpr6 0x1e000000
.... gpr7 0x0
.... gpr8 0x0
.... gpr9 0x0
.... gpr10 0x1
.... gpr11 0x0
.... gpr12 0x24022822
.... gpr13 0xc00000000feeaf80
.... gpr14 0x0
.... gpr15 0xc0000000fbc21000
.... gpr16 0x0
.... gpr17 0xc000000ffa9c5000
.... gpr18 0xc0000000ff33b8a0
.... gpr19 0xc000000001523000
.... gpr20 0xc0000000000a097c
.... gpr21 0xc000000fcac65600
.... gpr22 0xc0000000001e55a8
.... gpr23 0xc000000001523000
.... gpr24 0xc0000000ff33b850
.... gpr25 0xc000000fcac65600
.... gpr26 0xc000001e4b378210
.... gpr27 0xfffffffffffffead
.... gpr28 0x100000000
.... gpr29 0xc000000fcac65600
.... gpr30 0x1
.... gpr31 0x0
.... nip 0xc0000000001ddf68
.... msr 0x9000000000009032
.... orig_r3 0xc0000000001e5fcc
.... ctr 0xc00000000009e1b0
.... link 0xc0000000001e6a74
.... xer 0x0
.... ccr 0x84022882
.... softe 0x0
.... trap 0xf01
.... dar 0x0
.... dsisr 0xf00040060000004
... thread: :4807:4807
...... dso: /root/.debug/.build-id/1c/011201a1082e91b8449e6dd528f224d7a16535
:4807 4807 331.557004: 1 cycles: c0000000001ddf60 .perf_ctx_unlock (/boot/vmlinux)
0x1b10 [0x188]: event: 9
Changes from V2:
- tools/perf/config/Makefile is moved to the patch tools/perf.
- The patchset is reordered.
- perf_regs_load() function is used for the dwarf unwind test.Since it is not required here,
it is removed from tools/perf/arch/powerpc/include/perf_regs.h
- PERF_REGS_POWERPC_RESULT is removed.
Anju T (3):
perf/powerpc:add ability to sample intr machine state in power
perf/powerpc :add support for sampling intr machine state
tools/perf:Map the ID values with register names
arch/powerpc/Kconfig | 1 +
arch/powerpc/include/uapi/asm/perf_regs.h | 54 +++++++++++++
arch/powerpc/perf/Makefile | 2 +
arch/powerpc/perf/perf_regs.c | 92 ++++++++++++++++++++++
tools/perf/arch/powerpc/include/perf_regs.h | 114 ++++++++++++++++++++++++++++
tools/perf/config/Makefile | 5 ++
6 files changed, 268 insertions(+)
create mode 100644 arch/powerpc/include/uapi/asm/perf_regs.h
create mode 100644 arch/powerpc/perf/perf_regs.c
create mode 100644 tools/perf/arch/powerpc/include/perf_regs.h
--
2.1.0
The enum definition assigns an 'id' to each register in "struct pt_regs"
of arch/powerpc.The order of these values in the enum definition are
based on the corresponding macros in
arch/powerpc/include/uapi/asm/ptrace.h .
Signed-off-by: Anju T <[email protected]>
---
arch/powerpc/include/uapi/asm/perf_regs.h | 54 +++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
create mode 100644 arch/powerpc/include/uapi/asm/perf_regs.h
diff --git a/arch/powerpc/include/uapi/asm/perf_regs.h b/arch/powerpc/include/uapi/asm/perf_regs.h
new file mode 100644
index 0000000..30fb601
--- /dev/null
+++ b/arch/powerpc/include/uapi/asm/perf_regs.h
@@ -0,0 +1,54 @@
+#ifndef _ASM_POWERPC_PERF_REGS_H
+#define _ASM_POWERPC_PERF_REGS_H
+
+enum perf_event_powerpc_regs {
+ PERF_REG_POWERPC_GPR0,
+ PERF_REG_POWERPC_GPR1,
+ PERF_REG_POWERPC_GPR2,
+ PERF_REG_POWERPC_GPR3,
+ PERF_REG_POWERPC_GPR4,
+ PERF_REG_POWERPC_GPR5,
+ PERF_REG_POWERPC_GPR6,
+ PERF_REG_POWERPC_GPR7,
+ PERF_REG_POWERPC_GPR8,
+ PERF_REG_POWERPC_GPR9,
+ PERF_REG_POWERPC_GPR10,
+ PERF_REG_POWERPC_GPR11,
+ PERF_REG_POWERPC_GPR12,
+ PERF_REG_POWERPC_GPR13,
+ PERF_REG_POWERPC_GPR14,
+ PERF_REG_POWERPC_GPR15,
+ PERF_REG_POWERPC_GPR16,
+ PERF_REG_POWERPC_GPR17,
+ PERF_REG_POWERPC_GPR18,
+ PERF_REG_POWERPC_GPR19,
+ PERF_REG_POWERPC_GPR20,
+ PERF_REG_POWERPC_GPR21,
+ PERF_REG_POWERPC_GPR22,
+ PERF_REG_POWERPC_GPR23,
+ PERF_REG_POWERPC_GPR24,
+ PERF_REG_POWERPC_GPR25,
+ PERF_REG_POWERPC_GPR26,
+ PERF_REG_POWERPC_GPR27,
+ PERF_REG_POWERPC_GPR28,
+ PERF_REG_POWERPC_GPR29,
+ PERF_REG_POWERPC_GPR30,
+ PERF_REG_POWERPC_GPR31,
+ PERF_REG_POWERPC_NIP,
+ PERF_REG_POWERPC_MSR,
+ PERF_REG_POWERPC_ORIG_R3,
+ PERF_REG_POWERPC_CTR,
+ PERF_REG_POWERPC_LNK,
+ PERF_REG_POWERPC_XER,
+ PERF_REG_POWERPC_CCR,
+#ifdef __powerpc64__
+ PERF_REG_POWERPC_SOFTE,
+#else
+ PERF_REG_POWERPC_MQ,
+#endif
+ PERF_REG_POWERPC_TRAP,
+ PERF_REG_POWERPC_DAR,
+ PERF_REG_POWERPC_DSISR,
+ PERF_REG_POWERPC_MAX,
+};
+#endif /* _ASM_POWERPC_PERF_REGS_H */
--
2.1.0
The perf infrastructure uses a bit mask to find out
valid registers to display. Define a register mask
for supported registers defined in asm/perf_regs.h.
The bit positions also correspond to register IDs
which is used by perf infrastructure to fetch the register
values.CONFIG_HAVE_PERF_REGS enables
sampling of the interrupted machine state.
Signed-off-by: Anju T <[email protected]>
---
arch/powerpc/Kconfig | 1 +
arch/powerpc/perf/Makefile | 2 +
arch/powerpc/perf/perf_regs.c | 92 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 95 insertions(+)
create mode 100644 arch/powerpc/perf/perf_regs.c
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 9a7057e..c4ce60d 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -119,6 +119,7 @@ config PPC
select GENERIC_ATOMIC64 if PPC32
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select HAVE_PERF_EVENTS
+ select HAVE_PERF_REGS
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
select ARCH_WANT_IPC_PARSE_VERSION
diff --git a/arch/powerpc/perf/Makefile b/arch/powerpc/perf/Makefile
index f9c083a..cbae78a 100644
--- a/arch/powerpc/perf/Makefile
+++ b/arch/powerpc/perf/Makefile
@@ -7,6 +7,8 @@ obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \
power5+-pmu.o power6-pmu.o power7-pmu.o \
power8-pmu.o
obj32-$(CONFIG_PPC_PERF_CTRS) += mpc7450-pmu.o
+obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
+
obj-$(CONFIG_FSL_EMB_PERF_EVENT) += core-fsl-emb.o
obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500) += e500-pmu.o e6500-pmu.o
diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
new file mode 100644
index 0000000..0520492
--- /dev/null
+++ b/arch/powerpc/perf/perf_regs.c
@@ -0,0 +1,92 @@
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/perf_event.h>
+#include <linux/bug.h>
+#include <linux/stddef.h>
+#include <asm/ptrace.h>
+#include <asm/perf_regs.h>
+
+#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
+
+#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))
+
+static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR3, gpr[3]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR4, gpr[4]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR5, gpr[5]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR6, gpr[6]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR7, gpr[7]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR8, gpr[8]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR9, gpr[9]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR10, gpr[10]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR11, gpr[11]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR12, gpr[12]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR13, gpr[13]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR14, gpr[14]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR15, gpr[15]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR16, gpr[16]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR17, gpr[17]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR18, gpr[18]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR19, gpr[19]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR20, gpr[20]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR21, gpr[21]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR22, gpr[22]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR23, gpr[23]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR24, gpr[24]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR25, gpr[25]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR26, gpr[26]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR27, gpr[27]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR28, gpr[28]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR29, gpr[29]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR30, gpr[30]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_GPR31, gpr[31]),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_NIP, nip),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_MSR, msr),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_ORIG_R3, orig_gpr3),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_CTR, ctr),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_LNK, link),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_XER, xer),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_CCR, ccr),
+#ifdef __powerpc64__
+ PT_REGS_OFFSET(PERF_REG_POWERPC_SOFTE, softe),
+#else
+ PT_REGS_OFFSET(PERF_REG_POWERPC_MQ, mq),
+#endif
+ PT_REGS_OFFSET(PERF_REG_POWERPC_TRAP, trap),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_DAR, dar),
+ PT_REGS_OFFSET(PERF_REG_POWERPC_DSISR, dsisr),
+};
+
+u64 perf_reg_value(struct pt_regs *regs, int idx)
+{
+ if (WARN_ON_ONCE(idx >= PERF_REG_POWERPC_MAX))
+ return 0;
+ return regs_get_register(regs, pt_regs_offset[idx]);
+}
+
+int perf_reg_validate(u64 mask)
+{
+ if (!mask || mask & REG_RESERVED)
+ return -EINVAL;
+ return 0;
+}
+
+u64 perf_reg_abi(struct task_struct *task)
+{
+ return PERF_SAMPLE_REGS_ABI_64;
+}
+
+void perf_get_regs_user(struct perf_regs *regs_user,
+ struct pt_regs *regs,
+ struct pt_regs *regs_user_copy)
+{
+ /*
+ *TODO : Update this function when
+ *PERF_SAMPLE_REGS_USER is enabled
+ */
+ return;
+}
--
2.1.0
Map ID values with corresponding register names.These names are then
displayed when user issues perf record with the -I option
followed by perf report/script with -D option.
Signed-off-by: Anju T <[email protected]>
---
tools/perf/arch/powerpc/include/perf_regs.h | 114 ++++++++++++++++++++++++++++
tools/perf/config/Makefile | 5 ++
2 files changed, 119 insertions(+)
create mode 100644 tools/perf/arch/powerpc/include/perf_regs.h
diff --git a/tools/perf/arch/powerpc/include/perf_regs.h b/tools/perf/arch/powerpc/include/perf_regs.h
new file mode 100644
index 0000000..47307ca
--- /dev/null
+++ b/tools/perf/arch/powerpc/include/perf_regs.h
@@ -0,0 +1,114 @@
+#ifndef ARCH_PERF_REGS_H
+#define ARCH_PERF_REGS_H
+
+#include <stdlib.h>
+#include <linux/types.h>
+#include <asm/perf_regs.h>
+
+#define PERF_REGS_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1)
+#define PERF_REGS_MAX PERF_REG_POWERPC_MAX
+#define PERF_SAMPLE_REGS_ABI PERF_SAMPLE_REGS_ABI_64
+
+#define PERF_REG_IP PERF_REG_POWERPC_NIP
+#define PERF_REG_SP PERF_REG_POWERPC_R1
+
+static inline const char *perf_reg_name(int id)
+{
+ switch (id) {
+ case PERF_REG_POWERPC_GPR0:
+ return "gpr0";
+ case PERF_REG_POWERPC_GPR1:
+ return "gpr1";
+ case PERF_REG_POWERPC_GPR2:
+ return "gpr2";
+ case PERF_REG_POWERPC_GPR3:
+ return "gpr3";
+ case PERF_REG_POWERPC_GPR4:
+ return "gpr4";
+ case PERF_REG_POWERPC_GPR5:
+ return "gpr5";
+ case PERF_REG_POWERPC_GPR6:
+ return "gpr6";
+ case PERF_REG_POWERPC_GPR7:
+ return "gpr7";
+ case PERF_REG_POWERPC_GPR8:
+ return "gpr8";
+ case PERF_REG_POWERPC_GPR9:
+ return "gpr9";
+ case PERF_REG_POWERPC_GPR10:
+ return "gpr10";
+ case PERF_REG_POWERPC_GPR11:
+ return "gpr11";
+ case PERF_REG_POWERPC_GPR12:
+ return "gpr12";
+ case PERF_REG_POWERPC_GPR13:
+ return "gpr13";
+ case PERF_REG_POWERPC_GPR14:
+ return "gpr14";
+ case PERF_REG_POWERPC_GPR15:
+ return "gpr15";
+ case PERF_REG_POWERPC_GPR16:
+ return "gpr16";
+ case PERF_REG_POWERPC_GPR17:
+ return "gpr17";
+ case PERF_REG_POWERPC_GPR18:
+ return "gpr18";
+ case PERF_REG_POWERPC_GPR19:
+ return "gpr19";
+ case PERF_REG_POWERPC_GPR20:
+ return "gpr20";
+ case PERF_REG_POWERPC_GPR21:
+ return "gpr21";
+ case PERF_REG_POWERPC_GPR22:
+ return "gpr22";
+ case PERF_REG_POWERPC_GPR23:
+ return "gpr23";
+ case PERF_REG_POWERPC_GPR24:
+ return "gpr24";
+ case PERF_REG_POWERPC_GPR25:
+ return "gpr25";
+ case PERF_REG_POWERPC_GPR26:
+ return "gpr26";
+ case PERF_REG_POWERPC_GPR27:
+ return "gpr27";
+ case PERF_REG_POWERPC_GPR28:
+ return "gpr28";
+ case PERF_REG_POWERPC_GPR29:
+ return "gpr29";
+ case PERF_REG_POWERPC_GPR30:
+ return "gpr30";
+ case PERF_REG_POWERPC_GPR31:
+ return "gpr31";
+ case PERF_REG_POWERPC_NIP:
+ return "nip";
+ case PERF_REG_POWERPC_MSR:
+ return "msr";
+ case PERF_REG_POWERPC_ORIG_R3:
+ return "orig_r3";
+ case PERF_REG_POWERPC_CTR:
+ return "ctr";
+ case PERF_REG_POWERPC_LNK:
+ return "link";
+ case PERF_REG_POWERPC_XER:
+ return "xer";
+ case PERF_REG_POWERPC_CCR:
+ return "ccr";
+#ifdef __powerpc64__
+ case PERF_REG_POWERPC_SOFTE:
+ return "softe";
+#else
+ case PERF_REG_POWERPC_MQ:
+ return "mq";
+#endif
+ case PERF_REG_POWERPC_TRAP:
+ return "trap";
+ case PERF_REG_POWERPC_DAR:
+ return "dar";
+ case PERF_REG_POWERPC_DSISR:
+ return "dsisr";
+ default:
+ return NULL;
+ }
+ return NULL;
+}
+#endif /*ARCH_PERF_REGS_H */
diff --git a/tools/perf/config/Makefile b/tools/perf/config/Makefile
index 38a0853..3db9b5d 100644
--- a/tools/perf/config/Makefile
+++ b/tools/perf/config/Makefile
@@ -23,6 +23,11 @@ $(call detected_var,ARCH)
NO_PERF_REGS := 1
+#Additional ARCH settings for ppc64
+ifeq ($(ARCH),powerpc)
+ NO_PERF_REGS := 0
+endif
+
# Additional ARCH settings for x86
ifeq ($(ARCH),x86)
$(call detected,CONFIG_X86)
--
2.1.0
On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote:
> The perf infrastructure uses a bit mask to find out
> valid registers to display. Define a register mask
> for supported registers defined in asm/perf_regs.h.
> The bit positions also correspond to register IDs
> which is used by perf infrastructure to fetch the register
> values.CONFIG_HAVE_PERF_REGS enables
> sampling of the interrupted machine state.
> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
> new file mode 100644
> index 0000000..0520492
> --- /dev/null
> +++ b/arch/powerpc/perf/perf_regs.c
> @@ -0,0 +1,92 @@
> +#include <linux/errno.h>
> +#include <linux/kernel.h>
> +#include <linux/sched.h>
> +#include <linux/perf_event.h>
> +#include <linux/bug.h>
> +#include <linux/stddef.h>
> +#include <asm/ptrace.h>
> +#include <asm/perf_regs.h>
> +
> +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
> +
> +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))
> +
> +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]),
> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]),
> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]),
<snip>
I realise you're following the example of other architectures, but we have
almost this exact same structure in ptrace.c, see regoffset_table.
It would be really nice if we could share them between ptrace and perf.
cheers
Hi Michael,
On Tuesday 03 November 2015 02:46 PM, Michael Ellerman wrote:
> On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote:
>
>> The perf infrastructure uses a bit mask to find out
>> valid registers to display. Define a register mask
>> for supported registers defined in asm/perf_regs.h.
>> The bit positions also correspond to register IDs
>> which is used by perf infrastructure to fetch the register
>> values.CONFIG_HAVE_PERF_REGS enables
>> sampling of the interrupted machine state.
>> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
>> new file mode 100644
>> index 0000000..0520492
>> --- /dev/null
>> +++ b/arch/powerpc/perf/perf_regs.c
>> @@ -0,0 +1,92 @@
>> +#include <linux/errno.h>
>> +#include <linux/kernel.h>
>> +#include <linux/sched.h>
>> +#include <linux/perf_event.h>
>> +#include <linux/bug.h>
>> +#include <linux/stddef.h>
>> +#include <asm/ptrace.h>
>> +#include <asm/perf_regs.h>
>> +
>> +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
>> +
>> +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))
>> +
>> +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
>> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]),
>> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]),
>> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]),
> <snip>
>
> I realise you're following the example of other architectures, but we have
> almost this exact same structure in ptrace.c, see regoffset_table.
>
> It would be really nice if we could share them between ptrace and perf.
>
> cheers
>
Thank you for reviewing the patch.
That is a great suggestion.
In ptrace.c the structure doesn't include ORIG_R3. So,in that case what
should we do?
Thanks and Regards
Anju
On Tuesday 03 November 2015 02:46 PM, Michael Ellerman wrote:
> On Tue, 2015-11-03 at 11:40 +0530, Anju T wrote:
>
>> The perf infrastructure uses a bit mask to find out
>> valid registers to display. Define a register mask
>> for supported registers defined in asm/perf_regs.h.
>> The bit positions also correspond to register IDs
>> which is used by perf infrastructure to fetch the register
>> values.CONFIG_HAVE_PERF_REGS enables
>> sampling of the interrupted machine state.
>> diff --git a/arch/powerpc/perf/perf_regs.c b/arch/powerpc/perf/perf_regs.c
>> new file mode 100644
>> index 0000000..0520492
>> --- /dev/null
>> +++ b/arch/powerpc/perf/perf_regs.c
>> @@ -0,0 +1,92 @@
>> +#include <linux/errno.h>
>> +#include <linux/kernel.h>
>> +#include <linux/sched.h>
>> +#include <linux/perf_event.h>
>> +#include <linux/bug.h>
>> +#include <linux/stddef.h>
>> +#include <asm/ptrace.h>
>> +#include <asm/perf_regs.h>
>> +
>> +#define PT_REGS_OFFSET(id, r) [id] = offsetof(struct pt_regs, r)
>> +
>> +#define REG_RESERVED (~((1ULL << PERF_REG_POWERPC_MAX) - 1))
>> +
>> +static unsigned int pt_regs_offset[PERF_REG_POWERPC_MAX] = {
>> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR0, gpr[0]),
>> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR1, gpr[1]),
>> + PT_REGS_OFFSET(PERF_REG_POWERPC_GPR2, gpr[2]),
> <snip>
>
> I realise you're following the example of other architectures, but we have
> almost this exact same structure in ptrace.c, see regoffset_table.
That won't work because we want to add more regs to the perf version but
not the ptrace version.
Maddy
> It would be really nice if we could share them between ptrace and perf.
>
> cheers
>
> _______________________________________________
> Linuxppc-dev mailing list
> [email protected]
> https://lists.ozlabs.org/listinfo/linuxppc-dev
On 11/3/15, Anju T <[email protected]> wrote:
> This short patch series adds the ability to sample the interrupted
> machine state for each hardware sample.
>
> To test this patchset,
> Eg:
>
> $perf record -I ls // record machine state at interrupt
> $perf script -D //read the perf.data file
Uncovered the following warning with the series applied. Looks like
that it's not
directly related to your patches but anyway...
[ 507.655197] DEBUG_LOCKS_WARN_ON(!current->hardirqs_enabled)
[ 507.655220] ------------[ cut here ]------------
[ 507.655226] WARNING: at kernel/locking/lockdep.c:3523
[ 507.655230] Modules linked in: ipv6 binfmt_misc ehea
[ 507.655242] CPU: 12 PID: 3746 Comm: ls Tainted: G S
4.3.0-rc3-00103-g3b0e21e-dirty #11
[ 507.655249] task: c0000005b607b290 ti: c0000005b62e8000 task.ti:
c0000005b62e8000
[ 507.655255] NIP: c00000000010c944 LR: c00000000010c940 CTR: c000000000659380
[ 507.655261] REGS: c0000005b62eb5c0 TRAP: 0700 Tainted: G S
(4.3.0-rc3-00103-g3b0e21e-dirty)
[ 507.655266] MSR: 8000000000029032 <SF,EE,ME,IR,DR,RI> CR: 22088422
XER: 0000000e
[ 507.655284] CFAR: c0000000008977c4 SOFTE: 0
GPR00: c00000000010c940 c0000005b62eb840 c00000000102e600 000000000000002f
GPR04: 0000000000000001 c0000000001208d8 0000000000000000 0000000000000001
GPR08: c000000000eee600 c0000005b607b290 0000000000000000 0000000000003fef
GPR12: 0000000042088428 c00000000e956600 00000000001fffff 00003fffd546c4b0
GPR16: 00000000001fffff 0000000000000013 c000000000b198a8 0000000000000000
GPR20: c0000005acbb2f80 c0000005b5c5dd00 00003fffd546c500 0000000000000001
GPR24: c00000000024af54 0000000000000000 0000000000000001 0000000000000001
GPR28: 0000000000000000 0000000000000000 c0000005acbb2ea0 c000000001e0cf78
[ 507.655376] NIP [c00000000010c944] .check_flags.part.36+0xd4/0x240
[ 507.655382] LR [c00000000010c940] .check_flags.part.36+0xd0/0x240
[ 507.655387] Call Trace:
[ 507.655391] [c0000005b62eb840] [c00000000010c940]
.check_flags.part.36+0xd0/0x240 (unreliable)
[ 507.655400] [c0000005b62eb8c0] [c0000000001112b8] .lock_acquire+0x208/0x2a0
[ 507.655407] [c0000005b62eb990] [c00000000024af80] .__might_fault+0xb0/0xf0
[ 507.655415] [c0000005b62eba10] [c0000000004d5d38] .strnlen_user+0x1d8/0x200
[ 507.655422] [c0000005b62ebad0] [c00000000032fa0c]
.load_elf_binary+0x103c/0x1650
[ 507.655430] [c0000005b62ebc10] [c0000000002bac54]
.search_binary_handler+0xc4/0x260
[ 507.655437] [c0000005b62ebcb0] [c0000000002bcd54]
.do_execveat_common.isra.22+0x7d4/0xb40
[ 507.655444] [c0000005b62ebda0] [c0000000002bd4a8] .SyS_execve+0x38/0x50
[ 507.655451] [c0000005b62ebe30] [c00000000000916c] system_call+0x38/0xd0
[ 507.655456] Instruction dump:
[ 507.655461] 419e0034 3d4200e5 392a3280 81290000 2f890000 40fe0020
3c62ffad 3c82ffad
[ 507.655475] 3863c038 38841f88 4878adfd 60000000 <0fe00000> 3c62ffad
38632010 4878ade9
[ 507.655490] ---[ end trace 47284e8c92efaa7e ]---
[ 507.655494] possible reason: unannotated irqs-on.
[ 507.655498] irq event stamp: 2324
[ 507.655501] hardirqs last enabled at (2323): [<c00000000088ed24>]
._raw_spin_unlock_irqrestore+0x54/0xd0
[ 507.655510] hardirqs last disabled at (2324): [<c000000000009924>]
restore_irq_off+0x24/0x28
[ 507.655518] softirqs last enabled at (2184): [<c00000000009cb90>]
.__do_softirq+0x500/0x670
[ 507.655526] softirqs last disabled at (2169): [<c00000000009d198>]
.irq_exit+0xd8/0x120
>
> Sample output obtained for this patchset/ output looks like as follows:
>
> 331557004666 0x1988 [0x188]: PERF_RECORD_SAMPLE(IP, 0x1): 4807/4807:
> 0xc0000000001ddf60 period: 1 addr: 0
> ... intr regs: mask 0x7ffffffffff ABI 64-bit
> .... gpr0 0xc0000000001e6a74
> .... gpr1 0xc0000000ff33b9a0
> .... gpr2 0xc000000001523000
> .... gpr3 0xc000000ffa9deb60
> .... gpr4 0xc0000000ff971e00
> .... gpr5 0x4d32564532
> .... gpr6 0x1e000000
> .... gpr7 0x0
> .... gpr8 0x0
> .... gpr9 0x0
> .... gpr10 0x1
> .... gpr11 0x0
> .... gpr12 0x24022822
> .... gpr13 0xc00000000feeaf80
> .... gpr14 0x0
> .... gpr15 0xc0000000fbc21000
> .... gpr16 0x0
> .... gpr17 0xc000000ffa9c5000
> .... gpr18 0xc0000000ff33b8a0
> .... gpr19 0xc000000001523000
> .... gpr20 0xc0000000000a097c
> .... gpr21 0xc000000fcac65600
> .... gpr22 0xc0000000001e55a8
> .... gpr23 0xc000000001523000
> .... gpr24 0xc0000000ff33b850
> .... gpr25 0xc000000fcac65600
> .... gpr26 0xc000001e4b378210
> .... gpr27 0xfffffffffffffead
> .... gpr28 0x100000000
> .... gpr29 0xc000000fcac65600
> .... gpr30 0x1
> .... gpr31 0x0
> .... nip 0xc0000000001ddf68
> .... msr 0x9000000000009032
> .... orig_r3 0xc0000000001e5fcc
> .... ctr 0xc00000000009e1b0
> .... link 0xc0000000001e6a74
> .... xer 0x0
> .... ccr 0x84022882
> .... softe 0x0
> .... trap 0xf01
> .... dar 0x0
> .... dsisr 0xf00040060000004
> ... thread: :4807:4807
> ...... dso:
> /root/.debug/.build-id/1c/011201a1082e91b8449e6dd528f224d7a16535
> :4807 4807 331.557004: 1 cycles: c0000000001ddf60
> .perf_ctx_unlock (/boot/vmlinux)
>
> 0x1b10 [0x188]: event: 9
>
>
> Changes from V2:
>
> - tools/perf/config/Makefile is moved to the patch tools/perf.
> - The patchset is reordered.
> - perf_regs_load() function is used for the dwarf unwind test.Since it is
> not required here,
> it is removed from tools/perf/arch/powerpc/include/perf_regs.h
> - PERF_REGS_POWERPC_RESULT is removed.
>
>
>
>
>
> Anju T (3):
> perf/powerpc:add ability to sample intr machine state in power
> perf/powerpc :add support for sampling intr machine state
> tools/perf:Map the ID values with register names
>
> arch/powerpc/Kconfig | 1 +
> arch/powerpc/include/uapi/asm/perf_regs.h | 54 +++++++++++++
> arch/powerpc/perf/Makefile | 2 +
> arch/powerpc/perf/perf_regs.c | 92 ++++++++++++++++++++++
> tools/perf/arch/powerpc/include/perf_regs.h | 114
> ++++++++++++++++++++++++++++
> tools/perf/config/Makefile | 5 ++
> 6 files changed, 268 insertions(+)
> create mode 100644 arch/powerpc/include/uapi/asm/perf_regs.h
> create mode 100644 arch/powerpc/perf/perf_regs.c
> create mode 100644 tools/perf/arch/powerpc/include/perf_regs.h
>
> --
> 2.1.0
>
> _______________________________________________
> Linuxppc-dev mailing list
> [email protected]
> https://lists.ozlabs.org/listinfo/linuxppc-dev
Hi Denis,
On Wednesday 04 November 2015 02:26 PM, Denis Kirjanov wrote:
> On 11/3/15, Anju T <[email protected]> wrote:
>> This short patch series adds the ability to sample the interrupted
>> machine state for each hardware sample.
>>
>> To test this patchset,
>> Eg:
>>
>> $perf record -I ls // record machine state at interrupt
>> $perf script -D //read the perf.data file
> Uncovered the following warning with the series applied. Looks like
> that it's not
> directly related to your patches but anyway...
May I know the config you used while testing?
Did this warning appeared on boot time?
Thanks
Anju
>
> [ 507.655197] DEBUG_LOCKS_WARN_ON(!current->hardirqs_enabled)
> [ 507.655220] ------------[ cut here ]------------
> [ 507.655226] WARNING: at kernel/locking/lockdep.c:3523
> [ 507.655230] Modules linked in: ipv6 binfmt_misc ehea
> [ 507.655242] CPU: 12 PID: 3746 Comm: ls Tainted: G S
> 4.3.0-rc3-00103-g3b0e21e-dirty #11
> [ 507.655249] task: c0000005b607b290 ti: c0000005b62e8000 task.ti:
> c0000005b62e8000
> [ 507.655255] NIP: c00000000010c944 LR: c00000000010c940 CTR: c000000000659380
> [ 507.655261] REGS: c0000005b62eb5c0 TRAP: 0700 Tainted: G S
> (4.3.0-rc3-00103-g3b0e21e-dirty)
> [ 507.655266] MSR: 8000000000029032 <SF,EE,ME,IR,DR,RI> CR: 22088422
> XER: 0000000e
> [ 507.655284] CFAR: c0000000008977c4 SOFTE: 0
> GPR00: c00000000010c940 c0000005b62eb840 c00000000102e600 000000000000002f
> GPR04: 0000000000000001 c0000000001208d8 0000000000000000 0000000000000001
> GPR08: c000000000eee600 c0000005b607b290 0000000000000000 0000000000003fef
> GPR12: 0000000042088428 c00000000e956600 00000000001fffff 00003fffd546c4b0
> GPR16: 00000000001fffff 0000000000000013 c000000000b198a8 0000000000000000
> GPR20: c0000005acbb2f80 c0000005b5c5dd00 00003fffd546c500 0000000000000001
> GPR24: c00000000024af54 0000000000000000 0000000000000001 0000000000000001
> GPR28: 0000000000000000 0000000000000000 c0000005acbb2ea0 c000000001e0cf78
> [ 507.655376] NIP [c00000000010c944] .check_flags.part.36+0xd4/0x240
> [ 507.655382] LR [c00000000010c940] .check_flags.part.36+0xd0/0x240
> [ 507.655387] Call Trace:
> [ 507.655391] [c0000005b62eb840] [c00000000010c940]
> .check_flags.part.36+0xd0/0x240 (unreliable)
> [ 507.655400] [c0000005b62eb8c0] [c0000000001112b8] .lock_acquire+0x208/0x2a0
> [ 507.655407] [c0000005b62eb990] [c00000000024af80] .__might_fault+0xb0/0xf0
> [ 507.655415] [c0000005b62eba10] [c0000000004d5d38] .strnlen_user+0x1d8/0x200
> [ 507.655422] [c0000005b62ebad0] [c00000000032fa0c]
> .load_elf_binary+0x103c/0x1650
> [ 507.655430] [c0000005b62ebc10] [c0000000002bac54]
> .search_binary_handler+0xc4/0x260
> [ 507.655437] [c0000005b62ebcb0] [c0000000002bcd54]
> .do_execveat_common.isra.22+0x7d4/0xb40
> [ 507.655444] [c0000005b62ebda0] [c0000000002bd4a8] .SyS_execve+0x38/0x50
> [ 507.655451] [c0000005b62ebe30] [c00000000000916c] system_call+0x38/0xd0
> [ 507.655456] Instruction dump:
> [ 507.655461] 419e0034 3d4200e5 392a3280 81290000 2f890000 40fe0020
> 3c62ffad 3c82ffad
> [ 507.655475] 3863c038 38841f88 4878adfd 60000000 <0fe00000> 3c62ffad
> 38632010 4878ade9
> [ 507.655490] ---[ end trace 47284e8c92efaa7e ]---
> [ 507.655494] possible reason: unannotated irqs-on.
> [ 507.655498] irq event stamp: 2324
> [ 507.655501] hardirqs last enabled at (2323): [<c00000000088ed24>]
> ._raw_spin_unlock_irqrestore+0x54/0xd0
> [ 507.655510] hardirqs last disabled at (2324): [<c000000000009924>]
> restore_irq_off+0x24/0x28
> [ 507.655518] softirqs last enabled at (2184): [<c00000000009cb90>]
> .__do_softirq+0x500/0x670
> [ 507.655526] softirqs last disabled at (2169): [<c00000000009d198>]
> .irq_exit+0xd8/0x120
>
>> Sample output obtained for this patchset/ output looks like as follows:
>>
>> 331557004666 0x1988 [0x188]: PERF_RECORD_SAMPLE(IP, 0x1): 4807/4807:
>> 0xc0000000001ddf60 period: 1 addr: 0
>> ... intr regs: mask 0x7ffffffffff ABI 64-bit
>> .... gpr0 0xc0000000001e6a74
>> .... gpr1 0xc0000000ff33b9a0
>> .... gpr2 0xc000000001523000
>> .... gpr3 0xc000000ffa9deb60
>> .... gpr4 0xc0000000ff971e00
>> .... gpr5 0x4d32564532
>> .... gpr6 0x1e000000
>> .... gpr7 0x0
>> .... gpr8 0x0
>> .... gpr9 0x0
>> .... gpr10 0x1
>> .... gpr11 0x0
>> .... gpr12 0x24022822
>> .... gpr13 0xc00000000feeaf80
>> .... gpr14 0x0
>> .... gpr15 0xc0000000fbc21000
>> .... gpr16 0x0
>> .... gpr17 0xc000000ffa9c5000
>> .... gpr18 0xc0000000ff33b8a0
>> .... gpr19 0xc000000001523000
>> .... gpr20 0xc0000000000a097c
>> .... gpr21 0xc000000fcac65600
>> .... gpr22 0xc0000000001e55a8
>> .... gpr23 0xc000000001523000
>> .... gpr24 0xc0000000ff33b850
>> .... gpr25 0xc000000fcac65600
>> .... gpr26 0xc000001e4b378210
>> .... gpr27 0xfffffffffffffead
>> .... gpr28 0x100000000
>> .... gpr29 0xc000000fcac65600
>> .... gpr30 0x1
>> .... gpr31 0x0
>> .... nip 0xc0000000001ddf68
>> .... msr 0x9000000000009032
>> .... orig_r3 0xc0000000001e5fcc
>> .... ctr 0xc00000000009e1b0
>> .... link 0xc0000000001e6a74
>> .... xer 0x0
>> .... ccr 0x84022882
>> .... softe 0x0
>> .... trap 0xf01
>> .... dar 0x0
>> .... dsisr 0xf00040060000004
>> ... thread: :4807:4807
>> ...... dso:
>> /root/.debug/.build-id/1c/011201a1082e91b8449e6dd528f224d7a16535
>> :4807 4807 331.557004: 1 cycles: c0000000001ddf60
>> .perf_ctx_unlock (/boot/vmlinux)
>>
>> 0x1b10 [0x188]: event: 9
>>
>>
>> Changes from V2:
>>
>> - tools/perf/config/Makefile is moved to the patch tools/perf.
>> - The patchset is reordered.
>> - perf_regs_load() function is used for the dwarf unwind test.Since it is
>> not required here,
>> it is removed from tools/perf/arch/powerpc/include/perf_regs.h
>> - PERF_REGS_POWERPC_RESULT is removed.
>>
>>
>>
>>
>>
>> Anju T (3):
>> perf/powerpc:add ability to sample intr machine state in power
>> perf/powerpc :add support for sampling intr machine state
>> tools/perf:Map the ID values with register names
>>
>> arch/powerpc/Kconfig | 1 +
>> arch/powerpc/include/uapi/asm/perf_regs.h | 54 +++++++++++++
>> arch/powerpc/perf/Makefile | 2 +
>> arch/powerpc/perf/perf_regs.c | 92 ++++++++++++++++++++++
>> tools/perf/arch/powerpc/include/perf_regs.h | 114
>> ++++++++++++++++++++++++++++
>> tools/perf/config/Makefile | 5 ++
>> 6 files changed, 268 insertions(+)
>> create mode 100644 arch/powerpc/include/uapi/asm/perf_regs.h
>> create mode 100644 arch/powerpc/perf/perf_regs.c
>> create mode 100644 tools/perf/arch/powerpc/include/perf_regs.h
>>
>> --
>> 2.1.0
>>
>> _______________________________________________
>>
On 11/6/15, Anju T <[email protected]> wrote:
> Hi Denis,
>
> On Wednesday 04 November 2015 02:26 PM, Denis Kirjanov wrote:
>> On 11/3/15, Anju T <[email protected]> wrote:
>>> This short patch series adds the ability to sample the interrupted
>>> machine state for each hardware sample.
>>>
>>> To test this patchset,
>>> Eg:
>>>
>>> $perf record -I ls // record machine state at interrupt
>>> $perf script -D //read the perf.data file
>> Uncovered the following warning with the series applied. Looks like
>> that it's not
>> directly related to your patches but anyway...
>
> May I know the config you used while testing?
> Did this warning appeared on boot time?
Hi Anju,
This happens when perf record is invoked.
I think you have to enable DEBUG_LOCKDEP
Thanks
>
> Thanks
>
> Anju
>
>>
>> [ 507.655197] DEBUG_LOCKS_WARN_ON(!current->hardirqs_enabled)
>> [ 507.655220] ------------[ cut here ]------------
>> [ 507.655226] WARNING: at kernel/locking/lockdep.c:3523
>> [ 507.655230] Modules linked in: ipv6 binfmt_misc ehea
>> [ 507.655242] CPU: 12 PID: 3746 Comm: ls Tainted: G S
>> 4.3.0-rc3-00103-g3b0e21e-dirty #11
>> [ 507.655249] task: c0000005b607b290 ti: c0000005b62e8000 task.ti:
>> c0000005b62e8000
>> [ 507.655255] NIP: c00000000010c944 LR: c00000000010c940 CTR:
>> c000000000659380
>> [ 507.655261] REGS: c0000005b62eb5c0 TRAP: 0700 Tainted: G S
>> (4.3.0-rc3-00103-g3b0e21e-dirty)
>> [ 507.655266] MSR: 8000000000029032 <SF,EE,ME,IR,DR,RI> CR: 22088422
>> XER: 0000000e
>> [ 507.655284] CFAR: c0000000008977c4 SOFTE: 0
>> GPR00: c00000000010c940 c0000005b62eb840 c00000000102e600
>> 000000000000002f
>> GPR04: 0000000000000001 c0000000001208d8 0000000000000000
>> 0000000000000001
>> GPR08: c000000000eee600 c0000005b607b290 0000000000000000
>> 0000000000003fef
>> GPR12: 0000000042088428 c00000000e956600 00000000001fffff
>> 00003fffd546c4b0
>> GPR16: 00000000001fffff 0000000000000013 c000000000b198a8
>> 0000000000000000
>> GPR20: c0000005acbb2f80 c0000005b5c5dd00 00003fffd546c500
>> 0000000000000001
>> GPR24: c00000000024af54 0000000000000000 0000000000000001
>> 0000000000000001
>> GPR28: 0000000000000000 0000000000000000 c0000005acbb2ea0
>> c000000001e0cf78
>> [ 507.655376] NIP [c00000000010c944] .check_flags.part.36+0xd4/0x240
>> [ 507.655382] LR [c00000000010c940] .check_flags.part.36+0xd0/0x240
>> [ 507.655387] Call Trace:
>> [ 507.655391] [c0000005b62eb840] [c00000000010c940]
>> .check_flags.part.36+0xd0/0x240 (unreliable)
>> [ 507.655400] [c0000005b62eb8c0] [c0000000001112b8]
>> .lock_acquire+0x208/0x2a0
>> [ 507.655407] [c0000005b62eb990] [c00000000024af80]
>> .__might_fault+0xb0/0xf0
>> [ 507.655415] [c0000005b62eba10] [c0000000004d5d38]
>> .strnlen_user+0x1d8/0x200
>> [ 507.655422] [c0000005b62ebad0] [c00000000032fa0c]
>> .load_elf_binary+0x103c/0x1650
>> [ 507.655430] [c0000005b62ebc10] [c0000000002bac54]
>> .search_binary_handler+0xc4/0x260
>> [ 507.655437] [c0000005b62ebcb0] [c0000000002bcd54]
>> .do_execveat_common.isra.22+0x7d4/0xb40
>> [ 507.655444] [c0000005b62ebda0] [c0000000002bd4a8]
>> .SyS_execve+0x38/0x50
>> [ 507.655451] [c0000005b62ebe30] [c00000000000916c]
>> system_call+0x38/0xd0
>> [ 507.655456] Instruction dump:
>> [ 507.655461] 419e0034 3d4200e5 392a3280 81290000 2f890000 40fe0020
>> 3c62ffad 3c82ffad
>> [ 507.655475] 3863c038 38841f88 4878adfd 60000000 <0fe00000> 3c62ffad
>> 38632010 4878ade9
>> [ 507.655490] ---[ end trace 47284e8c92efaa7e ]---
>> [ 507.655494] possible reason: unannotated irqs-on.
>> [ 507.655498] irq event stamp: 2324
>> [ 507.655501] hardirqs last enabled at (2323): [<c00000000088ed24>]
>> ._raw_spin_unlock_irqrestore+0x54/0xd0
>> [ 507.655510] hardirqs last disabled at (2324): [<c000000000009924>]
>> restore_irq_off+0x24/0x28
>> [ 507.655518] softirqs last enabled at (2184): [<c00000000009cb90>]
>> .__do_softirq+0x500/0x670
>> [ 507.655526] softirqs last disabled at (2169): [<c00000000009d198>]
>> .irq_exit+0xd8/0x120
>>
>>> Sample output obtained for this patchset/ output looks like as follows:
>>>
>>> 331557004666 0x1988 [0x188]: PERF_RECORD_SAMPLE(IP, 0x1): 4807/4807:
>>> 0xc0000000001ddf60 period: 1 addr: 0
>>> ... intr regs: mask 0x7ffffffffff ABI 64-bit
>>> .... gpr0 0xc0000000001e6a74
>>> .... gpr1 0xc0000000ff33b9a0
>>> .... gpr2 0xc000000001523000
>>> .... gpr3 0xc000000ffa9deb60
>>> .... gpr4 0xc0000000ff971e00
>>> .... gpr5 0x4d32564532
>>> .... gpr6 0x1e000000
>>> .... gpr7 0x0
>>> .... gpr8 0x0
>>> .... gpr9 0x0
>>> .... gpr10 0x1
>>> .... gpr11 0x0
>>> .... gpr12 0x24022822
>>> .... gpr13 0xc00000000feeaf80
>>> .... gpr14 0x0
>>> .... gpr15 0xc0000000fbc21000
>>> .... gpr16 0x0
>>> .... gpr17 0xc000000ffa9c5000
>>> .... gpr18 0xc0000000ff33b8a0
>>> .... gpr19 0xc000000001523000
>>> .... gpr20 0xc0000000000a097c
>>> .... gpr21 0xc000000fcac65600
>>> .... gpr22 0xc0000000001e55a8
>>> .... gpr23 0xc000000001523000
>>> .... gpr24 0xc0000000ff33b850
>>> .... gpr25 0xc000000fcac65600
>>> .... gpr26 0xc000001e4b378210
>>> .... gpr27 0xfffffffffffffead
>>> .... gpr28 0x100000000
>>> .... gpr29 0xc000000fcac65600
>>> .... gpr30 0x1
>>> .... gpr31 0x0
>>> .... nip 0xc0000000001ddf68
>>> .... msr 0x9000000000009032
>>> .... orig_r3 0xc0000000001e5fcc
>>> .... ctr 0xc00000000009e1b0
>>> .... link 0xc0000000001e6a74
>>> .... xer 0x0
>>> .... ccr 0x84022882
>>> .... softe 0x0
>>> .... trap 0xf01
>>> .... dar 0x0
>>> .... dsisr 0xf00040060000004
>>> ... thread: :4807:4807
>>> ...... dso:
>>> /root/.debug/.build-id/1c/011201a1082e91b8449e6dd528f224d7a16535
>>> :4807 4807 331.557004: 1 cycles:
>>> c0000000001ddf60
>>> .perf_ctx_unlock (/boot/vmlinux)
>>>
>>> 0x1b10 [0x188]: event: 9
>>>
>>>
>>> Changes from V2:
>>>
>>> - tools/perf/config/Makefile is moved to the patch tools/perf.
>>> - The patchset is reordered.
>>> - perf_regs_load() function is used for the dwarf unwind test.Since it
>>> is
>>> not required here,
>>> it is removed from tools/perf/arch/powerpc/include/perf_regs.h
>>> - PERF_REGS_POWERPC_RESULT is removed.
>>>
>>>
>>>
>>>
>>>
>>> Anju T (3):
>>> perf/powerpc:add ability to sample intr machine state in power
>>> perf/powerpc :add support for sampling intr machine state
>>> tools/perf:Map the ID values with register names
>>>
>>> arch/powerpc/Kconfig | 1 +
>>> arch/powerpc/include/uapi/asm/perf_regs.h | 54 +++++++++++++
>>> arch/powerpc/perf/Makefile | 2 +
>>> arch/powerpc/perf/perf_regs.c | 92
>>> ++++++++++++++++++++++
>>> tools/perf/arch/powerpc/include/perf_regs.h | 114
>>> ++++++++++++++++++++++++++++
>>> tools/perf/config/Makefile | 5 ++
>>> 6 files changed, 268 insertions(+)
>>> create mode 100644 arch/powerpc/include/uapi/asm/perf_regs.h
>>> create mode 100644 arch/powerpc/perf/perf_regs.c
>>> create mode 100644 tools/perf/arch/powerpc/include/perf_regs.h
>>>
>>> --
>>> 2.1.0
>>>
>>> _______________________________________________
>>>
>
>