From: Peng Fan <[email protected]>
V2:
Update to use pmc0/pmc1 following hardware naming
This patchset is to add HSRUN mode support.
Patch 1,2 is to add binding doc and dts node
Patch 3 is to support HSRUN mode
Patch 4 is to use wait mode when HSRUN working per hardware state machine requirement.
Peng Fan (4):
dt-bindings: fsl: add i.MX7ULP PMC
ARM: dts: imx7ulp: add pmc node
ARM: imx: imx7ulp: support HSRUN mode
ARM: imx: cpuidle-imx7ulp: Stop mode disallowed when HSRUN
.../arm/freescale/fsl,imx7ulp-pm.yaml | 6 ++++-
arch/arm/boot/dts/imx7ulp.dtsi | 10 ++++++++
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpuidle-imx7ulp.c | 14 ++++++++---
arch/arm/mach-imx/pm-imx7ulp.c | 25 +++++++++++++++++++
5 files changed, 52 insertions(+), 4 deletions(-)
--
2.28.0
From: Peng Fan <[email protected]>
Update fsl,imx7ulp-pm.yaml to include pmc
Signed-off-by: Peng Fan <[email protected]>
---
.../devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
index 3b26040f8f18..28ebaa8b1d1e 100644
--- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
@@ -23,7 +23,11 @@ description: |
properties:
compatible:
- const: fsl,imx7ulp-smc1
+ items:
+ - enum:
+ - fsl,imx7ulp-smc1
+ - fsl,imx7ulp-pmc0
+ - fsl,imx7ulp-pmc1
reg:
maxItems: 1
--
2.28.0
From: Peng Fan <[email protected]>
Add i.MX7ULP pmc node for m4 and a7.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm/boot/dts/imx7ulp.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index b7ea37ad4e55..b02dc4c97fb8 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -286,6 +286,11 @@ pcc2: clock-controller@403f0000 {
assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
};
+ pmc1: pmc1@40400000 {
+ compatible = "fsl,imx7ulp-pmc1";
+ reg = <0x40400000 0x1000>;
+ };
+
smc1: clock-controller@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
@@ -447,6 +452,11 @@ m4aips1: bus@41080000 {
reg = <0x41080000 0x80000>;
ranges;
+ pmc0: pmc0@410a1000 {
+ compatible = "fsl,imx7ulp-pmc0";
+ reg = <0x410a1000 0x1000>;
+ };
+
sim: sim@410a3000 {
compatible = "fsl,imx7ulp-sim", "syscon";
reg = <0x410a3000 0x1000>;
--
2.28.0
From: Peng Fan <[email protected]>
Configure PMPROT to let ARM core could run into HSRUN mode.
In LDO-enabled mode, HSRUN mode is not allowed, so add a check before
configure PMPROT.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm/mach-imx/pm-imx7ulp.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
index 2e756d8191fa..393faf1e8382 100644
--- a/arch/arm/mach-imx/pm-imx7ulp.c
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -11,6 +11,10 @@
#include "common.h"
+#define PMC0_CTRL 0x28
+#define BM_CTRL_LDOEN BIT(31)
+
+#define SMC_PMPROT 0x8
#define SMC_PMCTRL 0x10
#define BP_PMCTRL_PSTOPO 16
#define PSTOPO_PSTOP3 0x3
@@ -25,7 +29,10 @@
#define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM)
#define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM)
+#define BM_PMPROT_AHSRUN BIT(7)
+
static void __iomem *smc1_base;
+static void __iomem *pmc0_base;
int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
{
@@ -65,5 +72,13 @@ void __init imx7ulp_pm_init(void)
of_node_put(np);
WARN_ON(!smc1_base);
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0");
+ pmc0_base = of_iomap(np, 0);
+ WARN_ON(!pmc0_base);
+ of_node_put(np);
+
+ if (!(readl_relaxed(pmc0_base + PMC0_CTRL) & BM_CTRL_LDOEN))
+ writel_relaxed(BM_PMPROT_AHSRUN, smc1_base + SMC_PMPROT);
+
imx7ulp_set_lpm(ULP_PM_RUN);
}
--
2.28.0
From: Peng Fan <[email protected]>
When cpu runs in HSRUN mode, cpuidle is not allowed to run into
Stop mode. So add imx7ulp_get_mode to get thr cpu run mode,
and use WAIT mode instead, when cpu in HSRUN mode.
Signed-off-by: Peng Fan <[email protected]>
---
arch/arm/mach-imx/common.h | 1 +
arch/arm/mach-imx/cpuidle-imx7ulp.c | 14 +++++++++++---
arch/arm/mach-imx/pm-imx7ulp.c | 10 ++++++++++
3 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 72c3fcc32910..707ac650f1c2 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -103,6 +103,7 @@ void imx6_set_int_mem_clk_lpm(bool enable);
void imx6sl_set_wait_clk(bool enter);
int imx_mmdc_get_ddr_type(void);
int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
+u32 imx7ulp_get_mode(void);
void imx_cpu_die(unsigned int cpu);
int imx_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-imx/cpuidle-imx7ulp.c b/arch/arm/mach-imx/cpuidle-imx7ulp.c
index ca86c967d19e..e7009d10b331 100644
--- a/arch/arm/mach-imx/cpuidle-imx7ulp.c
+++ b/arch/arm/mach-imx/cpuidle-imx7ulp.c
@@ -15,10 +15,18 @@
static int imx7ulp_enter_wait(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index)
{
- if (index == 1)
+ u32 mode;
+
+ if (index == 1) {
imx7ulp_set_lpm(ULP_PM_WAIT);
- else
- imx7ulp_set_lpm(ULP_PM_STOP);
+ } else {
+ mode = imx7ulp_get_mode();
+
+ if (mode == 3)
+ imx7ulp_set_lpm(ULP_PM_WAIT);
+ else
+ imx7ulp_set_lpm(ULP_PM_STOP);
+ }
cpu_do_idle();
diff --git a/arch/arm/mach-imx/pm-imx7ulp.c b/arch/arm/mach-imx/pm-imx7ulp.c
index 393faf1e8382..1410ccfc71bd 100644
--- a/arch/arm/mach-imx/pm-imx7ulp.c
+++ b/arch/arm/mach-imx/pm-imx7ulp.c
@@ -63,6 +63,16 @@ int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
return 0;
}
+u32 imx7ulp_get_mode(void)
+{
+ u32 mode;
+
+ mode = readl_relaxed(smc1_base + SMC_PMCTRL) & BM_PMCTRL_RUNM;
+ mode >>= BP_PMCTRL_RUNM;
+
+ return mode;
+}
+
void __init imx7ulp_pm_init(void)
{
struct device_node *np;
--
2.28.0
> From: Peng Fan <[email protected]>
> Sent: Wednesday, September 16, 2020 10:49 AM
>
> Add i.MX7ULP pmc node for m4 and a7.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> arch/arm/boot/dts/imx7ulp.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
> index b7ea37ad4e55..b02dc4c97fb8 100644
> --- a/arch/arm/boot/dts/imx7ulp.dtsi
> +++ b/arch/arm/boot/dts/imx7ulp.dtsi
> @@ -286,6 +286,11 @@ pcc2: clock-controller@403f0000 {
> assigned-clock-parents = <&scg1
> IMX7ULP_CLK_SOSC_BUS_CLK>;
> };
>
> + pmc1: pmc1@40400000 {
s/pmc1/pmc
> + compatible = "fsl,imx7ulp-pmc1";
> + reg = <0x40400000 0x1000>;
> + };
> +
> smc1: clock-controller@40410000 {
> compatible = "fsl,imx7ulp-smc1";
> reg = <0x40410000 0x1000>;
> @@ -447,6 +452,11 @@ m4aips1: bus@41080000 {
> reg = <0x41080000 0x80000>;
> ranges;
>
> + pmc0: pmc0@410a1000 {
s/pmc0/pmc
> + compatible = "fsl,imx7ulp-pmc0";
> + reg = <0x410a1000 0x1000>;
> + };
> +
> sim: sim@410a3000 {
> compatible = "fsl,imx7ulp-sim", "syscon";
> reg = <0x410a3000 0x1000>;
> --
> 2.28.0
> From: Peng Fan <[email protected]>
> Sent: Wednesday, September 16, 2020 10:49 AM
>
> Update fsl,imx7ulp-pm.yaml to include pmc
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> .../devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git
> a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
> b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
> index 3b26040f8f18..28ebaa8b1d1e 100644
> --- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
> +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml
> @@ -23,7 +23,11 @@ description: |
>
> properties:
> compatible:
> - const: fsl,imx7ulp-smc1
> + items:
> + - enum:
> + - fsl,imx7ulp-smc1
> + - fsl,imx7ulp-pmc0
> + - fsl,imx7ulp-pmc1
Could you add Description for each of them?
Regards
Aisheng
>
> reg:
> maxItems: 1
> --
> 2.28.0
> From: Peng Fan <[email protected]>
> Sent: Wednesday, September 16, 2020 10:49 AM
>
> Configure PMPROT to let ARM core could run into HSRUN mode.
> In LDO-enabled mode, HSRUN mode is not allowed, so add a check before
> configure PMPROT.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> arch/arm/mach-imx/pm-imx7ulp.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm/mach-imx/pm-imx7ulp.c
> b/arch/arm/mach-imx/pm-imx7ulp.c index 2e756d8191fa..393faf1e8382
> 100644
> --- a/arch/arm/mach-imx/pm-imx7ulp.c
> +++ b/arch/arm/mach-imx/pm-imx7ulp.c
> @@ -11,6 +11,10 @@
>
> #include "common.h"
>
> +#define PMC0_CTRL 0x28
> +#define BM_CTRL_LDOEN BIT(31)
> +
> +#define SMC_PMPROT 0x8
> #define SMC_PMCTRL 0x10
> #define BP_PMCTRL_PSTOPO 16
> #define PSTOPO_PSTOP3 0x3
> @@ -25,7 +29,10 @@
> #define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM)
> #define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM)
>
> +#define BM_PMPROT_AHSRUN BIT(7)
> +
> static void __iomem *smc1_base;
> +static void __iomem *pmc0_base;
>
> int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode) { @@ -65,5 +72,13
> @@ void __init imx7ulp_pm_init(void)
> of_node_put(np);
> WARN_ON(!smc1_base);
>
> + np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-pmc0");
> + pmc0_base = of_iomap(np, 0);
> + WARN_ON(!pmc0_base);
> + of_node_put(np);
> +
> + if (!(readl_relaxed(pmc0_base + PMC0_CTRL) & BM_CTRL_LDOEN))
> + writel_relaxed(BM_PMPROT_AHSRUN, smc1_base + SMC_PMPROT);
When will HSRUN mode be enabled? E.g. RUNM=HSRUN
It seems RUNM will be cleared in the following imx7ulp_set_lpm().
Regards
Aisheng
> +
> imx7ulp_set_lpm(ULP_PM_RUN);
> }
> --
> 2.28.0
> From: Peng Fan <[email protected]>
> Sent: Wednesday, September 16, 2020 10:49 AM
>
> When cpu runs in HSRUN mode, cpuidle is not allowed to run into Stop mode.
> So add imx7ulp_get_mode to get thr cpu run mode, and use WAIT mode
> instead, when cpu in HSRUN mode.
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> arch/arm/mach-imx/common.h | 1 +
> arch/arm/mach-imx/cpuidle-imx7ulp.c | 14 +++++++++++---
> arch/arm/mach-imx/pm-imx7ulp.c | 10 ++++++++++
> 3 files changed, 22 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
> index 72c3fcc32910..707ac650f1c2 100644
> --- a/arch/arm/mach-imx/common.h
> +++ b/arch/arm/mach-imx/common.h
> @@ -103,6 +103,7 @@ void imx6_set_int_mem_clk_lpm(bool enable); void
> imx6sl_set_wait_clk(bool enter); int imx_mmdc_get_ddr_type(void); int
> imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode);
> +u32 imx7ulp_get_mode(void);
>
> void imx_cpu_die(unsigned int cpu);
> int imx_cpu_kill(unsigned int cpu);
> diff --git a/arch/arm/mach-imx/cpuidle-imx7ulp.c
> b/arch/arm/mach-imx/cpuidle-imx7ulp.c
> index ca86c967d19e..e7009d10b331 100644
> --- a/arch/arm/mach-imx/cpuidle-imx7ulp.c
> +++ b/arch/arm/mach-imx/cpuidle-imx7ulp.c
> @@ -15,10 +15,18 @@
> static int imx7ulp_enter_wait(struct cpuidle_device *dev,
> struct cpuidle_driver *drv, int index) {
> - if (index == 1)
> + u32 mode;
> +
> + if (index == 1) {
> imx7ulp_set_lpm(ULP_PM_WAIT);
> - else
> - imx7ulp_set_lpm(ULP_PM_STOP);
> + } else {
> + mode = imx7ulp_get_mode();
> +
> + if (mode == 3)
Can we also put a comment above to ease the code reading?
Otherwise:
Reviewed-by: Dong Aisheng <[email protected]>
Regards
Aisheng
> + imx7ulp_set_lpm(ULP_PM_WAIT);
> + else
> + imx7ulp_set_lpm(ULP_PM_STOP);
> + }
>
> cpu_do_idle();
>
> diff --git a/arch/arm/mach-imx/pm-imx7ulp.c
> b/arch/arm/mach-imx/pm-imx7ulp.c index 393faf1e8382..1410ccfc71bd
> 100644
> --- a/arch/arm/mach-imx/pm-imx7ulp.c
> +++ b/arch/arm/mach-imx/pm-imx7ulp.c
> @@ -63,6 +63,16 @@ int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
> return 0;
> }
>
> +u32 imx7ulp_get_mode(void)
> +{
> + u32 mode;
> +
> + mode = readl_relaxed(smc1_base + SMC_PMCTRL) & BM_PMCTRL_RUNM;
> + mode >>= BP_PMCTRL_RUNM;
> +
> + return mode;
> +}
> +
> void __init imx7ulp_pm_init(void)
> {
> struct device_node *np;
> --
> 2.28.0
Hi Peng,
On Tue, Sep 15, 2020 at 11:55 PM <[email protected]> wrote:
>
> From: Peng Fan <[email protected]>
>
> V2:
> Update to use pmc0/pmc1 following hardware naming
>
> This patchset is to add HSRUN mode support.
> Patch 1,2 is to add binding doc and dts node
> Patch 3 is to support HSRUN mode
> Patch 4 is to use wait mode when HSRUN working per hardware state machine requirement.
>
> Peng Fan (4):
> dt-bindings: fsl: add i.MX7ULP PMC
> ARM: dts: imx7ulp: add pmc node
> ARM: imx: imx7ulp: support HSRUN mode
> ARM: imx: cpuidle-imx7ulp: Stop mode disallowed when HSRUN
It seems that a patch adding the 720MHz HSRUN operational point in
imx7ulp.dtsi is missing.
Thanks