In case USXGMII is being used as the PHY interface mode then USXGMII
autoneg must be enabled as well.
HW defaults to USXGMII autoneg being disabled which then results in
autoneg timeout, so enable it in case USXGMII is used.
Signed-off-by: Robert Marko <[email protected]>
---
drivers/net/phy/aquantia/aquantia_main.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/net/phy/aquantia/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c
index 7711e052e737..c602873052a0 100644
--- a/drivers/net/phy/aquantia/aquantia_main.c
+++ b/drivers/net/phy/aquantia/aquantia_main.c
@@ -26,6 +26,9 @@
#define PHY_ID_AQR412 0x03a1b712
#define PHY_ID_AQR113C 0x31c31c12
+#define MDIO_PHYXS_XAUI_RX_VEND2 0xc441
+#define MDIO_PHYXS_XAUI_RX_VEND2_USX_AUTONEG_EN BIT(3)
+
#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
@@ -545,6 +548,15 @@ static int aqr107_config_init(struct phy_device *phydev)
aqr107_validate_mode(phydev, phydev->interface);
+ if (phydev->interface == PHY_INTERFACE_MODE_USXGMII) {
+ ret = phy_modify_mmd(phydev, MDIO_MMD_PHYXS,
+ MDIO_PHYXS_XAUI_RX_VEND2,
+ MDIO_PHYXS_XAUI_RX_VEND2_USX_AUTONEG_EN,
+ MDIO_PHYXS_XAUI_RX_VEND2_USX_AUTONEG_EN);
+ if (ret)
+ return ret;
+ }
+
return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
}
--
2.42.0
On Fri, Nov 17, 2023 at 11:09:49AM +0100, Robert Marko wrote:
> In case USXGMII is being used as the PHY interface mode then USXGMII
> autoneg must be enabled as well.
>
> HW defaults to USXGMII autoneg being disabled which then results in
> autoneg timeout, so enable it in case USXGMII is used.
I was led to believe that the bitfield in bits 8:7 of the
VEND1_GLOBAL_CFG_* registers, when set to value '1' is something
to do with selecting USXGMII mode as opposed to 10GBASE-R. Could
you look in to that and whether that is the more correct way of
configuring the PHY for USXGMII mode?
Thanks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
On Fri, 17 Nov 2023 at 13:47, Russell King (Oracle)
<[email protected]> wrote:
>
> On Fri, Nov 17, 2023 at 11:09:49AM +0100, Robert Marko wrote:
> > In case USXGMII is being used as the PHY interface mode then USXGMII
> > autoneg must be enabled as well.
> >
> > HW defaults to USXGMII autoneg being disabled which then results in
> > autoneg timeout, so enable it in case USXGMII is used.
>
> I was led to believe that the bitfield in bits 8:7 of the
> VEND1_GLOBAL_CFG_* registers, when set to value '1' is something
> to do with selecting USXGMII mode as opposed to 10GBASE-R. Could
> you look in to that and whether that is the more correct way of
> configuring the PHY for USXGMII mode?
Hi,
bits 8:7 in the VEND1_GLOBAL_CFG_* are used to configure the rate
adaptation method.
With the following allowed values:
0 (Default) = No rate adaptation
1 = USX rate adaptation
2 = Pause rate adaptation
I dont think that is related to the issue I am facing here which is
that by default
Bit 3 in the PHY XS Transmit (XAUI Rx) Reserved Vendor Provisioning 2 register
is set to 0.
This means that USX Autoneg Control For MAC is disabled and in USXGMII mode
auto-negotiation between the PHY and MAC will fail/timeout.
I have checked various vendor drivers and they all enable this bit in
case USXGMII
is used.
Regards,
Robert
>
> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!