Quoting Tomer Maimon (2023-12-18 09:04:04)
> diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> new file mode 100644
> index 000000000000..e6c5111cc255
> --- /dev/null
> +++ b/drivers/clk/clk-npcm8xx.c
> @@ -0,0 +1,552 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Nuvoton NPCM8xx Clock Generator
> + * All the clocks are initialized by the bootloader, so this driver allows only
> + * reading of current settings directly from the hardware.
> + *
> + * Copyright (C) 2020 Nuvoton Technologies
> + * Author: Tomer Maimon <[email protected]>
> + */
> +
> +#define pr_fmt(fmt) "npcm8xx_clk: " fmt
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk-provider.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/regmap.h>
[...]
> +#define NPCM8XX_CLK_S_CLKOUT "clkout"
> +#define NPCM8XX_CLK_S_PRE_ADC "pre adc"
> +#define NPCM8XX_CLK_S_UART "uart"
> +#define NPCM8XX_CLK_S_UART2 "uart2"
> +#define NPCM8XX_CLK_S_TIMER "timer"
> +#define NPCM8XX_CLK_S_MMC "mmc"
> +#define NPCM8XX_CLK_S_SDHC "sdhc"
> +#define NPCM8XX_CLK_S_ADC "adc"
> +#define NPCM8XX_CLK_S_GFX "gfx0_gfx1_mem"
> +#define NPCM8XX_CLK_S_USBIF "serial_usbif"
> +#define NPCM8XX_CLK_S_USB_HOST "usb_host"
> +#define NPCM8XX_CLK_S_USB_BRIDGE "usb_bridge"
> +#define NPCM8XX_CLK_S_PCI "pci"
> +#define NPCM8XX_CLK_S_TH "th"
> +#define NPCM8XX_CLK_S_ATB "atb"
> +#define NPCM8XX_CLK_S_PRE_CLK "pre_clk"
> +#define NPCM8XX_CLK_S_RG "rg"
> +#define NPCM8XX_CLK_S_RCP "rcp"
> +
> +static struct clk_hw hw_pll1_div2, hw_pll2_div2, hw_gfx_div2, hw_pre_clk;
> +static struct npcm8xx_clk_pll_data npcm8xx_pll_clks[] = {
> + { NPCM8XX_CLK_S_PLL0, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON0, 0 },
This is a new driver, so please stop using .name in clk_parent_data
structures.
> + { NPCM8XX_CLK_S_PLL1, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON1, 0 },
> + { NPCM8XX_CLK_S_PLL2, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON2, 0 },
> + { NPCM8XX_CLK_S_PLL_GFX, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCONG, 0 },
> +};
> +
> +static const u32 cpuck_mux_table[] = { 0, 1, 2, 7 };
> +static const struct clk_parent_data cpuck_mux_parents[] = {
> + { .hw = &npcm8xx_pll_clks[0].hw },
> + { .hw = &npcm8xx_pll_clks[1].hw },
> + { .index = 0 },
This requires a binding update. As of today, there isn't a 'clocks'
property for the nuvoton,npcm845-clk binding.
> + { .hw = &npcm8xx_pll_clks[2].hw }
> +};
> +
> +static const u32 pixcksel_mux_table[] = { 0, 2 };
> +static const struct clk_parent_data pixcksel_mux_parents[] = {
> + { .hw = &npcm8xx_pll_clks[3].hw },
> + { .index = 0 }
> +};
> +
[...]
> +
> +/* configurable dividers: */
> +static struct npcm8xx_clk_div_data npcm8xx_divs[] = {
> + { NPCM8XX_CLKDIV1, 28, 3, NPCM8XX_CLK_S_ADC, &npcm8xx_pre_divs[0].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_ADC },
> + { NPCM8XX_CLKDIV1, 16, 5, NPCM8XX_CLK_S_UART, &npcm8xx_muxes[3].hw, 0, 0, NPCM8XX_CLK_UART },
> + { NPCM8XX_CLKDIV1, 11, 5, NPCM8XX_CLK_S_MMC, &npcm8xx_muxes[2].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_MMC },
> + { NPCM8XX_CLKDIV1, 6, 5, NPCM8XX_CLK_S_SPI3, &npcm8xx_pre_divs[1].hw, 0, 0, NPCM8XX_CLK_SPI3 },
> + { NPCM8XX_CLKDIV1, 2, 4, NPCM8XX_CLK_S_PCI, &npcm8xx_muxes[7].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PCI },
> +
> + { NPCM8XX_CLKDIV2, 30, 2, NPCM8XX_CLK_S_APB4, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB4 },
> + { NPCM8XX_CLKDIV2, 28, 2, NPCM8XX_CLK_S_APB3, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB3 },
> + { NPCM8XX_CLKDIV2, 26, 2, NPCM8XX_CLK_S_APB2, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB2 },
> + { NPCM8XX_CLKDIV2, 24, 2, NPCM8XX_CLK_S_APB1, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB1 },
> + { NPCM8XX_CLKDIV2, 22, 2, NPCM8XX_CLK_S_APB5, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB5 },
> + { NPCM8XX_CLKDIV2, 16, 5, NPCM8XX_CLK_S_CLKOUT, &npcm8xx_muxes[8].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_CLKOUT },
> + { NPCM8XX_CLKDIV2, 13, 3, NPCM8XX_CLK_S_GFX, &npcm8xx_muxes[7].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_GFX },
> + { NPCM8XX_CLKDIV2, 8, 5, NPCM8XX_CLK_S_USB_BRIDGE, &npcm8xx_muxes[4].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU },
Just put the string where there are any macros that are used once
please.
> + { NPCM8XX_CLKDIV2, 4, 4, NPCM8XX_CLK_S_USB_HOST, &npcm8xx_muxes[4].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU48 },
> + { NPCM8XX_CLKDIV2, 0, 4, NPCM8XX_CLK_S_SDHC, &npcm8xx_muxes[2].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SDHC },
> +
> + { NPCM8XX_CLKDIV3, 16, 8, NPCM8XX_CLK_S_SPI1, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI1 },
> + { NPCM8XX_CLKDIV3, 11, 5, NPCM8XX_CLK_S_UART2, &npcm8xx_muxes[3].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART2 },
> + { NPCM8XX_CLKDIV3, 6, 5, NPCM8XX_CLK_S_SPI0, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI0 },
> + { NPCM8XX_CLKDIV3, 1, 5, NPCM8XX_CLK_S_SPIX, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPIX },
> +
> + { NPCM8XX_CLKDIV4, 28, 4, NPCM8XX_CLK_S_RG, &npcm8xx_muxes[11].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RG },
> + { NPCM8XX_CLKDIV4, 12, 4, NPCM8XX_CLK_S_RCP, &npcm8xx_muxes[12].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RCP },
> +
> + { NPCM8XX_THRTL_CNT, 0, 2, NPCM8XX_CLK_S_TH, &npcm8xx_muxes[0].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_TH },
> +};
> +
[...]
> +
> +static int npcm8xx_clk_probe(struct platform_device *pdev)
> +{
> + struct clk_hw_onecell_data *npcm8xx_clk_data;
> + struct device_node *np = pdev->dev.of_node;
> + struct device *dev = &pdev->dev;
> + struct regmap *clk_regmap;
> + struct clk_hw *hw;
> + unsigned int i;
> +
> + npcm8xx_clk_data = devm_kzalloc(dev, struct_size(npcm8xx_clk_data, hws,
> + NPCM8XX_NUM_CLOCKS),
> + GFP_KERNEL);
> + if (!npcm8xx_clk_data)
> + return -ENOMEM;
> +
> + clk_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sysclk");
I don't see this as part of the binding either. Please update the
binding.
> + if (IS_ERR(clk_regmap)) {
> + dev_err(&pdev->dev, "Failed to find nuvoton,sysclk\n");
> + return PTR_ERR(clk_regmap);
> + }
> +
> + npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> +
> + for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> + npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> +
> + /* Register plls */
Hi Stephen,
Thanks for your comments
On Thu, 21 Dec 2023 at 00:09, Stephen Boyd <[email protected]> wrote:
>
> Quoting Tomer Maimon (2023-12-18 09:04:04)
> > diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> > new file mode 100644
> > index 000000000000..e6c5111cc255
> > --- /dev/null
> > +++ b/drivers/clk/clk-npcm8xx.c
> > @@ -0,0 +1,552 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Nuvoton NPCM8xx Clock Generator
> > + * All the clocks are initialized by the bootloader, so this driver allows only
> > + * reading of current settings directly from the hardware.
> > + *
> > + * Copyright (C) 2020 Nuvoton Technologies
> > + * Author: Tomer Maimon <[email protected]>
> > + */
> > +
> > +#define pr_fmt(fmt) "npcm8xx_clk: " fmt
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/clk-provider.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/regmap.h>
> [...]
> > +#define NPCM8XX_CLK_S_CLKOUT "clkout"
> > +#define NPCM8XX_CLK_S_PRE_ADC "pre adc"
> > +#define NPCM8XX_CLK_S_UART "uart"
> > +#define NPCM8XX_CLK_S_UART2 "uart2"
> > +#define NPCM8XX_CLK_S_TIMER "timer"
> > +#define NPCM8XX_CLK_S_MMC "mmc"
> > +#define NPCM8XX_CLK_S_SDHC "sdhc"
> > +#define NPCM8XX_CLK_S_ADC "adc"
> > +#define NPCM8XX_CLK_S_GFX "gfx0_gfx1_mem"
> > +#define NPCM8XX_CLK_S_USBIF "serial_usbif"
> > +#define NPCM8XX_CLK_S_USB_HOST "usb_host"
> > +#define NPCM8XX_CLK_S_USB_BRIDGE "usb_bridge"
> > +#define NPCM8XX_CLK_S_PCI "pci"
> > +#define NPCM8XX_CLK_S_TH "th"
> > +#define NPCM8XX_CLK_S_ATB "atb"
> > +#define NPCM8XX_CLK_S_PRE_CLK "pre_clk"
> > +#define NPCM8XX_CLK_S_RG "rg"
> > +#define NPCM8XX_CLK_S_RCP "rcp"
> > +
> > +static struct clk_hw hw_pll1_div2, hw_pll2_div2, hw_gfx_div2, hw_pre_clk;
> > +static struct npcm8xx_clk_pll_data npcm8xx_pll_clks[] = {
> > + { NPCM8XX_CLK_S_PLL0, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON0, 0 },
>
> This is a new driver, so please stop using .name in clk_parent_data
> structures.
A few versions ago you suggested defining the reference clock in the
device tree,Can I use .fw_name since the reference clock in the device
tree
refclk: refclk-25mhz {
compatible = "fixed-clock";
clock-output-names = "refclk";
clock-frequency = <25000000>;
#clock-cells = <0>;
};
clk: clock-controller@f0801000 {
compatible = "nuvoton,npcm845-clk";
nuvoton,sysclk = <&rst>;
#clock-cells = <1>;
clocks = <&refclk>;
clock-names = "refclk";
};
I will make sure to add refclk-25mhz to NPCM8xx device tree.
>
> > + { NPCM8XX_CLK_S_PLL1, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON1, 0 },
> > + { NPCM8XX_CLK_S_PLL2, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON2, 0 },
> > + { NPCM8XX_CLK_S_PLL_GFX, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCONG, 0 },
> > +};
> > +
> > +static const u32 cpuck_mux_table[] = { 0, 1, 2, 7 };
> > +static const struct clk_parent_data cpuck_mux_parents[] = {
> > + { .hw = &npcm8xx_pll_clks[0].hw },
> > + { .hw = &npcm8xx_pll_clks[1].hw },
> > + { .index = 0 },
>
> This requires a binding update. As of today, there isn't a 'clocks'
> property for the nuvoton,npcm845-clk binding.
Can I use fw_name = NPCM8XX_CLK_S_REFCLK instead of .index = 0 in
that way, I will not need to modify nuvoton,npcm845-clk binding.
>
> > + { .hw = &npcm8xx_pll_clks[2].hw }
> > +};
> > +
> > +static const u32 pixcksel_mux_table[] = { 0, 2 };
> > +static const struct clk_parent_data pixcksel_mux_parents[] = {
> > + { .hw = &npcm8xx_pll_clks[3].hw },
> > + { .index = 0 }
> > +};
> > +
> [...]
> > +
> > +/* configurable dividers: */
> > +static struct npcm8xx_clk_div_data npcm8xx_divs[] = {
> > + { NPCM8XX_CLKDIV1, 28, 3, NPCM8XX_CLK_S_ADC, &npcm8xx_pre_divs[0].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_ADC },
> > + { NPCM8XX_CLKDIV1, 16, 5, NPCM8XX_CLK_S_UART, &npcm8xx_muxes[3].hw, 0, 0, NPCM8XX_CLK_UART },
> > + { NPCM8XX_CLKDIV1, 11, 5, NPCM8XX_CLK_S_MMC, &npcm8xx_muxes[2].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_MMC },
> > + { NPCM8XX_CLKDIV1, 6, 5, NPCM8XX_CLK_S_SPI3, &npcm8xx_pre_divs[1].hw, 0, 0, NPCM8XX_CLK_SPI3 },
> > + { NPCM8XX_CLKDIV1, 2, 4, NPCM8XX_CLK_S_PCI, &npcm8xx_muxes[7].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_PCI },
> > +
> > + { NPCM8XX_CLKDIV2, 30, 2, NPCM8XX_CLK_S_APB4, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB4 },
> > + { NPCM8XX_CLKDIV2, 28, 2, NPCM8XX_CLK_S_APB3, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB3 },
> > + { NPCM8XX_CLKDIV2, 26, 2, NPCM8XX_CLK_S_APB2, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB2 },
> > + { NPCM8XX_CLKDIV2, 24, 2, NPCM8XX_CLK_S_APB1, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB1 },
> > + { NPCM8XX_CLKDIV2, 22, 2, NPCM8XX_CLK_S_APB5, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_APB5 },
> > + { NPCM8XX_CLKDIV2, 16, 5, NPCM8XX_CLK_S_CLKOUT, &npcm8xx_muxes[8].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_CLKOUT },
> > + { NPCM8XX_CLKDIV2, 13, 3, NPCM8XX_CLK_S_GFX, &npcm8xx_muxes[7].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_GFX },
> > + { NPCM8XX_CLKDIV2, 8, 5, NPCM8XX_CLK_S_USB_BRIDGE, &npcm8xx_muxes[4].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU },
>
> Just put the string where there are any macros that are used once
> please.
O.K.
>
> > + { NPCM8XX_CLKDIV2, 4, 4, NPCM8XX_CLK_S_USB_HOST, &npcm8xx_muxes[4].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SU48 },
> > + { NPCM8XX_CLKDIV2, 0, 4, NPCM8XX_CLK_S_SDHC, &npcm8xx_muxes[2].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SDHC },
> > +
> > + { NPCM8XX_CLKDIV3, 16, 8, NPCM8XX_CLK_S_SPI1, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI1 },
> > + { NPCM8XX_CLKDIV3, 11, 5, NPCM8XX_CLK_S_UART2, &npcm8xx_muxes[3].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_UART2 },
> > + { NPCM8XX_CLKDIV3, 6, 5, NPCM8XX_CLK_S_SPI0, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPI0 },
> > + { NPCM8XX_CLKDIV3, 1, 5, NPCM8XX_CLK_S_SPIX, &npcm8xx_pre_divs[1].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_SPIX },
> > +
> > + { NPCM8XX_CLKDIV4, 28, 4, NPCM8XX_CLK_S_RG, &npcm8xx_muxes[11].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RG },
> > + { NPCM8XX_CLKDIV4, 12, 4, NPCM8XX_CLK_S_RCP, &npcm8xx_muxes[12].hw, CLK_DIVIDER_READ_ONLY, 0, NPCM8XX_CLK_RCP },
> > +
> > + { NPCM8XX_THRTL_CNT, 0, 2, NPCM8XX_CLK_S_TH, &npcm8xx_muxes[0].hw, CLK_DIVIDER_READ_ONLY | CLK_DIVIDER_POWER_OF_TWO, 0, NPCM8XX_CLK_TH },
> > +};
> > +
> [...]
> > +
> > +static int npcm8xx_clk_probe(struct platform_device *pdev)
> > +{
> > + struct clk_hw_onecell_data *npcm8xx_clk_data;
> > + struct device_node *np = pdev->dev.of_node;
> > + struct device *dev = &pdev->dev;
> > + struct regmap *clk_regmap;
> > + struct clk_hw *hw;
> > + unsigned int i;
> > +
> > + npcm8xx_clk_data = devm_kzalloc(dev, struct_size(npcm8xx_clk_data, hws,
> > + NPCM8XX_NUM_CLOCKS),
> > + GFP_KERNEL);
> > + if (!npcm8xx_clk_data)
> > + return -ENOMEM;
> > +
> > + clk_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sysclk");
>
> I don't see this as part of the binding either. Please update the
> binding.
O.K.
>
> > + if (IS_ERR(clk_regmap)) {
> > + dev_err(&pdev->dev, "Failed to find nuvoton,sysclk\n");
> > + return PTR_ERR(clk_regmap);
> > + }
> > +
> > + npcm8xx_clk_data->num = NPCM8XX_NUM_CLOCKS;
> > +
> > + for (i = 0; i < NPCM8XX_NUM_CLOCKS; i++)
> > + npcm8xx_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
> > +
> > + /* Register plls */
Best regards,
Tomer
Quoting Tomer Maimon (2023-12-21 05:43:20)
> Hi Stephen,
>
> Thanks for your comments
>
> On Thu, 21 Dec 2023 at 00:09, Stephen Boyd <[email protected]> wrote:
> >
> > Quoting Tomer Maimon (2023-12-18 09:04:04)
> > > diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> > > new file mode 100644
> > > index 000000000000..e6c5111cc255
> > > --- /dev/null
> > > +++ b/drivers/clk/clk-npcm8xx.c
> > > @@ -0,0 +1,552 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Nuvoton NPCM8xx Clock Generator
> > > + * All the clocks are initialized by the bootloader, so this driver allows only
> > > + * reading of current settings directly from the hardware.
> > > + *
> > > + * Copyright (C) 2020 Nuvoton Technologies
> > > + * Author: Tomer Maimon <[email protected]>
> > > + */
> > > +
> > > +#define pr_fmt(fmt) "npcm8xx_clk: " fmt
> > > +
> > > +#include <linux/bitfield.h>
> > > +#include <linux/clk-provider.h>
> > > +#include <linux/err.h>
> > > +#include <linux/io.h>
> > > +#include <linux/kernel.h>
> > > +#include <linux/module.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/slab.h>
> > > +#include <linux/regmap.h>
> > [...]
> > > +#define NPCM8XX_CLK_S_CLKOUT "clkout"
> > > +#define NPCM8XX_CLK_S_PRE_ADC "pre adc"
> > > +#define NPCM8XX_CLK_S_UART "uart"
> > > +#define NPCM8XX_CLK_S_UART2 "uart2"
> > > +#define NPCM8XX_CLK_S_TIMER "timer"
> > > +#define NPCM8XX_CLK_S_MMC "mmc"
> > > +#define NPCM8XX_CLK_S_SDHC "sdhc"
> > > +#define NPCM8XX_CLK_S_ADC "adc"
> > > +#define NPCM8XX_CLK_S_GFX "gfx0_gfx1_mem"
> > > +#define NPCM8XX_CLK_S_USBIF "serial_usbif"
> > > +#define NPCM8XX_CLK_S_USB_HOST "usb_host"
> > > +#define NPCM8XX_CLK_S_USB_BRIDGE "usb_bridge"
> > > +#define NPCM8XX_CLK_S_PCI "pci"
> > > +#define NPCM8XX_CLK_S_TH "th"
> > > +#define NPCM8XX_CLK_S_ATB "atb"
> > > +#define NPCM8XX_CLK_S_PRE_CLK "pre_clk"
> > > +#define NPCM8XX_CLK_S_RG "rg"
> > > +#define NPCM8XX_CLK_S_RCP "rcp"
> > > +
> > > +static struct clk_hw hw_pll1_div2, hw_pll2_div2, hw_gfx_div2, hw_pre_clk;
> > > +static struct npcm8xx_clk_pll_data npcm8xx_pll_clks[] = {
> > > + { NPCM8XX_CLK_S_PLL0, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON0, 0 },
> >
> > This is a new driver, so please stop using .name in clk_parent_data
> > structures.
> A few versions ago you suggested defining the reference clock in the
> device tree,Can I use .fw_name since the reference clock in the device
> tree
>
> refclk: refclk-25mhz {
> compatible = "fixed-clock";
> clock-output-names = "refclk";
Please don't use clock-output-names property.
> clock-frequency = <25000000>;
> #clock-cells = <0>;
> };
Use of this binding is fine assuming the reference clk is a real thing
that exists outside the SoC. Is it?
>
> clk: clock-controller@f0801000 {
> compatible = "nuvoton,npcm845-clk";
> nuvoton,sysclk = <&rst>;
> #clock-cells = <1>;
> clocks = <&refclk>;
This is index = 0
> clock-names = "refclk";
> };
>
> I will make sure to add refclk-25mhz to NPCM8xx device tree.
> >
> > > + { NPCM8XX_CLK_S_PLL1, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON1, 0 },
> > > + { NPCM8XX_CLK_S_PLL2, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON2, 0 },
> > > + { NPCM8XX_CLK_S_PLL_GFX, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCONG, 0 },
> > > +};
> > > +
> > > +static const u32 cpuck_mux_table[] = { 0, 1, 2, 7 };
> > > +static const struct clk_parent_data cpuck_mux_parents[] = {
> > > + { .hw = &npcm8xx_pll_clks[0].hw },
> > > + { .hw = &npcm8xx_pll_clks[1].hw },
> > > + { .index = 0 },
> >
> > This requires a binding update. As of today, there isn't a 'clocks'
> > property for the nuvoton,npcm845-clk binding.
> Can I use fw_name = NPCM8XX_CLK_S_REFCLK instead of .index = 0 in
> that way, I will not need to modify nuvoton,npcm845-clk binding.
Why don't you want to modify the binding? If you add a clocks property
like in the example above you will have to modify the binding.
Hi Stephen,
Thanks for your clarifications.
On Wed, 3 Jan 2024 at 01:52, Stephen Boyd <[email protected]> wrote:
>
> Quoting Tomer Maimon (2023-12-21 05:43:20)
> > Hi Stephen,
> >
> > Thanks for your comments
> >
> > On Thu, 21 Dec 2023 at 00:09, Stephen Boyd <[email protected]> wrote:
> > >
> > > Quoting Tomer Maimon (2023-12-18 09:04:04)
> > > > diff --git a/drivers/clk/clk-npcm8xx.c b/drivers/clk/clk-npcm8xx.c
> > > > new file mode 100644
> > > > index 000000000000..e6c5111cc255
> > > > --- /dev/null
> > > > +++ b/drivers/clk/clk-npcm8xx.c
> > > > @@ -0,0 +1,552 @@
> > > > +// SPDX-License-Identifier: GPL-2.0
> > > > +/*
> > > > + * Nuvoton NPCM8xx Clock Generator
> > > > + * All the clocks are initialized by the bootloader, so this driver allows only
> > > > + * reading of current settings directly from the hardware.
> > > > + *
> > > > + * Copyright (C) 2020 Nuvoton Technologies
> > > > + * Author: Tomer Maimon <[email protected]>
> > > > + */
> > > > +
> > > > +#define pr_fmt(fmt) "npcm8xx_clk: " fmt
> > > > +
> > > > +#include <linux/bitfield.h>
> > > > +#include <linux/clk-provider.h>
> > > > +#include <linux/err.h>
> > > > +#include <linux/io.h>
> > > > +#include <linux/kernel.h>
> > > > +#include <linux/module.h>
> > > > +#include <linux/platform_device.h>
> > > > +#include <linux/slab.h>
> > > > +#include <linux/regmap.h>
> > > [...]
> > > > +#define NPCM8XX_CLK_S_CLKOUT "clkout"
> > > > +#define NPCM8XX_CLK_S_PRE_ADC "pre adc"
> > > > +#define NPCM8XX_CLK_S_UART "uart"
> > > > +#define NPCM8XX_CLK_S_UART2 "uart2"
> > > > +#define NPCM8XX_CLK_S_TIMER "timer"
> > > > +#define NPCM8XX_CLK_S_MMC "mmc"
> > > > +#define NPCM8XX_CLK_S_SDHC "sdhc"
> > > > +#define NPCM8XX_CLK_S_ADC "adc"
> > > > +#define NPCM8XX_CLK_S_GFX "gfx0_gfx1_mem"
> > > > +#define NPCM8XX_CLK_S_USBIF "serial_usbif"
> > > > +#define NPCM8XX_CLK_S_USB_HOST "usb_host"
> > > > +#define NPCM8XX_CLK_S_USB_BRIDGE "usb_bridge"
> > > > +#define NPCM8XX_CLK_S_PCI "pci"
> > > > +#define NPCM8XX_CLK_S_TH "th"
> > > > +#define NPCM8XX_CLK_S_ATB "atb"
> > > > +#define NPCM8XX_CLK_S_PRE_CLK "pre_clk"
> > > > +#define NPCM8XX_CLK_S_RG "rg"
> > > > +#define NPCM8XX_CLK_S_RCP "rcp"
> > > > +
> > > > +static struct clk_hw hw_pll1_div2, hw_pll2_div2, hw_gfx_div2, hw_pre_clk;
> > > > +static struct npcm8xx_clk_pll_data npcm8xx_pll_clks[] = {
> > > > + { NPCM8XX_CLK_S_PLL0, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON0, 0 },
> > >
> > > This is a new driver, so please stop using .name in clk_parent_data
> > > structures.
> > A few versions ago you suggested defining the reference clock in the
> > device tree,Can I use .fw_name since the reference clock in the device
> > tree
> >
> > refclk: refclk-25mhz {
> > compatible = "fixed-clock";
> > clock-output-names = "refclk";
>
> Please don't use clock-output-names property.
Will remove
>
> > clock-frequency = <25000000>;
> > #clock-cells = <0>;
> > };
>
> Use of this binding is fine assuming the reference clk is a real thing
> that exists outside the SoC. Is it?
Yes it is.
>
> >
> > clk: clock-controller@f0801000 {
> > compatible = "nuvoton,npcm845-clk";
> > nuvoton,sysclk = <&rst>;
> > #clock-cells = <1>;
> > clocks = <&refclk>;
>
> This is index = 0
O.K.
>
> > clock-names = "refclk";
> > };
> >
> > I will make sure to add refclk-25mhz to NPCM8xx device tree.
> > >
> > > > + { NPCM8XX_CLK_S_PLL1, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON1, 0 },
> > > > + { NPCM8XX_CLK_S_PLL2, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCON2, 0 },
> > > > + { NPCM8XX_CLK_S_PLL_GFX, { .name = NPCM8XX_CLK_S_REFCLK }, NPCM8XX_PLLCONG, 0 },
> > > > +};
> > > > +
> > > > +static const u32 cpuck_mux_table[] = { 0, 1, 2, 7 };
> > > > +static const struct clk_parent_data cpuck_mux_parents[] = {
> > > > + { .hw = &npcm8xx_pll_clks[0].hw },
> > > > + { .hw = &npcm8xx_pll_clks[1].hw },
> > > > + { .index = 0 },
> > >
> > > This requires a binding update. As of today, there isn't a 'clocks'
> > > property for the nuvoton,npcm845-clk binding.
> > Can I use fw_name = NPCM8XX_CLK_S_REFCLK instead of .index = 0 in
> > that way, I will not need to modify nuvoton,npcm845-clk binding.
>
> Why don't you want to modify the binding? If you add a clocks property
> like in the example above you will have to modify the binding.
Will add clocks property to nuvoton,npcm845-clk binding.
Thanks,
Tomer