From: Claudiu Beznea <[email protected]>
Hi,
This patch series adds initial support for The Renesas RZ/G3S (R9A08G045{S33})
SoC. The RZ/G3S device is a general-purpose microprocessor with a
single-core Arm® Cortex®-A55 (1.1GHz) and a dual-core Arm® Cortex®-M33 (250MHz),
perfect for an IOT gateway controller.
This includes:
- SoC identification;
- clocks (core clocks, pin controller clock, serial interface, SD ch0
clock) and corresponding resets;
- minimal device tree for SoM and carrier boards.
With this series Linux can boot from eMMC or SD card. The eMMC and uSD
interface are multiplexed on the SoM; selection is made using a hardware
switch.
Patches are gouped as follows:
- 01-04 adds SoC identification support;
- 05 is a simple cleanup on SoC identification support
- 06-09 contain fixes on clock drivers identified while adding RZ/G3S
support
- 10-14 clock cleanups identifies while adding support for RZ/G3S
- 15-22 clock changes needed by RZ/G3S
- 23-30 pinctrl changes needed by RZ/G3S
- 31 document SDHI for RZ/G3S
- 32-37 device tree support for RZ/G3S
Thank you,
Claudiu Beznea
Claudiu Beznea (37):
dt-bindings: serial: renesas,scif: document r9a08g045 support
dt-bindings: soc: renesas: document Renesas RZ/G3S SoC variants
dt-bindings: soc: renesas: renesas,rzg2l-sysc: document RZ/G3S SoC
soc: renesas: identify RZ/G3S SoC
soc: renesas: remove blank lines
clk: renesas: rzg2l: wait for status bit of SD mux before continuing
clk: renesas: rzg2l: lock around writes to mux register
clk: renesas: rzg2l: trust value returned by hardware
clk: renesas: rzg2l: fix computation formula
clk: renesas: rzg2l: use core->name for clock name
clk: renesas: rzg2l: simplify a bit the logic in
rzg2l_mod_clock_endisable()
clk: renesas: rzg2l: reduce the critical area
clk: renesas: rzg2l: use FIELD_GET() for PLL register fields
clk: renesas: rzg2l: use u32 for flag and mux_flags
clk: renesas: rzg2l: add support for RZ/G3S PLL
clk: renesas: rzg2l: add struct clk_hw_data
clk: renesas: rzg2l: remove CPG_SDHI_DSEL from generic header
clk: renesas: rzg2l: refactor sd mux driver
clk: renesas: rzg2l: add a divider clock for RZ/G3S
dt-bindings: clock: renesas,rzg2l-cpg: document RZ/G3S SoC
dt-bindings: clock: add r9a08g045 CPG clocks and resets definitions
clk: renesas: add minimal boot support for RZ/G3S SoC
pinctrl: renesas: rzg2l: index all registers based on port offset
pinctrl: renesas: rzg2l: adapt for different SD/PWPR register offsets
pinctrl: renesas: rzg2l: adapt function number for RZ/G3S
pinctrl: renesas: rzg2l: move ds and oi to SoC specific configuration
pinctrl: renesas: rzg2l: add support for different ds values on
different groups
pinctrl: renesas: rzg2l: make struct
rzg2l_pinctrl_data::dedicated_pins constant
dt-bindings: pinctrl: renesas: document RZ/G3S SoC
pinctrl: renesas: rzg2l: add support for RZ/G3S SoC
dt-bindings: mmc: renesas,sdhi: Document RZ/G3S support
arm64: dts: renesas: add initial DTSI for RZ/G3S SoC
arm64: dts: renesas: rzg3l-smarc-som: add initial support for RZ/G3S
SMARC Carrier-II SoM
arm64: dts: renesas: rzg3s-smarc: add initial device tree for RZ SMARC
Carrier-II Board
dt-bindings: arm: renesas: document SMARC Carrier-II EVK
arm64: dts: renesas: r9a08g045s33-smarc: add initial device tree for
RZ/G3S SMARC EVK board
arm64: defconfig: enable RZ/G3S (R9A08G045) SoC
.../bindings/clock/renesas,rzg2l-cpg.yaml | 1 +
.../devicetree/bindings/mmc/renesas,sdhi.yaml | 2 +
.../pinctrl/renesas,rzg2l-pinctrl.yaml | 26 +-
.../bindings/serial/renesas,scif.yaml | 1 +
.../soc/renesas/renesas,rzg2l-sysc.yaml | 1 +
.../bindings/soc/renesas/renesas.yaml | 8 +
arch/arm64/boot/dts/renesas/Makefile | 2 +
arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 139 ++++
.../boot/dts/renesas/r9a08g045s33-smarc.dts | 17 +
arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 14 +
.../boot/dts/renesas/rzg3s-smarc-som.dtsi | 147 ++++
arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 28 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/Kconfig | 7 +-
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r9a07g043-cpg.c | 19 +-
drivers/clk/renesas/r9a07g044-cpg.c | 19 +-
drivers/clk/renesas/r9a08g045-cpg.c | 217 ++++++
drivers/clk/renesas/rzg2l-cpg.c | 495 ++++++++++--
drivers/clk/renesas/rzg2l-cpg.h | 39 +-
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 728 ++++++++++++++----
drivers/soc/renesas/Kconfig | 6 +
drivers/soc/renesas/renesas-soc.c | 15 +-
include/dt-bindings/clock/r9a08g045-cpg.h | 243 ++++++
24 files changed, 1924 insertions(+), 252 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33-smarc.dts
create mode 100644 arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi
create mode 100644 arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
create mode 100644 drivers/clk/renesas/r9a08g045-cpg.c
create mode 100644 include/dt-bindings/clock/r9a08g045-cpg.h
--
2.39.2
From: Claudiu Beznea <[email protected]>
SD, PWPR power registers have different offsets b/w RZ/G2L and RZ/G3S.
Commit adds a per SoC configuration data structure that is initialized with
proper register offset for individual SoCs. The struct rzg2l_hwcfg will be
further extended in next commits.
Signed-off-by: Claudiu Beznea <[email protected]>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 52 ++++++++++++++++++++-----
1 file changed, 42 insertions(+), 10 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 6efdf4a424fd..8bdf065aa85b 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -98,8 +98,7 @@
#define IOLH(off) (0x1000 + (off) * 8)
#define IEN(off) (0x1800 + (off) * 8)
#define ISEL(off) (0x2C00 + (off) * 8)
-#define PWPR (0x3014)
-#define SD_CH(n) (0x3000 + (n) * 4)
+#define SD_CH(off, ch) ((off) + (ch) * 4)
#define QSPI (0x3008)
#define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
@@ -124,6 +123,24 @@
#define RZG2L_TINT_IRQ_START_INDEX 9
#define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i))
+/**
+ * struct rzg2l_register_offsets - specific register offsets
+ * @pwpr: PWPR register offset
+ * @sd_ch: SD_CH register offset
+ */
+struct rzg2l_register_offsets {
+ u16 pwpr;
+ u16 sd_ch;
+};
+
+/**
+ * struct rzg2l_hwcfg - hardware configuration data structure
+ * @regs: hardware specific register offsets
+ */
+struct rzg2l_hwcfg {
+ const struct rzg2l_register_offsets regs;
+};
+
struct rzg2l_dedicated_configs {
const char *name;
u32 config;
@@ -136,6 +153,7 @@ struct rzg2l_pinctrl_data {
struct rzg2l_dedicated_configs *dedicated_pins;
unsigned int n_port_pins;
unsigned int n_dedicated_pins;
+ const struct rzg2l_hwcfg *hwcfg;
};
struct rzg2l_pinctrl {
@@ -163,6 +181,7 @@ static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 };
static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
u8 pin, u8 off, u8 func)
{
+ const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs;
unsigned long flags;
u32 reg;
@@ -178,8 +197,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
/* Set the PWPR register to allow PFC register to write */
- writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
- writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */
+ writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
+ writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
/* Select Pin function mode with PFC register */
reg = readl(pctrl->base + PFC(off));
@@ -187,8 +206,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
/* Set the PWPR register to be write-protected */
- writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */
- writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */
+ writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
+ writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
/* Switch to Peripheral pin function with PMC register */
reg = readb(pctrl->base + PMC(off));
@@ -528,6 +547,8 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
{
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
enum pin_config_param param = pinconf_to_config_param(*config);
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
+ const struct rzg2l_register_offsets *regs = &hwcfg->regs;
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
unsigned int *pin_data = pin->drv_data;
unsigned int arg = 0;
@@ -563,9 +584,9 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
u32 pwr_reg = 0x0;
if (cfg & PIN_CFG_IO_VMC_SD0)
- pwr_reg = SD_CH(0);
+ pwr_reg = SD_CH(regs->sd_ch, 0);
else if (cfg & PIN_CFG_IO_VMC_SD1)
- pwr_reg = SD_CH(1);
+ pwr_reg = SD_CH(regs->sd_ch, 1);
else if (cfg & PIN_CFG_IO_VMC_QSPI)
pwr_reg = QSPI;
else
@@ -617,6 +638,8 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin];
unsigned int *pin_data = pin->drv_data;
+ const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg;
+ const struct rzg2l_register_offsets *regs = &hwcfg->regs;
enum pin_config_param param;
unsigned long flags;
void __iomem *addr;
@@ -660,9 +683,9 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
return -EINVAL;
if (cfg & PIN_CFG_IO_VMC_SD0)
- pwr_reg = SD_CH(0);
+ pwr_reg = SD_CH(regs->sd_ch, 0);
else if (cfg & PIN_CFG_IO_VMC_SD1)
- pwr_reg = SD_CH(1);
+ pwr_reg = SD_CH(regs->sd_ch, 1);
else if (cfg & PIN_CFG_IO_VMC_QSPI)
pwr_reg = QSPI;
else
@@ -1531,6 +1554,13 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)
return 0;
}
+static const struct rzg2l_hwcfg rzg2l_hwcfg = {
+ .regs = {
+ .pwpr = 0x3014,
+ .sd_ch = 0x3000,
+ },
+};
+
static struct rzg2l_pinctrl_data r9a07g043_data = {
.port_pins = rzg2l_gpio_names,
.port_pin_configs = r9a07g043_gpio_configs,
@@ -1538,6 +1568,7 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.dedicated_pins = rzg2l_dedicated_pins.common,
.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),
+ .hwcfg = &rzg2l_hwcfg,
};
static struct rzg2l_pinctrl_data r9a07g044_data = {
@@ -1548,6 +1579,7 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT,
.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) +
ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins),
+ .hwcfg = &rzg2l_hwcfg,
};
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
--
2.39.2
From: Claudiu Beznea <[email protected]>
Add support to identify the RZ/G3S (R9A08G045) SoC.
Signed-off-by: Claudiu Beznea <[email protected]>
---
drivers/soc/renesas/Kconfig | 6 ++++++
drivers/soc/renesas/renesas-soc.c | 13 +++++++++++++
2 files changed, 19 insertions(+)
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 5a75ab64d1ed..631b17c627a8 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -319,6 +319,12 @@ config ARCH_R9A07G054
help
This enables support for the Renesas RZ/V2L SoC variants.
+config ARCH_R9A08G045
+ bool "ARM64 Platform support for RZ/G3S"
+ select ARCH_RZG2L
+ help
+ This enables support for the Renesas RZ/G3S SoC variants.
+
config ARCH_R9A09G011
bool "ARM64 Platform support for RZ/V2M"
select PM
diff --git a/drivers/soc/renesas/renesas-soc.c b/drivers/soc/renesas/renesas-soc.c
index 42af7c09f743..1598b66ffb51 100644
--- a/drivers/soc/renesas/renesas-soc.c
+++ b/drivers/soc/renesas/renesas-soc.c
@@ -72,6 +72,10 @@ static const struct renesas_family fam_rzg2ul __initconst __maybe_unused = {
.name = "RZ/G2UL",
};
+static const struct renesas_family fam_rzg3s __initconst __maybe_unused = {
+ .name = "RZ/G3S",
+};
+
static const struct renesas_family fam_rzv2l __initconst __maybe_unused = {
.name = "RZ/V2L",
};
@@ -170,6 +174,11 @@ static const struct renesas_soc soc_rz_g2ul __initconst __maybe_unused = {
.id = 0x8450447,
};
+static const struct renesas_soc soc_rz_g3s __initconst __maybe_unused = {
+ .family = &fam_rzg3s,
+ .id = 0x85e0447,
+};
+
static const struct renesas_soc soc_rz_v2l __initconst __maybe_unused = {
.family = &fam_rzv2l,
.id = 0x8447447,
@@ -386,6 +395,9 @@ static const struct of_device_id renesas_socs[] __initconst __maybe_unused = {
#ifdef CONFIG_ARCH_R9A07G054
{ .compatible = "renesas,r9a07g054", .data = &soc_rz_v2l },
#endif
+#ifdef CONFIG_ARCH_R9A08G045
+ { .compatible = "renesas,r9a08g045", .data = &soc_rz_g3s },
+#endif
#ifdef CONFIG_ARCH_R9A09G011
{ .compatible = "renesas,r9a09g011", .data = &soc_rz_v2m },
#endif
@@ -429,6 +441,7 @@ static const struct of_device_id renesas_ids[] __initconst = {
{ .compatible = "renesas,r9a07g043-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g044-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a07g054-sysc", .data = &id_rzg2l },
+ { .compatible = "renesas,r9a08g045-sysc", .data = &id_rzg2l },
{ .compatible = "renesas,r9a09g011-sys", .data = &id_rzv2m },
{ .compatible = "renesas,prr", .data = &id_prr },
{ /* sentinel */ }
--
2.39.2
From: Claudiu Beznea <[email protected]>
SD MUX output (SD0) is further divided by 4 in G2{L, UL}. The divided
clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which
means a rate request for it is propagated to the MUX and could reach
rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0.
Add proper locking to avoid concurrent access on SD MUX set rate
registers.
Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <[email protected]>
---
drivers/clk/renesas/rzg2l-cpg.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 70d1c28ba088..1195d4b1f545 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -189,6 +189,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
u32 shift = GET_SHIFT(hwdata->conf);
const u32 clk_src_266 = 2;
u32 msk, val, bitmask;
+ unsigned long flags;
int ret;
/*
@@ -203,25 +204,27 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
* the index to value mapping is done by adding 1 to the index.
*/
bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
+ spin_lock_irqsave(&priv->rmw_lock, flags);
if (index != clk_src_266) {
writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
- ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
- !(val & msk), 100,
- CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
- if (ret) {
- dev_err(priv->dev, "failed to switch clk source\n");
- return ret;
- }
+ ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
+ !(val & msk), 100,
+ CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+ if (ret)
+ goto unlock;
}
writel(bitmask | ((index + 1) << shift), priv->base + off);
- ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
- !(val & msk), 100,
- CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+ ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
+ !(val & msk), 100,
+ CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
+unlock:
+ spin_unlock_irqrestore(&priv->rmw_lock, flags);
+
if (ret)
dev_err(priv->dev, "failed to switch clk source\n");
--
2.39.2
From: Claudiu Beznea <[email protected]>
Document Renesas SMARC Carrier-II EVK board which is based on RZ/G3S
(R9A08G045) SoC. The SMARC Carrier-II EVK consists of RZ/G3S SoM module and
SMARC Carrier-II carrier board, the SoM module sits on top of carrier
board.
Signed-off-by: Claudiu Beznea <[email protected]>
---
Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
index 822faf081e84..f4964445e5ab 100644
--- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
+++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
@@ -476,6 +476,8 @@ properties:
- description: RZ/G3S (R9A08G045)
items:
+ - enum:
+ - renesas,smarc2-evk # SMARC Carrier-II EVK
- enum:
- renesas,r9a08g045s33 # PCIe support
- const: renesas,r9a08g045
--
2.39.2
Hi Claudiu,
On Wed, Sep 13, 2023 at 7:32 AM claudiu beznea <[email protected]> wrote:
> On 12.09.2023 19:16, Rob Herring wrote:
> > On Tue, Sep 12, 2023 at 07:51:55AM +0300, Claudiu wrote:
> >> From: Claudiu Beznea <[email protected]>
> >>
> >> Document Renesas SMARC Carrier-II EVK board which is based on RZ/G3S
> >> (R9A08G045) SoC. The SMARC Carrier-II EVK consists of RZ/G3S SoM module and
> >> SMARC Carrier-II carrier board, the SoM module sits on top of carrier
> >> board.
> >>
> >> Signed-off-by: Claudiu Beznea <[email protected]>
Thanks for your patch!
> >> --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> >> +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml
> >> @@ -476,6 +476,8 @@ properties:
> >>
> >> - description: RZ/G3S (R9A08G045)
> >> items:
> >> + - enum:
> >> + - renesas,smarc2-evk # SMARC Carrier-II EVK
> >
> > You just changed the existing binding...
> >
> >> - enum:
> >> - renesas,r9a08g045s33 # PCIe support
> >
> > This is the SoM module?
>
> No, this is a SoC variant which supports PCIe.
Ideally, we need a compatible value for the SoM as well, as the SoM
can be used stand-alone, or plugged in a different carrier board.
For iWave Systems RZ/G1E SODIMM, we have that.
For the existing RZ/G2L variants, we forgot, but it can still be added...
>
> > You either need to squash this change or add
> > another case with 3 entries and maintain the 2 entry case. (there's no
> > way to express any entry at the beginning or middle can be optional)
> >
> >> - const: renesas,r9a08g045
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
From: Claudiu Beznea <[email protected]>
Enable config flag for Renesas RZ/G3S (R9A08G045) SoC.
Signed-off-by: Claudiu Beznea <[email protected]>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 5315789f4868..f597ae20959c 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1335,6 +1335,7 @@ CONFIG_ARCH_R8A774B1=y
CONFIG_ARCH_R9A07G043=y
CONFIG_ARCH_R9A07G044=y
CONFIG_ARCH_R9A07G054=y
+CONFIG_ARCH_R9A08G045=y
CONFIG_ARCH_R9A09G011=y
CONFIG_ROCKCHIP_IODOMAIN=y
CONFIG_ROCKCHIP_PM_DOMAINS=y
--
2.39.2
From: Claudiu Beznea <[email protected]>
Document support for the SD Card/MMC interface on the Renesas
RZ/G3S (R9A08G045) SoC.
Signed-off-by: Claudiu Beznea <[email protected]>
---
Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 7756a8687eaf..94e228787630 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -59,6 +59,7 @@ properties:
- renesas,sdhi-r9a07g043 # RZ/G2UL
- renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
- renesas,sdhi-r9a07g054 # RZ/V2L
+ - renesas,sdhi-r9a08g045 # RZ/G3S
- renesas,sdhi-r9a09g011 # RZ/V2M
- const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
- items:
@@ -122,6 +123,7 @@ allOf:
- renesas,sdhi-r9a07g043
- renesas,sdhi-r9a07g044
- renesas,sdhi-r9a07g054
+ - renesas,sdhi-r9a08g045
- renesas,sdhi-r9a09g011
then:
properties:
--
2.39.2
Hi Claudiu,
On Tue, Sep 12, 2023 at 6:52 AM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> SD MUX output (SD0) is further divided by 4 in G2{L, UL}. The divided
> clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which
> means a rate request for it is propagated to the MUX and could reach
> rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0.
> Add proper locking to avoid concurrent access on SD MUX set rate
> registers.
>
> Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
> Signed-off-by: Claudiu Beznea <[email protected]>
Thanks for your patch!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -189,6 +189,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
> u32 shift = GET_SHIFT(hwdata->conf);
> const u32 clk_src_266 = 2;
> u32 msk, val, bitmask;
> + unsigned long flags;
> int ret;
>
> /*
> @@ -203,25 +204,27 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
> * the index to value mapping is done by adding 1 to the index.
> */
> bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
> + spin_lock_irqsave(&priv->rmw_lock, flags);
> if (index != clk_src_266) {
> writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
>
> msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
>
> - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
> - !(val & msk), 100,
> - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
> - if (ret) {
> - dev_err(priv->dev, "failed to switch clk source\n");
> - return ret;
> - }
> + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
> + !(val & msk), 100,
According to the read_poll_timeout_atomic() documentation,
delay_us should be less than ~10us.
> + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US = 20 ms, which is a long timeout
for an atomic poll.
> + if (ret)
> + goto unlock;
> }
>
> writel(bitmask | ((index + 1) << shift), priv->base + off);
>
> - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
> - !(val & msk), 100,
> - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
> + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
> + !(val & msk), 100,
> + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
Likewise.
> +unlock:
> + spin_unlock_irqrestore(&priv->rmw_lock, flags);
> +
> if (ret)
> dev_err(priv->dev, "failed to switch clk source\n");
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, Sep 12, 2023 at 6:52 AM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> Add support to identify the RZ/G3S (R9A08G045) SoC.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
i.e. will queue in renesas-devel for v6.7.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, Sep 12, 2023 at 6:53 AM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> Document support for the SD Card/MMC interface on the Renesas
> RZ/G3S (R9A08G045) SoC.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On Tue, 12 Sept 2023 at 06:53, Claudiu <[email protected]> wrote:
>
> From: Claudiu Beznea <[email protected]>
>
> Document support for the SD Card/MMC interface on the Renesas
> RZ/G3S (R9A08G045) SoC.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
> ---
> Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> index 7756a8687eaf..94e228787630 100644
> --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
> @@ -59,6 +59,7 @@ properties:
> - renesas,sdhi-r9a07g043 # RZ/G2UL
> - renesas,sdhi-r9a07g044 # RZ/G2{L,LC}
> - renesas,sdhi-r9a07g054 # RZ/V2L
> + - renesas,sdhi-r9a08g045 # RZ/G3S
> - renesas,sdhi-r9a09g011 # RZ/V2M
> - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
> - items:
> @@ -122,6 +123,7 @@ allOf:
> - renesas,sdhi-r9a07g043
> - renesas,sdhi-r9a07g044
> - renesas,sdhi-r9a07g054
> + - renesas,sdhi-r9a08g045
> - renesas,sdhi-r9a09g011
> then:
> properties:
> --
> 2.39.2
>
On Tue, Sep 12, 2023 at 6:53 AM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> Enable config flag for Renesas RZ/G3S (R9A08G045) SoC.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
On 14.09.2023 15:13, Geert Uytterhoeven wrote:
> Hi Claudiu,
>
> On Tue, Sep 12, 2023 at 6:52 AM Claudiu <[email protected]> wrote:
>> From: Claudiu Beznea <[email protected]>
>>
>> SD MUX output (SD0) is further divided by 4 in G2{L, UL}. The divided
>> clock is SD0_DIV4. SD0_DIV4 is registered with CLK_SET_RATE_PARENT which
>> means a rate request for it is propagated to the MUX and could reach
>> rzg2l_cpg_sd_clk_mux_set_parent() concurrently with the users of SD0.
>> Add proper locking to avoid concurrent access on SD MUX set rate
>> registers.
>>
>> Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
>> Signed-off-by: Claudiu Beznea <[email protected]>
>
> Thanks for your patch!
>
>> --- a/drivers/clk/renesas/rzg2l-cpg.c
>> +++ b/drivers/clk/renesas/rzg2l-cpg.c
>> @@ -189,6 +189,7 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> u32 shift = GET_SHIFT(hwdata->conf);
>> const u32 clk_src_266 = 2;
>> u32 msk, val, bitmask;
>> + unsigned long flags;
>> int ret;
>>
>> /*
>> @@ -203,25 +204,27 @@ static int rzg2l_cpg_sd_clk_mux_set_parent(struct clk_hw *hw, u8 index)
>> * the index to value mapping is done by adding 1 to the index.
>> */
>> bitmask = (GENMASK(GET_WIDTH(hwdata->conf) - 1, 0) << shift) << 16;
>> + spin_lock_irqsave(&priv->rmw_lock, flags);
>> if (index != clk_src_266) {
>> writel(bitmask | ((clk_src_266 + 1) << shift), priv->base + off);
>>
>> msk = off ? CPG_CLKSTATUS_SELSDHI1_STS : CPG_CLKSTATUS_SELSDHI0_STS;
>>
>> - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
>> - !(val & msk), 100,
>> - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
>> - if (ret) {
>> - dev_err(priv->dev, "failed to switch clk source\n");
>> - return ret;
>> - }
>> + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
>> + !(val & msk), 100,
>
> According to the read_poll_timeout_atomic() documentation,
> delay_us should be less than ~10us.
I'll update it, thanks for pointing it.
>
>> + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
>
> CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US = 20 ms, which is a long timeout
> for an atomic poll.
I'll have to find the the rationale behind the original timeout. It may be
random, experimental or hardware related.
>
>> + if (ret)
>> + goto unlock;
>> }
>>
>> writel(bitmask | ((index + 1) << shift), priv->base + off);
>>
>> - ret = readl_poll_timeout(priv->base + CPG_CLKSTATUS, val,
>> - !(val & msk), 100,
>> - CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
>> + ret = readl_poll_timeout_atomic(priv->base + CPG_CLKSTATUS, val,
>> + !(val & msk), 100,
>> + CPG_SDHI_CLK_SWITCH_STATUS_TIMEOUT_US);
>
> Likewise.
>
>> +unlock:
>> + spin_unlock_irqrestore(&priv->rmw_lock, flags);
>> +
>> if (ret)
>> dev_err(priv->dev, "failed to switch clk source\n");
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
> Geert
>
On Tue, Sep 12, 2023 at 6:53 AM Claudiu <[email protected]> wrote:
> From: Claudiu Beznea <[email protected]>
>
> SD, PWPR power registers have different offsets b/w RZ/G2L and RZ/G3S.
> Commit adds a per SoC configuration data structure that is initialized with
> proper register offset for individual SoCs. The struct rzg2l_hwcfg will be
> further extended in next commits.
>
> Signed-off-by: Claudiu Beznea <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds