Hi,
This patch series implements support for the 2nd connectivity
peripheral block on gs101.
This block contains an additional 6 USI, 1 I3C and 1 PWM
interfaces/busses.
i2cdetect shows all expected devices on the one i2c bus that this patch
series enables.
Everything that's in scope in this series works also without the
clk_ignore_unused kernel command line argument.
While working on this, I noticed the existing peric0 support for gs101
has a couple issues. That explains why there are differences compared
to it and a separate patch series will be sent to fix up peric0
support.
Cheers,
Andre'
.../bindings/clock/google,gs101-clock.yaml | 9 +-
.../soc/samsung/samsung,exynos-sysreg.yaml | 2 +
.../boot/dts/exynos/google/gs101-oriole.dts | 9 +
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 42 ++
drivers/clk/samsung/clk-gs101.c | 347 ++++++++++++++++-
include/dt-bindings/clock/google,gs101.h | 48 +++
Add dt-schema documentation and clock IDs for the Connectivity
Peripheral 1 (PERIC1) clock management unit.
Signed-off-by: André Draszik <[email protected]>
---
Note for future reference: To ensure consistent naming throughout this
file, the IDs have been derived from the data sheet using the
following, with the expectation for all future additions to this file
to use the same:
sed \
-e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|CLK_FOUT_\1_PLL|' \
\
-e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_|CLK_MOUT_\1_|' \
-e 's|^PLL_CON0_PLL_\(.*\)|CLK_MOUT_PLL_\1|' \
-e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|CLK_MOUT_\1|' \
-e '/^PLL_CON[1-4]_[^_]\+_/d' \
-e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
-e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
\
-e 's|_IPCLKPORT||' \
-e 's|_RSTNSYNC||' \
\
-e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_|CLK_DOUT_\1_|' \
\
-e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_|CLK_GOUT_\1_|' \
-e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \
-e 's|^CLK_GOUT_[^_]\+_[^_]\+_CMU_\([^_]\+\)_PCLK$|CLK_GOUT_\1_PCLK|' \
-e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \
-e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|CLK_GOUT_\1_CLK_\1_\2|' \
\
-e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
---
.../bindings/clock/google,gs101-clock.yaml | 9 ++--
include/dt-bindings/clock/google,gs101.h | 48 +++++++++++++++++++
2 files changed, 54 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
index 03698cdecf7a..1d2bcea41c85 100644
--- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -31,6 +31,7 @@ properties:
- google,gs101-cmu-apm
- google,gs101-cmu-misc
- google,gs101-cmu-peric0
+ - google,gs101-cmu-peric1
clocks:
minItems: 1
@@ -93,15 +94,17 @@ allOf:
properties:
compatible:
contains:
- const: google,gs101-cmu-peric0
+ enum:
+ - google,gs101-cmu-peric0
+ - google,gs101-cmu-peric1
then:
properties:
clocks:
items:
- description: External reference clock (24.576 MHz)
- - description: Connectivity Peripheral 0 bus clock (from CMU_TOP)
- - description: Connectivity Peripheral 0 IP clock (from CMU_TOP)
+ - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
+ - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
clock-names:
items:
diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
index 64e6bdc6359c..3dac3577788a 100644
--- a/include/dt-bindings/clock/google,gs101.h
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -470,4 +470,52 @@
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
+/* CMU_PERIC1 */
+#define CLK_MOUT_PERIC1_BUS_USER 1
+#define CLK_MOUT_PERIC1_I3C_USER 2
+#define CLK_MOUT_PERIC1_USI0_USI_USER 3
+#define CLK_MOUT_PERIC1_USI10_USI_USER 4
+#define CLK_MOUT_PERIC1_USI11_USI_USER 5
+#define CLK_MOUT_PERIC1_USI12_USI_USER 6
+#define CLK_MOUT_PERIC1_USI13_USI_USER 7
+#define CLK_MOUT_PERIC1_USI9_USI_USER 8
+#define CLK_DOUT_PERIC1_I3C 9
+#define CLK_DOUT_PERIC1_USI0_USI 10
+#define CLK_DOUT_PERIC1_USI10_USI 11
+#define CLK_DOUT_PERIC1_USI11_USI 12
+#define CLK_DOUT_PERIC1_USI12_USI 13
+#define CLK_DOUT_PERIC1_USI13_USI 14
+#define CLK_DOUT_PERIC1_USI9_USI 15
+#define CLK_GOUT_PERIC1_IP 16
+#define CLK_GOUT_PERIC1_PCLK 17
+#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18
+#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19
+#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20
+#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21
+#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22
+#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37
+#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38
+#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44
+#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
+#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.43.0.429.g432eaa2c6b-goog
Enable the cmu-peric1 clock controller. It feeds additional USI, I3C
and PWM interfaces / busses.
Signed-off-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index aaac04df5e65..5088c81fd6aa 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -429,6 +429,16 @@ serial_0: serial@10a00000 {
};
};
+ cmu_peric1: clock-controller@10c00000 {
+ compatible = "google,gs101-cmu-peric1";
+ reg = <0x10c00000 0x4000>;
+ #clock-cells = <1>;
+ clocks = <&ext_24_5m>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
+ clock-names = "oscclk", "bus", "ip";
+ };
+
sysreg_peric1: syscon@10c20000 {
compatible = "google,gs101-peric1-sysreg", "syscon";
reg = <0x10c20000 0x10000>;
--
2.43.0.429.g432eaa2c6b-goog
On the gs101-oriole board, i2c bus 12 has various USB-related
controllers attached to it.
Note the selection of the USI protocol is intentionally left for the
board dts file.
Signed-off-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 30 ++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 5088c81fd6aa..d66590fa922f 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -450,6 +450,36 @@ pinctrl_peric1: pinctrl@10c40000 {
interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ usi12: usi@10d500c0 {
+ compatible = "google,gs101-usi",
+ "samsung,exynos850-usi";
+ reg = <0x10d500c0 0x20>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>,
+ <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>;
+ clock-names = "pclk", "ipclk";
+ samsung,sysreg = <&sysreg_peric1 0x1010>;
+ samsung,mode = <USI_V2_NONE>;
+ status = "disabled";
+
+ hsi2c_12: i2c@10d50000 {
+ compatible = "google,gs101-hsi2c",
+ "samsung,exynosautov9-hsi2c";
+ reg = <0x10d50000 0xc0>;
+ interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsi2c12_bus>;
+ clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>,
+ <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+ };
+
pinctrl_hsi1: pinctrl@11840000 {
compatible = "google,gs101-pinctrl";
reg = <0x11840000 0x00001000>;
--
2.43.0.429.g432eaa2c6b-goog
Now that we have hooked it up in the DTS, we can drop the
CLK_IGNORE_UNUSED from here.
Signed-off-by: André Draszik <[email protected]>
---
drivers/clk/samsung/clk-gs101.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 7f6c3b52d9ff..d55ed64d0e29 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -3393,7 +3393,7 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
"gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
- 21, CLK_IGNORE_UNUSED, 0),
+ 21, 0, 0),
};
static const struct samsung_cmu_info peric1_cmu_info __initconst = {
--
2.43.0.429.g432eaa2c6b-goog
Without the clock running, we can not access its registers, and now
that we have it, we should add it here so that it gets enabled as
and when needed.
Update the DTSI accordingly.
Signed-off-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index d66590fa922f..ac9cb46d8bc9 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -442,6 +442,7 @@ cmu_peric1: clock-controller@10c00000 {
sysreg_peric1: syscon@10c20000 {
compatible = "google,gs101-peric1-sysreg", "syscon";
reg = <0x10c20000 0x10000>;
+ clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>;
};
pinctrl_peric1: pinctrl@10c40000 {
--
2.43.0.429.g432eaa2c6b-goog
Otherwise it won't be accessible.
Signed-off-by: André Draszik <[email protected]>
---
.../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index 33d837ae4f45..c0c6ce8fc786 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -73,6 +73,7 @@ allOf:
contains:
enum:
- google,gs101-peric0-sysreg
+ - google,gs101-peric1-sysreg
- samsung,exynos850-cmgp-sysreg
- samsung,exynos850-peri-sysreg
- samsung,exynos850-sysreg
--
2.43.0.429.g432eaa2c6b-goog
This bus has various USB-related devices attached to it.
Signed-off-by: André Draszik <[email protected]>
---
arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
index cb4d17339b6b..c8f6b955cd4e 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
+++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
@@ -72,6 +72,10 @@ eeprom: eeprom@50 {
};
};
+&hsi2c_12 {
+ status = "okay";
+};
+
&pinctrl_far_alive {
key_voldown: key-voldown-pins {
samsung,pins = "gpa7-3";
@@ -113,6 +117,11 @@ &usi8 {
status = "okay";
};
+&usi12 {
+ samsung,mode = <USI_V2_I2C>;
+ status = "okay";
+};
+
&watchdog_cl0 {
timeout-sec = <30>;
status = "okay";
--
2.43.0.429.g432eaa2c6b-goog
CMU_PERIC1 is the clock management unit used for the peric1 block which
is used for additional USI, I3C and PWM interfaces/busses. Add support
for muxes, dividers and gates of cmu_peric1, except for
CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and
which downstream also ignores (similar to cmu_peric0).
Two clocks have been marked as CLK_IS_CRITICAL for the following
reason:
* disabling them makes it impossible to access any peric1
registers, (including those two registers).
* disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the
additional effect of making the whole system unresponsive.
The clocks marked as CLK_IGNORE_UNUSED need to be kept on until we have
updated the respective drivers for the following reasons:
* gout_peric1_gpio_peric1_pclk is required by the pinctrl
configuration. With this clock disabled, reconfiguring the pins
(for USI/I2C, USI/UART) will hang during register access.
Since pingctrl-samsung doesn't support a clock at the moment, we
just keep the kernel from disabling it at boot, until we have an
update for samsung-pinctrl, at which point we'll drop the flag.
* gout_peric1_sysreg_peric1_pclk needs to be hooked up to
sysreg_peric1 in DT which will be done in a followup-patch, at
which point we'll drop the special treatment from here. We're
adding the flag temporarily here so as to not break the boot (due
to pclk otherwise getting disabled).
Signed-off-by: André Draszik <[email protected]>
---
Note for future reference: To ensure consistent naming throughout this
driver, the clock names have been derived from the data sheet using the
following, with the expectation for all future additions to this file
to use the same:
sed \
-e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|fout_\L\1_pll|' \
\
-e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_\(.*\)|mout_\L\1_\2|' \
-e 's|^PLL_CON0_PLL_\(.*\)|mout_pll_\L\1|' \
-e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|mout_\L\1|' \
-e '/^PLL_CON[1-4]_[^_]\+_/d' \
-e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
-e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
\
-e 's|_IPCLKPORT||' \
-e 's|_RSTNSYNC||' \
\
-e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_\(.*\)|dout_\L\1_\2|' \
\
-e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_\(.*\)|gout_\L\1_\2|' \
-e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
-e 's|^gout_[^_]\+_[^_]\+_cmu_\([^_]\+\)_pclk$|gout_\1_\1_pclk|' \
-e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
-e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|gout_\L\1_clk_\L\1_\2|' \
\
-e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
---
drivers/clk/samsung/clk-gs101.c | 346 ++++++++++++++++++++++++++++++++
1 file changed, 346 insertions(+)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 27debbafdce4..7f6c3b52d9ff 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -21,6 +21,7 @@
#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
+#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -3066,6 +3067,348 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
.clk_name = "bus",
};
+/* ---- CMU_PERIC1 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_PERIC1 (0x10c00000) */
+#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
+#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
+#define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610
+#define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614
+#define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620
+#define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624
+#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630
+#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634
+#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640
+#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644
+#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650
+#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654
+#define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660
+#define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664
+#define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670
+#define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674
+#define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810
+#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
+#define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804
+#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
+#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
+#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
+#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
+#define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818
+#define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000
+#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
+#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008
+#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074
+#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
+#define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000
+#define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004
+#define QCH_CON_D_TZPC_PERIC1_QCH 0x3008
+#define QCH_CON_GPC_PERIC1_QCH 0x300c
+#define QCH_CON_GPIO_PERIC1_QCH 0x3010
+#define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014
+#define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018
+#define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c
+#define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020
+#define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024
+#define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028
+#define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c
+#define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030
+#define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034
+#define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038
+#define QCH_CON_SYSREG_PERIC1_QCH 0x303c
+#define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00
+
+static const unsigned long peric1_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER,
+ PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0,
+ CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI,
+ CLK_CON_BUF_CLKBUF_PERIC1_IP,
+ CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
+ CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
+ DMYQCH_CON_PERIC1_TOP0_QCH_S,
+ PCH_CON_LHM_AXI_P_PERIC1_PCH,
+ QCH_CON_D_TZPC_PERIC1_QCH,
+ QCH_CON_GPC_PERIC1_QCH,
+ QCH_CON_GPIO_PERIC1_QCH,
+ QCH_CON_LHM_AXI_P_PERIC1_QCH,
+ QCH_CON_PERIC1_CMU_PERIC1_QCH,
+ QCH_CON_PERIC1_TOP0_QCH_I3C0,
+ QCH_CON_PERIC1_TOP0_QCH_PWM,
+ QCH_CON_PERIC1_TOP0_QCH_USI0_USI,
+ QCH_CON_PERIC1_TOP0_QCH_USI10_USI,
+ QCH_CON_PERIC1_TOP0_QCH_USI11_USI,
+ QCH_CON_PERIC1_TOP0_QCH_USI12_USI,
+ QCH_CON_PERIC1_TOP0_QCH_USI13_USI,
+ QCH_CON_PERIC1_TOP0_QCH_USI9_USI,
+ QCH_CON_SYSREG_PERIC1_QCH,
+ QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1,
+};
+
+/* List of parent clocks for Muxes in CMU_PERIC1 */
+PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
+PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" };
+
+static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
+ mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC1_I3C_USER,
+ "mout_peric1_i3c_user", mout_peric1_nonbususer_p,
+ PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC1_USI0_USI_USER,
+ "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC1_USI10_USI_USER,
+ "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC1_USI11_USI_USER,
+ "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC1_USI12_USI_USER,
+ "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC1_USI13_USI_USER,
+ "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC1_USI9_USI_USER,
+ "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
+ PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
+};
+
+static const struct samsung_div_clock peric1_div_clks[] __initconst = {
+ DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
+ CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
+ DIV(CLK_DOUT_PERIC1_USI0_USI,
+ "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4),
+ DIV(CLK_DOUT_PERIC1_USI10_USI,
+ "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4),
+ DIV(CLK_DOUT_PERIC1_USI11_USI,
+ "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4),
+ DIV(CLK_DOUT_PERIC1_USI12_USI,
+ "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4),
+ DIV(CLK_DOUT_PERIC1_USI13_USI,
+ "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4),
+ DIV(CLK_DOUT_PERIC1_USI9_USI,
+ "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4),
+};
+
+static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_PERIC1_PCLK,
+ "gout_peric1_peric1_pclk", "mout_peric1_bus_user",
+ CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
+ 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK,
+ "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c",
+ CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK,
+ "gout_peric1_clk_peric1_oscclk_clk", "oscclk",
+ CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK,
+ "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK,
+ "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
+ "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
+ "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
+ 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
+ "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
+ "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
+ "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
+ "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
+ "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
+ "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
+ "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1,
+ "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15,
+ "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2,
+ "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3,
+ "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4,
+ "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5,
+ "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6,
+ "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8,
+ "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK,
+ "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK,
+ "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK,
+ "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK,
+ "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK,
+ "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK,
+ "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK,
+ "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
+ "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info peric1_cmu_info __initconst = {
+ .mux_clks = peric1_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
+ .div_clks = peric1_div_clks,
+ .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
+ .gate_clks = peric1_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
+ .nr_clk_ids = CLKS_NR_PERIC1,
+ .clk_regs = peric1_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
+ .clk_name = "bus",
+};
+
/* ---- platform_driver ----------------------------------------------------- */
static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -3086,6 +3429,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
}, {
.compatible = "google,gs101-cmu-peric0",
.data = &peric0_cmu_info,
+ }, {
+ .compatible = "google,gs101-cmu-peric1",
+ .data = &peric1_cmu_info,
}, {
},
};
--
2.43.0.429.g432eaa2c6b-goog
On Sat, 2024-01-27 at 00:19 +0000, André Draszik wrote:
> The clocks marked as CLK_IGNORE_UNUSED need to be kept on until we have
> updated the respective drivers for the following reasons:
> * gout_peric1_gpio_peric1_pclk is required by the pinctrl
> configuration. With this clock disabled, reconfiguring the pins
> (for USI/I2C, USI/UART) will hang during register access.
> Since pingctrl-samsung doesn't support a clock at the moment, we
> just keep the kernel from disabling it at boot, until we have an
> update for samsung-pinctrl, at which point we'll drop the flag.
I have patches for pinctrl-samsung implementing this new clock ready. Will
send next week.
Cheers,
Andre'
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> Hi,
>
> This patch series implements support for the 2nd connectivity
> peripheral block on gs101.
> This block contains an additional 6 USI, 1 I3C and 1 PWM
> interfaces/busses.
>
> i2cdetect shows all expected devices on the one i2c bus that this patch
> series enables.
> Everything that's in scope in this series works also without the
> clk_ignore_unused kernel command line argument.
>
> While working on this, I noticed the existing peric0 support for gs101
> has a couple issues. That explains why there are differences compared
> to it and a separate patch series will be sent to fix up peric0
> support.
>
> Cheers,
> Andre'
>
Looks like PATCH [00/xx] is missing in the subject.
> .../bindings/clock/google,gs101-clock.yaml | 9 +-
> .../soc/samsung/samsung,exynos-sysreg.yaml | 2 +
> .../boot/dts/exynos/google/gs101-oriole.dts | 9 +
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 42 ++
> drivers/clk/samsung/clk-gs101.c | 347 ++++++++++++++++-
> include/dt-bindings/clock/google,gs101.h | 48 +++
>
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> Add dt-schema documentation and clock IDs for the Connectivity
> Peripheral 1 (PERIC1) clock management unit.
>
> Signed-off-by: André Draszik <[email protected]>
>
> ---
> Note for future reference: To ensure consistent naming throughout this
> file, the IDs have been derived from the data sheet using the
> following, with the expectation for all future additions to this file
> to use the same:
> sed \
> -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|CLK_FOUT_\1_PLL|' \
> \
> -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_|CLK_MOUT_\1_|' \
> -e 's|^PLL_CON0_PLL_\(.*\)|CLK_MOUT_PLL_\1|' \
> -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|CLK_MOUT_\1|' \
> -e '/^PLL_CON[1-4]_[^_]\+_/d' \
> -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
> -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
> \
> -e 's|_IPCLKPORT||' \
> -e 's|_RSTNSYNC||' \
> \
> -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_|CLK_DOUT_\1_|' \
> \
> -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_|CLK_GOUT_\1_|' \
> -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \
> -e 's|^CLK_GOUT_[^_]\+_[^_]\+_CMU_\([^_]\+\)_PCLK$|CLK_GOUT_\1_PCLK|' \
> -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \
> -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|CLK_GOUT_\1_CLK_\1_\2|' \
> \
> -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> .../bindings/clock/google,gs101-clock.yaml | 9 ++--
> include/dt-bindings/clock/google,gs101.h | 48 +++++++++++++++++++
> 2 files changed, 54 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> index 03698cdecf7a..1d2bcea41c85 100644
> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -31,6 +31,7 @@ properties:
> - google,gs101-cmu-apm
> - google,gs101-cmu-misc
> - google,gs101-cmu-peric0
> + - google,gs101-cmu-peric1
>
> clocks:
> minItems: 1
> @@ -93,15 +94,17 @@ allOf:
> properties:
> compatible:
> contains:
> - const: google,gs101-cmu-peric0
> + enum:
> + - google,gs101-cmu-peric0
> + - google,gs101-cmu-peric1
>
> then:
> properties:
> clocks:
> items:
> - description: External reference clock (24.576 MHz)
> - - description: Connectivity Peripheral 0 bus clock (from CMU_TOP)
> - - description: Connectivity Peripheral 0 IP clock (from CMU_TOP)
> + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
> + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
>
> clock-names:
> items:
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> index 64e6bdc6359c..3dac3577788a 100644
> --- a/include/dt-bindings/clock/google,gs101.h
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -470,4 +470,52 @@
> #define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
> #define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
>
> +/* CMU_PERIC1 */
> +#define CLK_MOUT_PERIC1_BUS_USER 1
> +#define CLK_MOUT_PERIC1_I3C_USER 2
> +#define CLK_MOUT_PERIC1_USI0_USI_USER 3
> +#define CLK_MOUT_PERIC1_USI10_USI_USER 4
> +#define CLK_MOUT_PERIC1_USI11_USI_USER 5
> +#define CLK_MOUT_PERIC1_USI12_USI_USER 6
> +#define CLK_MOUT_PERIC1_USI13_USI_USER 7
> +#define CLK_MOUT_PERIC1_USI9_USI_USER 8
> +#define CLK_DOUT_PERIC1_I3C 9
> +#define CLK_DOUT_PERIC1_USI0_USI 10
> +#define CLK_DOUT_PERIC1_USI10_USI 11
> +#define CLK_DOUT_PERIC1_USI11_USI 12
> +#define CLK_DOUT_PERIC1_USI12_USI 13
> +#define CLK_DOUT_PERIC1_USI13_USI 14
> +#define CLK_DOUT_PERIC1_USI9_USI 15
> +#define CLK_GOUT_PERIC1_IP 16
> +#define CLK_GOUT_PERIC1_PCLK 17
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19
> +#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20
> +#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21
> +#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22
> +#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> +#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
> +
> #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> Enable the cmu-peric1 clock controller. It feeds additional USI, I3C
> and PWM interfaces / busses.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index aaac04df5e65..5088c81fd6aa 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -429,6 +429,16 @@ serial_0: serial@10a00000 {
> };
> };
>
> + cmu_peric1: clock-controller@10c00000 {
> + compatible = "google,gs101-cmu-peric1";
> + reg = <0x10c00000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&ext_24_5m>,
> + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
> + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
> + clock-names = "oscclk", "bus", "ip";
> + };
> +
> sysreg_peric1: syscon@10c20000 {
> compatible = "google,gs101-peric1-sysreg", "syscon";
> reg = <0x10c20000 0x10000>;
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> On the gs101-oriole board, i2c bus 12 has various USB-related
> controllers attached to it.
>
> Note the selection of the USI protocol is intentionally left for the
> board dts file.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 30 ++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 5088c81fd6aa..d66590fa922f 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -450,6 +450,36 @@ pinctrl_peric1: pinctrl@10c40000 {
> interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + usi12: usi@10d500c0 {
> + compatible = "google,gs101-usi",
> + "samsung,exynos850-usi";
It doesn't fit on one line?
> + reg = <0x10d500c0 0x20>;
> + ranges;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>,
> + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>;
> + clock-names = "pclk", "ipclk";
> + samsung,sysreg = <&sysreg_peric1 0x1010>;
> + samsung,mode = <USI_V2_NONE>;
> + status = "disabled";
> +
> + hsi2c_12: i2c@10d50000 {
> + compatible = "google,gs101-hsi2c",
> + "samsung,exynosautov9-hsi2c";
> + reg = <0x10d50000 0xc0>;
> + interrupts = <GIC_SPI 655 IRQ_TYPE_LEVEL_HIGH 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hsi2c12_bus>;
I remember Krzysztof asked me to put pinctrl-0 first in my recent
patches. Not sure how important it is, just saying. Other than that,
LGTM:
Reviewed-by: Sam Protsenko <[email protected]>
> + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5>,
> + <&cmu_peric1 CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5>;
> + clock-names = "hsi2c", "hsi2c_pclk";
> + status = "disabled";
> + };
> + };
> +
> pinctrl_hsi1: pinctrl@11840000 {
> compatible = "google,gs101-pinctrl";
> reg = <0x11840000 0x00001000>;
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> This bus has various USB-related devices attached to it.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
> arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> index cb4d17339b6b..c8f6b955cd4e 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> @@ -72,6 +72,10 @@ eeprom: eeprom@50 {
> };
> };
>
> +&hsi2c_12 {
> + status = "okay";
But there are no bus clients declared here? A bit of explanation about
how this bus is being currently used would be nice to have (in commit
message); e.g. maybe it's used in user space somehow, etc. Because
otherwise it doesn't have much sense to enable the bus with no users.
> +};
> +
> &pinctrl_far_alive {
> key_voldown: key-voldown-pins {
> samsung,pins = "gpa7-3";
> @@ -113,6 +117,11 @@ &usi8 {
> status = "okay";
> };
>
> +&usi12 {
> + samsung,mode = <USI_V2_I2C>;
> + status = "okay";
> +};
> +
> &watchdog_cl0 {
> timeout-sec = <30>;
> status = "okay";
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> Otherwise it won't be accessible.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> index 33d837ae4f45..c0c6ce8fc786 100644
> --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysregyaml
> +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysregyaml
> @@ -73,6 +73,7 @@ allOf:
> contains:
> enum:
> - google,gs101-peric0-sysreg
> + - google,gs101-peric1-sysreg
> - samsung,exynos850-cmgp-sysreg
> - samsung,exynos850-peri-sysreg
> - samsung,exynos850-sysreg
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> Without the clock running, we can not access its registers, and now
> that we have it, we should add it here so that it gets enabled as
> and when needed.
>
That sounds like this patch deserves "Fixes:" tag :) Other than that:
Reviewed-by: Sam Protsenko <[email protected]>
> Update the DTSI accordingly.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index d66590fa922f..ac9cb46d8bc9 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -442,6 +442,7 @@ cmu_peric1: clock-controller@10c00000 {
> sysreg_peric1: syscon@10c20000 {
> compatible = "google,gs101-peric1-sysreg", "syscon";
> reg = <0x10c20000 0x10000>;
> + clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK>;
> };
>
> pinctrl_peric1: pinctrl@10c40000 {
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> Now that we have hooked it up in the DTS, we can drop the
> CLK_IGNORE_UNUSED from here.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> drivers/clk/samsung/clk-gs101.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 7f6c3b52d9ff..d55ed64d0e29 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -3393,7 +3393,7 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
> GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
> "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
> - 21, CLK_IGNORE_UNUSED, 0),
> + 21, 0, 0),
> };
>
> static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>
> CMU_PERIC1 is the clock management unit used for the peric1 block which
> is used for additional USI, I3C and PWM interfaces/busses. Add support
> for muxes, dividers and gates of cmu_peric1, except for
> CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and
> which downstream also ignores (similar to cmu_peric0).
>
> Two clocks have been marked as CLK_IS_CRITICAL for the following
> reason:
> * disabling them makes it impossible to access any peric1
> registers, (including those two registers).
> * disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the
> additional effect of making the whole system unresponsive.
>
> The clocks marked as CLK_IGNORE_UNUSED need to be kept on until we have
> updated the respective drivers for the following reasons:
> * gout_peric1_gpio_peric1_pclk is required by the pinctrl
> configuration. With this clock disabled, reconfiguring the pins
> (for USI/I2C, USI/UART) will hang during register access.
> Since pingctrl-samsung doesn't support a clock at the moment, we
> just keep the kernel from disabling it at boot, until we have an
> update for samsung-pinctrl, at which point we'll drop the flag.
> * gout_peric1_sysreg_peric1_pclk needs to be hooked up to
> sysreg_peric1 in DT which will be done in a followup-patch, at
> which point we'll drop the special treatment from here. We're
> adding the flag temporarily here so as to not break the boot (due
> to pclk otherwise getting disabled).
>
> Signed-off-by: André Draszik <[email protected]>
>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> Note for future reference: To ensure consistent naming throughout this
> driver, the clock names have been derived from the data sheet using the
> following, with the expectation for all future additions to this file
> to use the same:
> sed \
> -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|fout_\L\1_pll|' \
> \
> -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_\(.*\)|mout_\L\1_\2|' \
> -e 's|^PLL_CON0_PLL_\(.*\)|mout_pll_\L\1|' \
> -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|mout_\L\1|' \
> -e '/^PLL_CON[1-4]_[^_]\+_/d' \
> -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
> -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
> \
> -e 's|_IPCLKPORT||' \
> -e 's|_RSTNSYNC||' \
> \
> -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_\(.*\)|dout_\L\1_\2|' \
> \
> -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_\(.*\)|gout_\L\1_\2|' \
> -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
> -e 's|^gout_[^_]\+_[^_]\+_cmu_\([^_]\+\)_pclk$|gout_\1_\1_pclk|' \
> -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
> -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|gout_\L\1_clk_\L\1_\2|' \
> \
> -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
> ---
> drivers/clk/samsung/clk-gs101.c | 346 ++++++++++++++++++++++++++++++++
> 1 file changed, 346 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 27debbafdce4..7f6c3b52d9ff 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -21,6 +21,7 @@
> #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
> #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> +#define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -3066,6 +3067,348 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
> .clk_name = "bus",
> };
>
> +/* ---- CMU_PERIC1 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_PERIC1 (0x10c00000) */
> +#define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
> +#define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
> +#define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610
> +#define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614
> +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620
> +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624
> +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630
> +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634
> +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640
> +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644
> +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650
> +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654
> +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660
> +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664
> +#define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670
> +#define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674
> +#define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810
> +#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
> +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804
> +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
> +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
> +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
> +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
> +#define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818
> +#define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000
> +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
> +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008
> +#define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
> +#define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000
> +#define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004
> +#define QCH_CON_D_TZPC_PERIC1_QCH 0x3008
> +#define QCH_CON_GPC_PERIC1_QCH 0x300c
> +#define QCH_CON_GPIO_PERIC1_QCH 0x3010
> +#define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014
> +#define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018
> +#define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c
> +#define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020
> +#define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024
> +#define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028
> +#define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c
> +#define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030
> +#define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034
> +#define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038
> +#define QCH_CON_SYSREG_PERIC1_QCH 0x303c
> +#define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00
> +
> +static const unsigned long peric1_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER,
> + PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
> + CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0,
> + CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI,
> + CLK_CON_BUF_CLKBUF_PERIC1_IP,
> + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
> + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
> + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
> + DMYQCH_CON_PERIC1_TOP0_QCH_S,
> + PCH_CON_LHM_AXI_P_PERIC1_PCH,
> + QCH_CON_D_TZPC_PERIC1_QCH,
> + QCH_CON_GPC_PERIC1_QCH,
> + QCH_CON_GPIO_PERIC1_QCH,
> + QCH_CON_LHM_AXI_P_PERIC1_QCH,
> + QCH_CON_PERIC1_CMU_PERIC1_QCH,
> + QCH_CON_PERIC1_TOP0_QCH_I3C0,
> + QCH_CON_PERIC1_TOP0_QCH_PWM,
> + QCH_CON_PERIC1_TOP0_QCH_USI0_USI,
> + QCH_CON_PERIC1_TOP0_QCH_USI10_USI,
> + QCH_CON_PERIC1_TOP0_QCH_USI11_USI,
> + QCH_CON_PERIC1_TOP0_QCH_USI12_USI,
> + QCH_CON_PERIC1_TOP0_QCH_USI13_USI,
> + QCH_CON_PERIC1_TOP0_QCH_USI9_USI,
> + QCH_CON_SYSREG_PERIC1_QCH,
> + QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_PERIC1 */
> +PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
> +PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" };
> +
> +static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
> + mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC1_I3C_USER,
> + "mout_peric1_i3c_user", mout_peric1_nonbususer_p,
> + PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC1_USI0_USI_USER,
> + "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC1_USI10_USI_USER,
> + "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC1_USI11_USI_USER,
> + "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC1_USI12_USI_USER,
> + "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC1_USI13_USI_USER,
> + "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC1_USI9_USI_USER,
> + "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
> + PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
> +};
> +
> +static const struct samsung_div_clock peric1_div_clks[] __initconst = {
> + DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
> + CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
> + DIV(CLK_DOUT_PERIC1_USI0_USI,
> + "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4),
> + DIV(CLK_DOUT_PERIC1_USI10_USI,
> + "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4),
> + DIV(CLK_DOUT_PERIC1_USI11_USI,
> + "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4),
> + DIV(CLK_DOUT_PERIC1_USI12_USI,
> + "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4),
> + DIV(CLK_DOUT_PERIC1_USI13_USI,
> + "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4),
> + DIV(CLK_DOUT_PERIC1_USI9_USI,
> + "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4),
> +};
> +
> +static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_PERIC1_PCLK,
> + "gout_peric1_peric1_pclk", "mout_peric1_bus_user",
> + CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
> + 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK,
> + "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c",
> + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK,
> + "gout_peric1_clk_peric1_oscclk_clk", "oscclk",
> + CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK,
> + "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK,
> + "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
> + "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
> + 21, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
> + "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
> + 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
> + "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
> + "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
> + "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
> + "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
> + "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
> + "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
> + "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1,
> + "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15,
> + "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2,
> + "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3,
> + "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4,
> + "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5,
> + "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6,
> + "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8,
> + "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK,
> + "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK,
> + "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK,
> + "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK,
> + "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK,
> + "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK,
> + "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK,
> + "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
> + "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
> + 21, CLK_IGNORE_UNUSED, 0),
> +};
> +
> +static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> + .mux_clks = peric1_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
> + .div_clks = peric1_div_clks,
> + .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
> + .gate_clks = peric1_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
> + .nr_clk_ids = CLKS_NR_PERIC1,
> + .clk_regs = peric1_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
> + .clk_name = "bus",
> +};
> +
> /* ---- platform_driver ----------------------------------------------------- */
>
> static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -3086,6 +3429,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> }, {
> .compatible = "google,gs101-cmu-peric0",
> .data = &peric0_cmu_info,
> + }, {
> + .compatible = "google,gs101-cmu-peric1",
> + .data = &peric1_cmu_info,
> }, {
> },
> };
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Sat, 27 Jan 2024 at 00:19, André Draszik <[email protected]> wrote:
>
> Enable the cmu-peric1 clock controller. It feeds additional USI, I3C
> and PWM interfaces / busses.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
Reviewed-by: Peter Griffin <[email protected]>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index aaac04df5e65..5088c81fd6aa 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -429,6 +429,16 @@ serial_0: serial@10a00000 {
> };
> };
>
> + cmu_peric1: clock-controller@10c00000 {
> + compatible = "google,gs101-cmu-peric1";
> + reg = <0x10c00000 0x4000>;
> + #clock-cells = <1>;
> + clocks = <&ext_24_5m>,
> + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
> + <&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
> + clock-names = "oscclk", "bus", "ip";
> + };
> +
> sysreg_peric1: syscon@10c20000 {
> compatible = "google,gs101-peric1-sysreg", "syscon";
> reg = <0x10c20000 0x10000>;
> --
> 2.43.0.429.g432eaa2c6b-goog
>
Hi André
On Sat, 27 Jan 2024 at 00:19, André Draszik <[email protected]> wrote:
>
> Add dt-schema documentation and clock IDs for the Connectivity
> Peripheral 1 (PERIC1) clock management unit.
>
> Signed-off-by: André Draszik <[email protected]>
>
> ---
Thanks for working on these regexes! That should make enabling more
clock units and other Exynos SoCs a bit easier.
Reviewed-by: Peter Griffin <[email protected]>
> Note for future reference: To ensure consistent naming throughout this
> file, the IDs have been derived from the data sheet using the
> following, with the expectation for all future additions to this file
> to use the same:
> sed \
> -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|CLK_FOUT_\1_PLL|' \
> \
> -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_|CLK_MOUT_\1_|' \
> -e 's|^PLL_CON0_PLL_\(.*\)|CLK_MOUT_PLL_\1|' \
> -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|CLK_MOUT_\1|' \
> -e '/^PLL_CON[1-4]_[^_]\+_/d' \
> -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
> -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
> \
> -e 's|_IPCLKPORT||' \
> -e 's|_RSTNSYNC||' \
> \
> -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_|CLK_DOUT_\1_|' \
> \
> -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_|CLK_GOUT_\1_|' \
> -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \
> -e 's|^CLK_GOUT_[^_]\+_[^_]\+_CMU_\([^_]\+\)_PCLK$|CLK_GOUT_\1_PCLK|' \
> -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_|CLK_GOUT_\1_|' \
> -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|CLK_GOUT_\1_CLK_\1_\2|' \
> \
> -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
> ---
> .../bindings/clock/google,gs101-clock.yaml | 9 ++--
> include/dt-bindings/clock/google,gs101.h | 48 +++++++++++++++++++
> 2 files changed, 54 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> index 03698cdecf7a..1d2bcea41c85 100644
> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> @@ -31,6 +31,7 @@ properties:
> - google,gs101-cmu-apm
> - google,gs101-cmu-misc
> - google,gs101-cmu-peric0
> + - google,gs101-cmu-peric1
>
> clocks:
> minItems: 1
> @@ -93,15 +94,17 @@ allOf:
> properties:
> compatible:
> contains:
> - const: google,gs101-cmu-peric0
> + enum:
> + - google,gs101-cmu-peric0
> + - google,gs101-cmu-peric1
>
> then:
> properties:
> clocks:
> items:
> - description: External reference clock (24.576 MHz)
> - - description: Connectivity Peripheral 0 bus clock (from CMU_TOP)
> - - description: Connectivity Peripheral 0 IP clock (from CMU_TOP)
> + - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
> + - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)
>
> clock-names:
> items:
> diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
> index 64e6bdc6359c..3dac3577788a 100644
> --- a/include/dt-bindings/clock/google,gs101.h
> +++ b/include/dt-bindings/clock/google,gs101.h
> @@ -470,4 +470,52 @@
> #define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
> #define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
>
> +/* CMU_PERIC1 */
> +#define CLK_MOUT_PERIC1_BUS_USER 1
> +#define CLK_MOUT_PERIC1_I3C_USER 2
> +#define CLK_MOUT_PERIC1_USI0_USI_USER 3
> +#define CLK_MOUT_PERIC1_USI10_USI_USER 4
> +#define CLK_MOUT_PERIC1_USI11_USI_USER 5
> +#define CLK_MOUT_PERIC1_USI12_USI_USER 6
> +#define CLK_MOUT_PERIC1_USI13_USI_USER 7
> +#define CLK_MOUT_PERIC1_USI9_USI_USER 8
> +#define CLK_DOUT_PERIC1_I3C 9
> +#define CLK_DOUT_PERIC1_USI0_USI 10
> +#define CLK_DOUT_PERIC1_USI10_USI 11
> +#define CLK_DOUT_PERIC1_USI11_USI 12
> +#define CLK_DOUT_PERIC1_USI12_USI 13
> +#define CLK_DOUT_PERIC1_USI13_USI 14
> +#define CLK_DOUT_PERIC1_USI9_USI 15
> +#define CLK_GOUT_PERIC1_IP 16
> +#define CLK_GOUT_PERIC1_PCLK 17
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK 18
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK 19
> +#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK 20
> +#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK 21
> +#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 22
> +#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 23
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1 24
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2 25
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3 26
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4 27
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5 28
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6 29
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8 30
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1 31
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15 32
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2 33
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3 34
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4 35
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5 36
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6 37
> +#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8 38
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK 39
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK 40
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK 41
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK 42
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK 43
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK 44
> +#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK 45
> +#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 46
> +
> #endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Sat, 27 Jan 2024 at 00:19, André Draszik <[email protected]> wrote:
>
> This bus has various USB-related devices attached to it.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
As Sam said, you could be a bit more verbose on what those USB devices
are on the bus as they aren't enabled in this series. But apart from
that
Reviewed-by: Peter Griffin <[email protected]>
> arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> index cb4d17339b6b..c8f6b955cd4e 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> @@ -72,6 +72,10 @@ eeprom: eeprom@50 {
> };
> };
>
> +&hsi2c_12 {
> + status = "okay";
> +};
> +
> &pinctrl_far_alive {
> key_voldown: key-voldown-pins {
> samsung,pins = "gpa7-3";
> @@ -113,6 +117,11 @@ &usi8 {
> status = "okay";
> };
>
> +&usi12 {
> + samsung,mode = <USI_V2_I2C>;
> + status = "okay";
> +};
> +
> &watchdog_cl0 {
> timeout-sec = <30>;
> status = "okay";
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Sat, 27 Jan 2024 at 00:19, André Draszik <[email protected]> wrote:
>
> Now that we have hooked it up in the DTS, we can drop the
> CLK_IGNORE_UNUSED from here.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
Reviewed-by: Peter Griffin <[email protected]>
> drivers/clk/samsung/clk-gs101.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 7f6c3b52d9ff..d55ed64d0e29 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -3393,7 +3393,7 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
> GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
> "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
> - 21, CLK_IGNORE_UNUSED, 0),
> + 21, 0, 0),
> };
>
> static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Sat, 27 Jan 2024 at 00:19, André Draszik <[email protected]> wrote:
>
> Otherwise it won't be accessible.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
Reviewed-by: Peter Griffin <[email protected]>
> .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
> index 33d837ae4f45..c0c6ce8fc786 100644
> --- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysregyaml
> +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysregyaml
> @@ -73,6 +73,7 @@ allOf:
> contains:
> enum:
> - google,gs101-peric0-sysreg
> + - google,gs101-peric1-sysreg
> - samsung,exynos850-cmgp-sysreg
> - samsung,exynos850-peri-sysreg
> - samsung,exynos850-sysreg
> --
> 2.43.0.429.g432eaa2c6b-goog
>
On Fri, 2024-01-26 at 20:55 -0600, Sam Protsenko wrote:
> On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
> > --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> > @@ -450,6 +450,36 @@ pinctrl_peric1: pinctrl@10c40000 {
> > interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>;
> > };
> >
> > + usi12: usi@10d500c0 {
> > + compatible = "google,gs101-usi",
> > + "samsung,exynos850-usi";
>
> It doesn't fit on one line?
No, it's 81 characters. While I know it's not a hard rule in this case,
there are other cases in this file where the line was split in the same
way, so I followed that.
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&hsi2c12_bus>;
>
> I remember Krzysztof asked me to put pinctrl-0 first in my recent
> patches. Not sure how important it is, just saying. Other than that,
Makes sense, this came from a copy/paste and I have fixed it.
Cheers,
Andre'
Hi Sam,
On Fri, 2024-01-26 at 20:58 -0600, Sam Protsenko wrote:
> On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
> >
> > This bus has various USB-related devices attached to it.
> >
> > [...]
> >
> > +&hsi2c_12 {
> > + status = "okay";
>
> But there are no bus clients declared here? A bit of explanation about
> how this bus is being currently used would be nice to have (in commit
> message); e.g. maybe it's used in user space somehow, etc. Because
> otherwise it doesn't have much sense to enable the bus with no users.
As per the commit message, there are devices, but:
* most or all don't have an upstream driver at this stage
* it does make sense to enable the bus, as enabling it allows working on
the drivers for the devices that are attached to this bus
Cheers,
Andre'
Hi Sam,
On Fri, 2024-01-26 at 21:00 -0600, Sam Protsenko wrote:
> On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
> >
> > Without the clock running, we can not access its registers, and now
> > that we have it, we should add it here so that it gets enabled as
> > and when needed.
> >
>
> That sounds like this patch deserves "Fixes:" tag :) Other than that:
I didn't add it, because at the time &sysreg_peric1 was added, the clock
macro CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK didn't exist and &sysreg_peric1
wasn't in use until this series here anyway.
If this patch here gets backported to some older kernel due to the Fixes: tag,
without the whole peric1 series, it wouldn't build. Therefore I left it out.
Should it still be added?
Cheers,
Andre'
On 29/01/2024 11:45, André Draszik wrote:
> Hi Sam,
>
> On Fri, 2024-01-26 at 21:00 -0600, Sam Protsenko wrote:
>> On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
>>>
>>> Without the clock running, we can not access its registers, and now
>>> that we have it, we should add it here so that it gets enabled as
>>> and when needed.
>>>
>>
>> That sounds like this patch deserves "Fixes:" tag :) Other than that:
>
> I didn't add it, because at the time &sysreg_peric1 was added, the clock
> macro CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK didn't exist and &sysreg_peric1
> wasn't in use until this series here anyway.
> If this patch here gets backported to some older kernel due to the Fixes: tag,
> without the whole peric1 series, it wouldn't build. Therefore I left it out.
Clk patches don't have fixes tag, so Fixes for this alone would be
confusing.
Best regards,
Krzysztof
On 27/01/2024 01:19, André Draszik wrote:
> Now that we have hooked it up in the DTS, we can drop the
Your driver patch cannot depend on DTS. Not for a new platform. I am
repeating this all the time last days...
> CLK_IGNORE_UNUSED from here.
>
> Signed-off-by: André Draszik <[email protected]>
> ---
> drivers/clk/samsung/clk-gs101.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 7f6c3b52d9ff..d55ed64d0e29 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -3393,7 +3393,7 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
> GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
> "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
> - 21, CLK_IGNORE_UNUSED, 0),
I don't understand. You just added this clock in this patchset. This
means that your patch #3 is incorrect.
Best regards,
Krzysztof
On Sat, 27 Jan 2024 at 00:19, André Draszik <[email protected]> wrote:
>
> CMU_PERIC1 is the clock management unit used for the peric1 block which
> is used for additional USI, I3C and PWM interfaces/busses. Add support
> for muxes, dividers and gates of cmu_peric1, except for
> CLK_GOUT_PERIC1_IP which isn't well described in the datasheet and
> which downstream also ignores (similar to cmu_peric0).
>
> Two clocks have been marked as CLK_IS_CRITICAL for the following
> reason:
> * disabling them makes it impossible to access any peric1
> registers, (including those two registers).
> * disabling gout_peric1_lhm_axi_p_peric1_i_clk sometimes has the
> additional effect of making the whole system unresponsive.
>
> The clocks marked as CLK_IGNORE_UNUSED need to be kept on until we have
> updated the respective drivers for the following reasons:
> * gout_peric1_gpio_peric1_pclk is required by the pinctrl
> configuration. With this clock disabled, reconfiguring the pins
> (for USI/I2C, USI/UART) will hang during register access.
> Since pingctrl-samsung doesn't support a clock at the moment, we
> just keep the kernel from disabling it at boot, until we have an
> update for samsung-pinctrl, at which point we'll drop the flag.
> * gout_peric1_sysreg_peric1_pclk needs to be hooked up to
> sysreg_peric1 in DT which will be done in a followup-patch, at
> which point we'll drop the special treatment from here. We're
> adding the flag temporarily here so as to not break the boot (due
> to pclk otherwise getting disabled).
>
> Signed-off-by: André Draszik <[email protected]>
>
> ---
Thankyou for being verbose on this reasoning behind CLK_IGNORE_UNUSED
and CLK_IS_CRITICAL flags
Reviewed-by: Peter Griffin <[email protected]>
Hi Krzysztof,
On Mon, 2024-01-29 at 12:03 +0100, Krzysztof Kozlowski wrote:
> On 27/01/2024 01:19, André Draszik wrote:
> > Now that we have hooked it up in the DTS, we can drop the
>
> Your driver patch cannot depend on DTS. Not for a new platform. I am
> repeating this all the time last days...
>
> > CLK_IGNORE_UNUSED from here.
> >
> > Signed-off-by: André Draszik <[email protected]>
> > ---
> > drivers/clk/samsung/clk-gs101.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> > index 7f6c3b52d9ff..d55ed64d0e29 100644
> > --- a/drivers/clk/samsung/clk-gs101.c
> > +++ b/drivers/clk/samsung/clk-gs101.c
> > @@ -3393,7 +3393,7 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
> > GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
> > "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
> > CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
> > - 21, CLK_IGNORE_UNUSED, 0),
>
> I don't understand. You just added this clock in this patchset. This
> means that your patch #3 is incorrect.
In patch #3 I'm hooking up all the clocks to Linux. If I don't CLK_IGNORE_UNUSED
for the 'sysreg' pclk in patch #3, then it'll hang on loading drivers that
require sysreg access (because Linux disabled the clock).
I can not change patch #8 to come between 2 and 3 either, because at that stage
neither the clock nor the DT node reference &cmu_peric1 actually exist, and the
clock and can't be claimed by sysreg.
Since we can not mix DT and driver changes in the same commit, I can not merge
patches #3 and #4 and #8 either.
I had to do it this way so that the platform always boots for every commit to keep
things bisectable.
Alternatively, I could merge patches #4 and #8 (but that seems wrong to me), or
drop patches #7, #8 and #9 from this series and apply it later in the -rc phase?
Is there a better way that you have in mind that we're missing, that keeps things
atomic and bootable/bisectable?
Cheers,
Andre'
On 29/01/2024 14:47, André Draszik wrote:
> Hi Krzysztof,
>
> On Mon, 2024-01-29 at 12:03 +0100, Krzysztof Kozlowski wrote:
>> On 27/01/2024 01:19, André Draszik wrote:
>>> Now that we have hooked it up in the DTS, we can drop the
>>
>> Your driver patch cannot depend on DTS. Not for a new platform. I am
>> repeating this all the time last days...
>>
>>> CLK_IGNORE_UNUSED from here.
>>>
>>> Signed-off-by: André Draszik <[email protected]>
>>> ---
>>> drivers/clk/samsung/clk-gs101.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
>>> index 7f6c3b52d9ff..d55ed64d0e29 100644
>>> --- a/drivers/clk/samsung/clk-gs101.c
>>> +++ b/drivers/clk/samsung/clk-gs101.c
>>> @@ -3393,7 +3393,7 @@ static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
>>> GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
>>> "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
>>> CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
>>> - 21, CLK_IGNORE_UNUSED, 0),
>>
>> I don't understand. You just added this clock in this patchset. This
>> means that your patch #3 is incorrect.
>
> In patch #3 I'm hooking up all the clocks to Linux. If I don't CLK_IGNORE_UNUSED
> for the 'sysreg' pclk in patch #3, then it'll hang on loading drivers that
> require sysreg access (because Linux disabled the clock).
Then add clk_ignore_unused to cmdline. That's anyway recommended for
development platforms without full clock and pd description
(pd_ignore_unused). Not mentioning that we might default to
clk_ignore_unused at some point soon.
>
> I can not change patch #8 to come between 2 and 3 either, because at that stage
> neither the clock nor the DT node reference &cmu_peric1 actually exist, and the
> clock and can't be claimed by sysreg.
At the point of me applying this patch, there will be no DTS node
either. This ordering fixes nothing.
>
> Since we can not mix DT and driver changes in the same commit, I can not merge
> patches #3 and #4 and #8 either.
>
> I had to do it this way so that the platform always boots for every commit to keep
> things bisectable.
But it is not bisectable - you did not fix anything. You can try by
yourself:
# git checkout drivers
# git am patch #1, #2, #3 and #9
# git checkout dt
# git am patch #4, #5, #6, #7, #8
and now try to bisect it. You will have the same problems you try to
avoid. So what is solved by this ordering? Nothing.
>
> Alternatively, I could merge patches #4 and #8 (but that seems wrong to me), or
> drop patches #7, #8 and #9 from this series and apply it later in the -rc phase?
Probably the mistake was done in the way how you upstream things: adding
sysreg syscon without its clocks.
Additionally:
1. Disabling unused clocks is current OS policy, so why the policy
should affect DTS and driver ordering?
2. This is platform did not receive a release kernel, so glitches are okay.
For this case #9 must be squashed with #3. #4 with #9.
>
>
> Is there a better way that you have in mind that we're missing, that keeps things
> atomic and bootable/bisectable?
Best regards,
Krzysztof
On Mon, 2024-01-29 at 15:08 +0100, Krzysztof Kozlowski wrote:
> For this case #9 must be squashed with #3. #4 with #9.
Will do as you suggest, Krzysztof (I think you meant #4 with #8).
Thanks for your patience.
Cheers,
Andre'
On 29/01/2024 16:21, André Draszik wrote:
> On Mon, 2024-01-29 at 15:08 +0100, Krzysztof Kozlowski wrote:
>> For this case #9 must be squashed with #3. #4 with #9.
>
> Will do as you suggest, Krzysztof (I think you meant #4 with #8).
Yes, indeed, the DTS patches.
Best regards,
Krzysztof
On Mon, Jan 29, 2024 at 4:40 AM André Draszik <[email protected]> wrote:
>
> Hi Sam,
>
> On Fri, 2024-01-26 at 20:58 -0600, Sam Protsenko wrote:
> > On Fri, Jan 26, 2024 at 6:19 PM André Draszik <[email protected]> wrote:
> > >
> > > This bus has various USB-related devices attached to it.
> > >
> > > [...]
> > >
> > > +&hsi2c_12 {
> > > + status = "okay";
> >
> > But there are no bus clients declared here? A bit of explanation about
> > how this bus is being currently used would be nice to have (in commit
> > message); e.g. maybe it's used in user space somehow, etc. Because
> > otherwise it doesn't have much sense to enable the bus with no users.
>
> As per the commit message, there are devices, but:
> * most or all don't have an upstream driver at this stage
> * it does make sense to enable the bus, as enabling it allows working on
> the drivers for the devices that are attached to this bus
>
Then can you please add the corresponding TODO comment on top of the
code you added in this patch? And perhaps also describe which devices
you have on the bus in commit message.
> Cheers,
> Andre'
>
On 1/27/24 00:19, André Draszik wrote:
> Add dt-schema documentation and clock IDs for the Connectivity
> Peripheral 1 (PERIC1) clock management unit.
>
> Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Tudor Ambarus <[email protected]>
On Mon, 2024-01-29 at 09:28 +0000, Peter Griffin wrote:
> As Sam said, you could be a bit more verbose on what those USB devices
> are on the bus as they aren't enabled in this series. But apart from
Done.
A.
On Mon, 2024-01-29 at 10:34 -0600, Sam Protsenko wrote:
> Then can you please add the corresponding TODO comment on top of the
> code you added in this patch? And perhaps also describe which devices
> you have on the bus in commit message.
Done.
Cheers,
Andre'
Hi, Andre',
I played with SPI and noticed that we have to propagate some clock rates
to parents here. If you don't play with all the peripherals from the
block you can't know what to propagate. So I think it's fine to not
handle this topic right now. I'll come with a patch on top of yours when
I finish the SPI validation. The patch is looking fine. I'll finish
reviewing the series after v2 is out.
Cheers,
ta