This patch set shall be queued after the cmu_misc clock name fixes from:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
Add support for PERIC0 clocks. Use them for USI in serial and I2C
configurations. Tested the serial at different baudrates (115200,
1M, 3M) and the I2C with an at24 eeprom, all went fine.
Apart of the DT and defconfig changes, the patch set spans through the tty
and clk subsystems. The expectation is that Krzysztof will apply the whole
series through the Samsung SoC tree. If the tty and clk subsystem
maintainers can give an acked-by or reviewed-by on the relevant patches
that would be most appreciated!
Thanks!
ta
Changes in v3:
- rename cmu_peric0 clocks to just "bus" and "ip" and then comply with
the change in device tree and clock driver
- reposition ``iotype`` of ``struct s3c24xx_uart_info`` to reduce the
memory footprint of the struct. A patch set reworking the members of
the struct will follow.
- fix the usi8 clocks order in the device tree
- collect Peter's R-b tags
- changes log in each patch set as well, in the comments section under
```---```
Changes in v2:
- gs101 serial - infer the reg-io-width from the compatible as the entire
PERIC block allows just 32-bit register accesses.
- identify the critical clocks faaaaaaarom PERIC0 and mark them accordingly
(if disabled theslocks hang the system even if their parents are
still enabled).
- update dtsi and use USI's gate clocks instead of the dividers clocks
- move hsi2c_8 cells and pinctrls into dtsi
- address Sam's cosmetic changes in the device tree files
- drop defconfig patches (savedefconfig output & at24 eeprom enablement)
- collect Acked-by and Reviewed-by tags
- changes log in each patch as well, in the comments section under
```---```
Tudor Ambarus (12):
dt-bindings: clock: google,gs101-clock: add PERIC0 clock management
unit
dt-bindings: i2c: exynos5: add google,gs101-hsi2c compatible
dt-bindings: serial: samsung: do not allow reg-io-width for gs101
tty: serial: samsung: prepare for different IO types
tty: serial: samsung: set UPIO_MEM32 iotype for gs101
tty: serial: samsung: add gs101 earlycon support
clk: samsung: gs101: add support for cmu_peric0
arm64: dts: exynos: gs101: remove reg-io-width from serial
arm64: dts: exynos: gs101: enable cmu-peric0 clock controller
arm64: dts: exynos: gs101: update USI UART to use peric0 clocks
arm64: dts: exynos: gs101: define USI8 with I2C configuration
arm64: dts: exynos: gs101: enable eeprom on gs101-oriole
.../bindings/clock/google,gs101-clock.yaml | 25 +-
.../devicetree/bindings/i2c/i2c-exynos5.yaml | 1 +
.../bindings/serial/samsung_uart.yaml | 2 +
.../boot/dts/exynos/google/gs101-oriole.dts | 14 +
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 54 +-
drivers/clk/samsung/clk-gs101.c | 583 ++++++++++++++++++
drivers/tty/serial/samsung_tty.c | 58 +-
include/dt-bindings/clock/google,gs101.h | 81 +++
8 files changed, 794 insertions(+), 24 deletions(-)
--
2.43.0.472.g3155946c3a-goog
Add dt-schema documentation for the Connectivity Peripheral 0 (PERIC0)
clock management unit.
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3:
- rename the clock names to just "bus" and "ip" as per Rob's suggestion
- collect Peter's R-b tag
v2:
- fix comments as per Sam's suggestion and collect his R-b tag
- Rob's suggestion of renaming the clock-names to just "bus" and "ip"
was not implemented as I felt it affects readability in the driver
and consistency with other exynos clock drivers. I will happily update
the names in the -rc phase if someone else has a stronger opinion than
mine.
.../bindings/clock/google,gs101-clock.yaml | 25 +++++-
include/dt-bindings/clock/google,gs101.h | 81 +++++++++++++++++++
2 files changed, 104 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
index ca7fdada3ff2..03698cdecf7a 100644
--- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
@@ -30,14 +30,15 @@ properties:
- google,gs101-cmu-top
- google,gs101-cmu-apm
- google,gs101-cmu-misc
+ - google,gs101-cmu-peric0
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 3
clock-names:
minItems: 1
- maxItems: 2
+ maxItems: 3
"#clock-cells":
const: 1
@@ -88,6 +89,26 @@ allOf:
- const: bus
- const: sss
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: google,gs101-cmu-peric0
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (24.576 MHz)
+ - description: Connectivity Peripheral 0 bus clock (from CMU_TOP)
+ - description: Connectivity Peripheral 0 IP clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: bus
+ - const: ip
+
additionalProperties: false
examples:
diff --git a/include/dt-bindings/clock/google,gs101.h b/include/dt-bindings/clock/google,gs101.h
index 21adec22387c..64e6bdc6359c 100644
--- a/include/dt-bindings/clock/google,gs101.h
+++ b/include/dt-bindings/clock/google,gs101.h
@@ -389,4 +389,85 @@
#define CLK_GOUT_MISC_WDT_CLUSTER1_PCLK 73
#define CLK_GOUT_MISC_XIU_D_MISC_ACLK 74
+/* CMU_PERIC0 */
+#define CLK_MOUT_PERIC0_BUS_USER 1
+#define CLK_MOUT_PERIC0_I3C_USER 2
+#define CLK_MOUT_PERIC0_USI0_UART_USER 3
+#define CLK_MOUT_PERIC0_USI14_USI_USER 4
+#define CLK_MOUT_PERIC0_USI1_USI_USER 5
+#define CLK_MOUT_PERIC0_USI2_USI_USER 6
+#define CLK_MOUT_PERIC0_USI3_USI_USER 7
+#define CLK_MOUT_PERIC0_USI4_USI_USER 8
+#define CLK_MOUT_PERIC0_USI5_USI_USER 9
+#define CLK_MOUT_PERIC0_USI6_USI_USER 10
+#define CLK_MOUT_PERIC0_USI7_USI_USER 11
+#define CLK_MOUT_PERIC0_USI8_USI_USER 12
+#define CLK_DOUT_PERIC0_I3C 13
+#define CLK_DOUT_PERIC0_USI0_UART 14
+#define CLK_DOUT_PERIC0_USI14_USI 15
+#define CLK_DOUT_PERIC0_USI1_USI 16
+#define CLK_DOUT_PERIC0_USI2_USI 17
+#define CLK_DOUT_PERIC0_USI3_USI 18
+#define CLK_DOUT_PERIC0_USI4_USI 19
+#define CLK_DOUT_PERIC0_USI5_USI 20
+#define CLK_DOUT_PERIC0_USI6_USI 21
+#define CLK_DOUT_PERIC0_USI7_USI 22
+#define CLK_DOUT_PERIC0_USI8_USI 23
+#define CLK_GOUT_PERIC0_IP 24
+#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 25
+#define CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK 26
+#define CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK 27
+#define CLK_GOUT_PERIC0_GPC_PERIC0_PCLK 28
+#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 29
+#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 30
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0 31
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1 32
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10 33
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11 34
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12 35
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13 36
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14 37
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15 38
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2 39
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3 40
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4 41
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5 42
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6 43
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7 44
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8 45
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9 46
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0 47
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1 48
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10 49
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11 50
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12 51
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13 52
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14 53
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15 54
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2 55
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3 56
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4 57
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5 58
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6 59
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7 60
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8 61
+#define CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9 62
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0 63
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2 64
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0 65
+#define CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2 66
+#define CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK 67
+#define CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK 68
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK 69
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK 70
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK 71
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK 72
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK 73
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK 74
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK 75
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK 76
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK 77
+#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK 78
+#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 79
+
#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */
--
2.43.0.472.g3155946c3a-goog
All gs101 serial ports are restricted to 32-bit register accesses.
This requirement will be inferred from the compatible. Do not allow
the reg-io-width property for the google,gs101-uart compatible.
Suggested-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3: collect Peter's R-b tag
v2: new patch
Documentation/devicetree/bindings/serial/samsung_uart.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
index 133259ed3a34..0f0131026911 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
@@ -143,6 +143,8 @@ allOf:
then:
required:
- samsung,uart-fifosize
+ properties:
+ reg-io-width: false
unevaluatedProperties: false
--
2.43.0.472.g3155946c3a-goog
Add google,gs101-hsi2c dedicated compatible for representing
I2C of Google GS101 SoC.
Acked-by: Wolfram Sang <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3: collect Peter's tag
v2: collect tags
Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
index df9c57bca2a8..cc8bba5537b9 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
+++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml
@@ -33,6 +33,7 @@ properties:
- const: samsung,exynos7-hsi2c
- items:
- enum:
+ - google,gs101-hsi2c
- samsung,exynos850-hsi2c
- const: samsung,exynosautov9-hsi2c
- const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420
--
2.43.0.472.g3155946c3a-goog
GS101's Connectivity Peripheral blocks (peric0/1 blocks) which
include the I3C and USI (I2C, SPI, UART) only allow 32-bit
register accesses. If using 8-bit register accesses, a SError
Interrupt is raised causing the system unusable.
Instead of specifying the reg-io-width = 4 everywhere, for each node,
the requirement should be deduced from the compatible.
Prepare the samsung tty driver to allow IO types different than
UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all
its 8 bits are exposed to uapi. We can't make NULL checks on it to
verify if it's set, thus always set it from the driver's data.
Use u8 for the ``iotype`` member of ``struct s3c24xx_uart_info`` to
emphasize that the iotype is an 8 bit mask.
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3:
- reposition the ``iotype`` member of ``struct s3c24xx_uart_info`` so
that we reduce the struct's memory footprint.
- change ``iotype`` to u8 to emphasize that it's a 8 bit mask and update
the commit message explaining why.
v2: new patch
drivers/tty/serial/samsung_tty.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index 66bd6c090ace..ff646cddd3f8 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -84,6 +84,7 @@ struct s3c24xx_uart_info {
unsigned long clksel_mask;
unsigned long clksel_shift;
unsigned long ucon_mask;
+ u8 iotype;
/* uart port features */
@@ -1742,7 +1743,6 @@ static void s3c24xx_serial_init_port_default(int index) {
spin_lock_init(&port->lock);
- port->iotype = UPIO_MEM;
port->uartclk = 0;
port->fifosize = 16;
port->flags = UPF_BOOT_AUTOCONF;
@@ -1989,6 +1989,8 @@ static int s3c24xx_serial_probe(struct platform_device *pdev)
break;
}
+ ourport->port.iotype = ourport->info->iotype;
+
if (np) {
of_property_read_u32(np,
"samsung,uart-fifosize", &ourport->port.fifosize);
@@ -2401,6 +2403,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
.name = "Samsung S3C6400 UART",
.type = TYPE_S3C6400,
.port_type = PORT_S3C6400,
+ .iotype = UPIO_MEM,
.fifosize = 64,
.has_divslot = 1,
.rx_fifomask = S3C2440_UFSTAT_RXMASK,
@@ -2430,6 +2433,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
.name = "Samsung S5PV210 UART",
.type = TYPE_S3C6400,
.port_type = PORT_S3C6400,
+ .iotype = UPIO_MEM,
.has_divslot = 1,
.rx_fifomask = S5PV210_UFSTAT_RXMASK,
.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
@@ -2459,6 +2463,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
.name = "Samsung Exynos UART", \
.type = TYPE_S3C6400, \
.port_type = PORT_S3C6400, \
+ .iotype = UPIO_MEM, \
.has_divslot = 1, \
.rx_fifomask = S5PV210_UFSTAT_RXMASK, \
.rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
@@ -2519,6 +2524,7 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
.name = "Apple S5L UART",
.type = TYPE_APPLE_S5L,
.port_type = PORT_8250,
+ .iotype = UPIO_MEM,
.fifosize = 16,
.rx_fifomask = S3C2410_UFSTAT_RXMASK,
.rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
@@ -2548,6 +2554,7 @@ static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
.name = "Axis ARTPEC-8 UART",
.type = TYPE_S3C6400,
.port_type = PORT_S3C6400,
+ .iotype = UPIO_MEM,
.fifosize = 64,
.has_divslot = 1,
.rx_fifomask = S5PV210_UFSTAT_RXMASK,
--
2.43.0.472.g3155946c3a-goog
GS101's Connectivity Peripheral blocks (peric0/1 blocks) which
include the I3C and USI (I2C, SPI, UART) only allow 32-bit
register accesses.
Instead of specifying the reg-io-width = 4 everywhere, for each node,
the requirement should be deduced from the compatible.
Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible.
Update the uart info name to be GS101 specific in order to
differentiate from the other exynos platforms. All the other settings
are not changed.
exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data
because the iotype restriction is gs101 specific and there was no other
user of exynos_fifoszdt_serial_drv_data.
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3: collect Peter's R-b tag
v2: new patch
drivers/tty/serial/samsung_tty.c | 38 +++++++++++++++++++++++---------
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index ff646cddd3f8..a81b61953a28 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -2497,25 +2497,43 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
.fifosize = { 256, 64, 64, 64 },
};
-/*
- * Common drv_data struct for platforms that specify samsung,uart-fifosize in
- * device tree.
- */
-static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = {
- EXYNOS_COMMON_SERIAL_DRV_DATA(),
+static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
+ .info = {
+ .name = "Google GS101 UART",
+ .type = TYPE_S3C6400,
+ .port_type = PORT_S3C6400,
+ .iotype = UPIO_MEM32,
+ .has_divslot = 1,
+ .rx_fifomask = S5PV210_UFSTAT_RXMASK,
+ .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
+ .rx_fifofull = S5PV210_UFSTAT_RXFULL,
+ .tx_fifofull = S5PV210_UFSTAT_TXFULL,
+ .tx_fifomask = S5PV210_UFSTAT_TXMASK,
+ .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
+ .def_clk_sel = S3C2410_UCON_CLKSEL0,
+ .num_clks = 1,
+ .clksel_mask = 0,
+ .clksel_shift = 0,
+ },
+ .def_cfg = {
+ .ucon = S5PV210_UCON_DEFAULT,
+ .ufcon = S5PV210_UFCON_DEFAULT,
+ .has_fracval = 1,
+ },
+ /* samsung,uart-fifosize must be specified in the device tree. */
.fifosize = { 0 },
};
#define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
#define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
#define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
-#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data)
+#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
#else
#define EXYNOS4210_SERIAL_DRV_DATA NULL
#define EXYNOS5433_SERIAL_DRV_DATA NULL
#define EXYNOS850_SERIAL_DRV_DATA NULL
-#define EXYNOS_FIFOSZDT_DRV_DATA NULL
+#define GS101_SERIAL_DRV_DATA NULL
#endif
#ifdef CONFIG_ARCH_APPLE
@@ -2603,7 +2621,7 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
.driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
}, {
.name = "gs101-uart",
- .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA,
+ .driver_data = (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
},
{ },
};
@@ -2626,7 +2644,7 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
{ .compatible = "axis,artpec8-uart",
.data = ARTPEC8_SERIAL_DRV_DATA },
{ .compatible = "google,gs101-uart",
- .data = EXYNOS_FIFOSZDT_DRV_DATA },
+ .data = GS101_SERIAL_DRV_DATA },
{},
};
MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
--
2.43.0.472.g3155946c3a-goog
The entire bus (PERIC) on which the GS101 serial resides only allows
32-bit register accesses. The reg-io-width dt property is disallowed
for the "google,gs101-uart" compatible and instead the iotype is
inferred from the compatible. Always set UPIO_MEM32 iotype for the
gs101 earlycon.
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3: collect Peter's R-b tag
v2: update commit message
drivers/tty/serial/samsung_tty.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
index a81b61953a28..fed50423b7c1 100644
--- a/drivers/tty/serial/samsung_tty.c
+++ b/drivers/tty/serial/samsung_tty.c
@@ -2812,6 +2812,17 @@ OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
s5pv210_early_console_setup);
+static int __init gs101_early_console_setup(struct earlycon_device *device,
+ const char *opt)
+{
+ /* gs101 always expects MMIO32 register accesses. */
+ device->port.iotype = UPIO_MEM32;
+
+ return s5pv210_early_console_setup(device, opt);
+}
+
+OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup);
+
/* Apple S5L */
static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
const char *opt)
--
2.43.0.472.g3155946c3a-goog
Enable the cmu-peric0 clock controller. It feeds USI and I3c.
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3:
- comply with the renamed cmu_peric0 clock names, "bus" and "ip"
- collect Peter's R-b tag
v2: collect Sam's R-b tag
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 4e5f4c748906..2d1344a202a9 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -339,6 +339,16 @@ ppi_cluster2: interrupt-partition-2 {
};
};
+ cmu_peric0: clock-controller@10800000 {
+ compatible = "google,gs101-cmu-peric0";
+ reg = <0x10800000 0x4000>;
+ #clock-cells = <1>;
+ clocks = <&ext_24_5m>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
+ <&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
+ clock-names = "oscclk", "bus", "ip";
+ };
+
sysreg_peric0: syscon@10820000 {
compatible = "google,gs101-peric0-sysreg", "syscon";
reg = <0x10820000 0x10000>;
--
2.43.0.472.g3155946c3a-goog
CMU_PERIC0 is the clock management unit used for the peric0 block which
is used for USI and I3C. Add support for all cmu_peric0 clocks but
CLK_GOUT_PERIC0_IP (not enough info in the datasheet).
Few clocks are marked as critical because when either of them is
disabled, the system hangs even if their clock parents are enabled.
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3:
- comply with the renamed cmu_peric0 clock name: "bus"
- collect Peter's R-b tag
v2:
- update commit message
- identify and mark critical clocks
drivers/clk/samsung/clk-gs101.c | 583 ++++++++++++++++++++++++++++++++
1 file changed, 583 insertions(+)
diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
index 782993951fff..f3f0f5feb28d 100644
--- a/drivers/clk/samsung/clk-gs101.c
+++ b/drivers/clk/samsung/clk-gs101.c
@@ -20,6 +20,7 @@
#define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
#define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
#define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
+#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
@@ -2478,6 +2479,585 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = {
.clk_name = "bus",
};
+/* ---- CMU_PERIC0 ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_PERIC0 (0x10800000) */
+#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
+#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604
+#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610
+#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4
+#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0
+#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4
+#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800
+#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810
+#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830
+#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834
+#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000
+#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004
+#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4
+#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8
+#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000
+#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004
+#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008
+#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c
+#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010
+#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014
+#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018
+#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c
+#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020
+#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024
+#define QCH_CON_GPC_PERIC0_QCH 0x3028
+#define QCH_CON_GPIO_PERIC0_QCH 0x302c
+#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030
+#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034
+#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038
+#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c
+#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040
+#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044
+#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048
+#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c
+#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050
+#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054
+#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058
+#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c
+#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060
+#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064
+#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068
+#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c
+#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070
+#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074
+#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078
+#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c
+#define QCH_CON_SYSREG_PERIC0_QCH 0x3080
+#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00
+
+static const unsigned long peric0_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER,
+ PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER,
+ PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
+ CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0,
+ CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI,
+ CLK_CON_BUF_CLKBUF_PERIC0_IP,
+ CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
+ CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
+ DMYQCH_CON_PERIC0_TOP0_QCH_S1,
+ DMYQCH_CON_PERIC0_TOP0_QCH_S2,
+ DMYQCH_CON_PERIC0_TOP0_QCH_S3,
+ DMYQCH_CON_PERIC0_TOP0_QCH_S4,
+ DMYQCH_CON_PERIC0_TOP0_QCH_S5,
+ DMYQCH_CON_PERIC0_TOP0_QCH_S6,
+ DMYQCH_CON_PERIC0_TOP0_QCH_S7,
+ DMYQCH_CON_PERIC0_TOP0_QCH_S8,
+ PCH_CON_LHM_AXI_P_PERIC0_PCH,
+ QCH_CON_D_TZPC_PERIC0_QCH,
+ QCH_CON_GPC_PERIC0_QCH,
+ QCH_CON_GPIO_PERIC0_QCH,
+ QCH_CON_LHM_AXI_P_PERIC0_QCH,
+ QCH_CON_PERIC0_CMU_PERIC0_QCH,
+ QCH_CON_PERIC0_TOP0_QCH_I3C1,
+ QCH_CON_PERIC0_TOP0_QCH_I3C2,
+ QCH_CON_PERIC0_TOP0_QCH_I3C3,
+ QCH_CON_PERIC0_TOP0_QCH_I3C4,
+ QCH_CON_PERIC0_TOP0_QCH_I3C5,
+ QCH_CON_PERIC0_TOP0_QCH_I3C6,
+ QCH_CON_PERIC0_TOP0_QCH_I3C7,
+ QCH_CON_PERIC0_TOP0_QCH_I3C8,
+ QCH_CON_PERIC0_TOP0_QCH_USI1_USI,
+ QCH_CON_PERIC0_TOP0_QCH_USI2_USI,
+ QCH_CON_PERIC0_TOP0_QCH_USI3_USI,
+ QCH_CON_PERIC0_TOP0_QCH_USI4_USI,
+ QCH_CON_PERIC0_TOP0_QCH_USI5_USI,
+ QCH_CON_PERIC0_TOP0_QCH_USI6_USI,
+ QCH_CON_PERIC0_TOP0_QCH_USI7_USI,
+ QCH_CON_PERIC0_TOP0_QCH_USI8_USI,
+ QCH_CON_PERIC0_TOP1_QCH_USI0_UART,
+ QCH_CON_PERIC0_TOP1_QCH_USI14_UART,
+ QCH_CON_SYSREG_PERIC0_QCH,
+ QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0,
+};
+
+/* List of parent clocks for Muxes in CMU_PERIC0 */
+PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
+PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
+PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
+PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
+
+static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
+ mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user",
+ mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI0_UART_USER,
+ "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI14_USI_USER,
+ "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI1_USI_USER,
+ "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI2_USI_USER,
+ "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI3_USI_USER,
+ "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI4_USI_USER,
+ "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI5_USI_USER,
+ "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI6_USI_USER,
+ "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI7_USI_USER,
+ "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
+ MUX(CLK_MOUT_PERIC0_USI8_USI_USER,
+ "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
+ PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
+};
+
+static const struct samsung_div_clock peric0_div_clks[] __initconst = {
+ DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI0_UART,
+ "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI14_USI,
+ "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI1_USI,
+ "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI2_USI,
+ "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI3_USI,
+ "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI4_USI,
+ "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI5_USI,
+ "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI6_USI,
+ "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI7_USI,
+ "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 3),
+ DIV(CLK_DOUT_PERIC0_USI8_USI,
+ "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
+ CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 3),
+};
+
+static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
+ /* Disabling this clock makes the system hang. Mark the clock as critical. */
+ GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
+ "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user",
+ CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
+ 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK,
+ "gout_peric0_clk_peric0_oscclk_clk", "oscclk",
+ CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK,
+ "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK,
+ "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK,
+ "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
+ 21, 0, 0),
+ /* Disabling this clock makes the system hang. Mark the clock as critical. */
+ GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK,
+ "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
+ 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
+ "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
+ "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
+ "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11,
+ "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12,
+ "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13,
+ "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14,
+ "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15,
+ "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
+ "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
+ "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
+ "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
+ "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
+ "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
+ "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
+ "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9,
+ "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0,
+ "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1,
+ "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10,
+ "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11,
+ "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12,
+ "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13,
+ "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14,
+ "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15,
+ "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2,
+ "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3,
+ "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4,
+ "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5,
+ "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6,
+ "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7,
+ "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8,
+ "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9,
+ "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
+ 21, 0, 0),
+ /* Disabling this clock makes the system hang. Mark the clock as critical. */
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0,
+ "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
+ 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
+ "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
+ 21, 0, 0),
+ /* Disabling this clock makes the system hang. Mark the clock as critical. */
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
+ "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
+ 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2,
+ "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK,
+ "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK,
+ "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK,
+ "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK,
+ "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK,
+ "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK,
+ "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK,
+ "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK,
+ "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK,
+ "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK,
+ "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK,
+ "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK,
+ "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK,
+ "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user",
+ CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info peric0_cmu_info __initconst = {
+ .mux_clks = peric0_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
+ .div_clks = peric0_div_clks,
+ .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
+ .gate_clks = peric0_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
+ .nr_clk_ids = CLKS_NR_PERIC0,
+ .clk_regs = peric0_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
+ .clk_name = "bus",
+};
+
/* ---- platform_driver ----------------------------------------------------- */
static int __init gs101_cmu_probe(struct platform_device *pdev)
@@ -2498,6 +3078,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
}, {
.compatible = "google,gs101-cmu-misc",
.data = &misc_cmu_info,
+ }, {
+ .compatible = "google,gs101-cmu-peric0",
+ .data = &peric0_cmu_info,
}, {
},
};
--
2.43.0.472.g3155946c3a-goog
Remove the reg-io-width property in order to comply with the bindings.
The entire bus (PERIC) on which the GS101 serial resides only allows
32-bit register accesses. The reg-io-width dt property is disallowed
for the "google,gs101-uart" compatible and instead the iotype is
inferred from the compatible.
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3: collect Peter's R-b tag
v2: new patch
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index d838e3a7af6e..4e5f4c748906 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -366,7 +366,6 @@ usi_uart: usi@10a000c0 {
serial_0: serial@10a00000 {
compatible = "google,gs101-uart";
reg = <0x10a00000 0xc0>;
- reg-io-width = <4>;
interrupts = <GIC_SPI 634
IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&dummy_clk 0>, <&dummy_clk 0>;
--
2.43.0.472.g3155946c3a-goog
Get rid of the dummy clock and start using the cmu_peric0 clocks
for the usi_uart and serial_0 nodes.
Tested the serial at 115200, 1000000 and 3000000 baudrates,
everthing went fine.
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3: no change
v2: identify and use gate clocks instead of divider clocks
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++----------
1 file changed, 4 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 2d1344a202a9..6aa25cc4676e 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -180,14 +180,6 @@ HERA_CPU_SLEEP: cpu-hera-sleep {
};
};
- /* TODO replace with CCF clock */
- dummy_clk: clock-3 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12345>;
- clock-output-names = "pclk";
- };
-
/* ect node is required to be present by bootloader */
ect {
};
@@ -367,7 +359,8 @@ usi_uart: usi@10a000c0 {
ranges;
#address-cells = <1>;
#size-cells = <1>;
- clocks = <&dummy_clk>, <&dummy_clk>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
clock-names = "pclk", "ipclk";
samsung,sysreg = <&sysreg_peric0 0x1020>;
samsung,mode = <USI_V2_UART>;
@@ -378,7 +371,8 @@ serial_0: serial@10a00000 {
reg = <0x10a00000 0xc0>;
interrupts = <GIC_SPI 634
IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&dummy_clk 0>, <&dummy_clk 0>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
clock-names = "uart", "clk_uart_baud0";
samsung,uart-fifosize = <256>;
status = "disabled";
--
2.43.0.472.g3155946c3a-goog
Enable the eeprom found on the battery connector.
The selection of the USI protocol is done in the board dts file because
the USI CONFIG register comes with a 0x0 reset value, meaning that USI8
does not have a default protocol (I2C, SPI, UART) at reset.
Reviewed-by: Sam Protsenko <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3: collect Peter's R-b tag
v2:
- move cells and pinctrls properties to dtsi
- collect Sam's R-b
arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
index 4a71f752200d..cb4d17339b6b 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
+++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
@@ -63,6 +63,15 @@ &ext_200m {
clock-frequency = <200000000>;
};
+&hsi2c_8 {
+ status = "okay";
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c08";
+ reg = <0x50>;
+ };
+};
+
&pinctrl_far_alive {
key_voldown: key-voldown-pins {
samsung,pins = "gpa7-3";
@@ -99,6 +108,11 @@ &usi_uart {
status = "okay";
};
+&usi8 {
+ samsung,mode = <USI_V2_I2C>;
+ status = "okay";
+};
+
&watchdog_cl0 {
timeout-sec = <30>;
status = "okay";
--
2.43.0.472.g3155946c3a-goog
USI8 I2C is used to communicate with an eeprom found on the battery
connector. Define USI8 in I2C configuration.
USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
selection of the protocol is intentionally left for the board dts file.
Signed-off-by: Tudor Ambarus <[email protected]>
---
v3: reorder usi8 clock order (thanks Andre'!). Did not make any
difference at testing as the usi driver treats the clocks in bulk.
v2:
- identify and use gate clocks instead of dividers
- move cells and pinctrl properties from dts to dtsi
- move IRQ type constant on the previous line
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 6aa25cc4676e..f14a24628d04 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 {
interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ usi8: usi@109700c0 {
+ compatible = "google,gs101-usi",
+ "samsung,exynos850-usi";
+ reg = <0x109700c0 0x20>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>;
+ clock-names = "pclk", "ipclk";
+ samsung,sysreg = <&sysreg_peric0 0x101c>;
+ status = "disabled";
+
+ hsi2c_8: i2c@10970000 {
+ compatible = "google,gs101-hsi2c",
+ "samsung,exynosautov9-hsi2c";
+ reg = <0x10970000 0xc0>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hsi2c8_bus>;
+ clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>,
+ <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>;
+ clock-names = "hsi2c", "hsi2c_pclk";
+ status = "disabled";
+ };
+ };
+
usi_uart: usi@10a000c0 {
compatible = "google,gs101-usi",
"samsung,exynos850-usi";
--
2.43.0.472.g3155946c3a-goog
On 09/01/2024 13:58, Tudor Ambarus wrote:
> Add google,gs101-hsi2c dedicated compatible for representing
> I2C of Google GS101 SoC.
>
> Acked-by: Wolfram Sang <[email protected]>
OK, I will take it but in general this should not go via SoC tree, but
I2C. GS101 was already merged, so please send all your future
submissions regular way.
Best regards,
Krzysztof
On 09/01/2024 13:58, Tudor Ambarus wrote:
> All gs101 serial ports are restricted to 32-bit register accesses.
> This requirement will be inferred from the compatible. Do not allow
> the reg-io-width property for the google,gs101-uart compatible.
>
> Suggested-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Peter Griffin <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
> v3: collect Peter's R-b tag
> v2: new patch
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Please split the serial patches into separate patchset and send them
usual way, so Greg can pick them up. GS101 was merged, thus this is not
initial submission anymore.
Best regards,
Krzysztof
On 09/01/2024 13:58, Tudor Ambarus wrote:
> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which
> include the I3C and USI (I2C, SPI, UART) only allow 32-bit
> register accesses. If using 8-bit register accesses, a SError
> Interrupt is raised causing the system unusable.
>
> Instead of specifying the reg-io-width = 4 everywhere, for each node,
> the requirement should be deduced from the compatible.
>
> Prepare the samsung tty driver to allow IO types different than
> UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all
> its 8 bits are exposed to uapi. We can't make NULL checks on it to
> verify if it's set, thus always set it from the driver's data.
> Use u8 for the ``iotype`` member of ``struct s3c24xx_uart_info`` to
> emphasize that the iotype is an 8 bit mask.
>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 09/01/2024 13:58, Tudor Ambarus wrote:
> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which
> include the I3C and USI (I2C, SPI, UART) only allow 32-bit
> register accesses.
>
> Instead of specifying the reg-io-width = 4 everywhere, for each node,
> the requirement should be deduced from the compatible.
>
> Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible.
> Update the uart info name to be GS101 specific in order to
> differentiate from the other exynos platforms. All the other settings
> are not changed.
>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 09/01/2024 13:58, Tudor Ambarus wrote:
> The entire bus (PERIC) on which the GS101 serial resides only allows
> 32-bit register accesses. The reg-io-width dt property is disallowed
> for the "google,gs101-uart" compatible and instead the iotype is
> inferred from the compatible. Always set UPIO_MEM32 iotype for the
> gs101 earlycon.
>
> Reviewed-by: Peter Griffin <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
> v3: collect Peter's R-b tag
> v2: update commit message
>
> drivers/tty/serial/samsung_tty.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 1/10/24 08:06, Krzysztof Kozlowski wrote:
> On 09/01/2024 13:58, Tudor Ambarus wrote:
>> All gs101 serial ports are restricted to 32-bit register accesses.
>> This requirement will be inferred from the compatible. Do not allow
>> the reg-io-width property for the google,gs101-uart compatible.
>>
>> Suggested-by: Krzysztof Kozlowski <[email protected]>
>> Reviewed-by: Peter Griffin <[email protected]>
>> Signed-off-by: Tudor Ambarus <[email protected]>
>> ---
>> v3: collect Peter's R-b tag
>> v2: new patch
>>
>
>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
>
> Please split the serial patches into separate patchset and send them
> usual way, so Greg can pick them up. GS101 was merged, thus this is not
> initial submission anymore.
>
Got it, will do. Thanks.
ta
On Tue, 09 Jan 2024 12:58:03 +0000, Tudor Ambarus wrote:
> Add dt-schema documentation for the Connectivity Peripheral 0 (PERIC0)
> clock management unit.
>
> Reviewed-by: Sam Protsenko <[email protected]>
> Reviewed-by: Peter Griffin <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
> v3:
> - rename the clock names to just "bus" and "ip" as per Rob's suggestion
> - collect Peter's R-b tag
>
> v2:
> - fix comments as per Sam's suggestion and collect his R-b tag
> - Rob's suggestion of renaming the clock-names to just "bus" and "ip"
> was not implemented as I felt it affects readability in the driver
> and consistency with other exynos clock drivers. I will happily update
> the names in the -rc phase if someone else has a stronger opinion than
> mine.
>
> .../bindings/clock/google,gs101-clock.yaml | 25 +++++-
> include/dt-bindings/clock/google,gs101.h | 81 +++++++++++++++++++
> 2 files changed, 104 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, Jan 9, 2024 at 7:00 AM Tudor Ambarus <[email protected]> wrote:
>
> CMU_PERIC0 is the clock management unit used for the peric0 block which
> is used for USI and I3C. Add support for all cmu_peric0 clocks but
> CLK_GOUT_PERIC0_IP (not enough info in the datasheet).
>
> Few clocks are marked as critical because when either of them is
> disabled, the system hangs even if their clock parents are enabled.
>
> Reviewed-by: Peter Griffin <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
> v3:
> - comply with the renamed cmu_peric0 clock name: "bus"
> - collect Peter's R-b tag
> v2:
> - update commit message
> - identify and mark critical clocks
>
> drivers/clk/samsung/clk-gs101.c | 583 ++++++++++++++++++++++++++++++++
> 1 file changed, 583 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index 782993951fff..f3f0f5feb28d 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -20,6 +20,7 @@
> #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
> #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
> #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> +#define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -2478,6 +2479,585 @@ static const struct samsung_cmu_info misc_cmu_info __initconst = {
> .clk_name = "bus",
> };
>
> +/* ---- CMU_PERIC0 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_PERIC0 (0x10800000) */
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4
> +#define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0
> +#define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4
> +#define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830
> +#define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834
> +#define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000
> +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004
> +#define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4
> +#define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8
> +#define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000
> +#define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004
> +#define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008
> +#define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c
> +#define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010
> +#define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014
> +#define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018
> +#define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c
> +#define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020
> +#define QCH_CON_D_TZPC_PERIC0_QCH 0x3024
> +#define QCH_CON_GPC_PERIC0_QCH 0x3028
> +#define QCH_CON_GPIO_PERIC0_QCH 0x302c
> +#define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030
> +#define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034
> +#define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038
> +#define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c
> +#define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040
> +#define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044
> +#define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048
> +#define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c
> +#define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050
> +#define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054
> +#define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058
> +#define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c
> +#define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060
> +#define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064
> +#define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068
> +#define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c
> +#define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070
> +#define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074
> +#define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078
> +#define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c
> +#define QCH_CON_SYSREG_PERIC0_QCH 0x3080
> +#define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00
> +
> +static const unsigned long peric0_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER,
> + PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER,
> + PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
> + CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0,
> + CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI,
> + CLK_CON_BUF_CLKBUF_PERIC0_IP,
> + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
> + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
> + DMYQCH_CON_PERIC0_TOP0_QCH_S1,
> + DMYQCH_CON_PERIC0_TOP0_QCH_S2,
> + DMYQCH_CON_PERIC0_TOP0_QCH_S3,
> + DMYQCH_CON_PERIC0_TOP0_QCH_S4,
> + DMYQCH_CON_PERIC0_TOP0_QCH_S5,
> + DMYQCH_CON_PERIC0_TOP0_QCH_S6,
> + DMYQCH_CON_PERIC0_TOP0_QCH_S7,
> + DMYQCH_CON_PERIC0_TOP0_QCH_S8,
> + PCH_CON_LHM_AXI_P_PERIC0_PCH,
> + QCH_CON_D_TZPC_PERIC0_QCH,
> + QCH_CON_GPC_PERIC0_QCH,
> + QCH_CON_GPIO_PERIC0_QCH,
> + QCH_CON_LHM_AXI_P_PERIC0_QCH,
> + QCH_CON_PERIC0_CMU_PERIC0_QCH,
> + QCH_CON_PERIC0_TOP0_QCH_I3C1,
> + QCH_CON_PERIC0_TOP0_QCH_I3C2,
> + QCH_CON_PERIC0_TOP0_QCH_I3C3,
> + QCH_CON_PERIC0_TOP0_QCH_I3C4,
> + QCH_CON_PERIC0_TOP0_QCH_I3C5,
> + QCH_CON_PERIC0_TOP0_QCH_I3C6,
> + QCH_CON_PERIC0_TOP0_QCH_I3C7,
> + QCH_CON_PERIC0_TOP0_QCH_I3C8,
> + QCH_CON_PERIC0_TOP0_QCH_USI1_USI,
> + QCH_CON_PERIC0_TOP0_QCH_USI2_USI,
> + QCH_CON_PERIC0_TOP0_QCH_USI3_USI,
> + QCH_CON_PERIC0_TOP0_QCH_USI4_USI,
> + QCH_CON_PERIC0_TOP0_QCH_USI5_USI,
> + QCH_CON_PERIC0_TOP0_QCH_USI6_USI,
> + QCH_CON_PERIC0_TOP0_QCH_USI7_USI,
> + QCH_CON_PERIC0_TOP0_QCH_USI8_USI,
> + QCH_CON_PERIC0_TOP1_QCH_USI0_UART,
> + QCH_CON_PERIC0_TOP1_QCH_USI14_UART,
> + QCH_CON_SYSREG_PERIC0_QCH,
> + QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_PERIC0 */
> +PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
> +PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
> +PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
> +PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
> +
> +static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
> + mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user",
> + mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI0_UART_USER,
> + "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI14_USI_USER,
> + "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI1_USI_USER,
> + "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI2_USI_USER,
> + "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI3_USI_USER,
> + "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI4_USI_USER,
> + "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI5_USI_USER,
> + "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI6_USI_USER,
> + "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI7_USI_USER,
> + "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
> + MUX(CLK_MOUT_PERIC0_USI8_USI_USER,
> + "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
> + PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
> +};
> +
> +static const struct samsung_div_clock peric0_div_clks[] __initconst = {
> + DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI0_UART,
> + "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI14_USI,
> + "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI1_USI,
> + "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI2_USI,
> + "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI3_USI,
> + "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI4_USI,
> + "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI5_USI,
> + "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI6_USI,
> + "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI7_USI,
> + "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 3),
> + DIV(CLK_DOUT_PERIC0_USI8_USI,
> + "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
> + CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 3),
> +};
> +
> +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
> + /* Disabling this clock makes the system hang. Mark the clock as critical. */
> + GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
> + "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user",
> + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
> + 21, CLK_IS_CRITICAL, 0),
Why not just CLK_IGNORE_UNUSED? As I understand this gate clock can be
used to disable PCLK (bus clock) provided to the whole CMU_PERIC0.
Aren't there any valid cases for disabling this clock, like during
some PM transitions? For Exynos850 clock driver I marked all clocks of
this kind as CLK_IGNORE_UNUSED and it works fine. In other words: I'd
say CLK_IS_CRITICAL flag is more "strong" than CLK_IGNORE_UNUSED, and
requires better and more specific explanation, to make sure we are not
abusing it. And I'm not sure this is the case.
The same goes for the rest of clocks marked as CLK_IS_CRITICAL in this
patch. Please check if maybe using CLK_IGNORE_UNUSED makes sense for
any of those as well.
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK,
> + "gout_peric0_clk_peric0_oscclk_clk", "oscclk",
> + CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK,
> + "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK,
> + "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK,
> + "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
> + 21, 0, 0),
> + /* Disabling this clock makes the system hang. Mark the clock as critical. */
> + GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK,
> + "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
> + 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
> + "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
> + "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
> + "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11,
> + "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12,
> + "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13,
> + "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14,
> + "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15,
> + "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
> + "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
> + "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
> + "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
> + "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
> + "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
> + "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
> + "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9,
> + "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0,
> + "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1,
> + "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10,
> + "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11,
> + "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12,
> + "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13,
> + "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14,
> + "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15,
> + "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2,
> + "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3,
> + "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4,
> + "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5,
> + "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6,
> + "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7,
> + "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8,
> + "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9,
> + "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
> + 21, 0, 0),
> + /* Disabling this clock makes the system hang. Mark the clock as critical. */
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0,
> + "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
> + 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
> + "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
> + 21, 0, 0),
> + /* Disabling this clock makes the system hang. Mark the clock as critical. */
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
> + "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
> + 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2,
> + "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK,
> + "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK,
> + "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK,
> + "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK,
> + "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK,
> + "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK,
> + "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK,
> + "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK,
> + "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK,
> + "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK,
> + "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK,
> + "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK,
> + "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK,
> + "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user",
> + CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info peric0_cmu_info __initconst = {
> + .mux_clks = peric0_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
> + .div_clks = peric0_div_clks,
> + .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
> + .gate_clks = peric0_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
> + .nr_clk_ids = CLKS_NR_PERIC0,
> + .clk_regs = peric0_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
> + .clk_name = "bus",
> +};
> +
> /* ---- platform_driver ----------------------------------------------------- */
>
> static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -2498,6 +3078,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> }, {
> .compatible = "google,gs101-cmu-misc",
> .data = &misc_cmu_info,
> + }, {
> + .compatible = "google,gs101-cmu-peric0",
> + .data = &peric0_cmu_info,
> }, {
> },
> };
> --
> 2.43.0.472.g3155946c3a-goog
>
>
On Tue, Jan 9, 2024 at 6:59 AM Tudor Ambarus <[email protected]> wrote:
>
> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which
> include the I3C and USI (I2C, SPI, UART) only allow 32-bit
> register accesses. If using 8-bit register accesses, a SError
> Interrupt is raised causing the system unusable.
>
> Instead of specifying the reg-io-width = 4 everywhere, for each node,
> the requirement should be deduced from the compatible.
>
> Prepare the samsung tty driver to allow IO types different than
> UPIO_MEM. ``struct uart_port::iotype`` is an unsigned char where all
> its 8 bits are exposed to uapi. We can't make NULL checks on it to
> verify if it's set, thus always set it from the driver's data.
> Use u8 for the ``iotype`` member of ``struct s3c24xx_uart_info`` to
> emphasize that the iotype is an 8 bit mask.
>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> v3:
> - reposition the ``iotype`` member of ``struct s3c24xx_uart_info`` so
> that we reduce the struct's memory footprint.
> - change ``iotype`` to u8 to emphasize that it's a 8 bit mask and update
> the commit message explaining why.
> v2: new patch
>
> drivers/tty/serial/samsung_tty.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index 66bd6c090ace..ff646cddd3f8 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -84,6 +84,7 @@ struct s3c24xx_uart_info {
> unsigned long clksel_mask;
> unsigned long clksel_shift;
> unsigned long ucon_mask;
> + u8 iotype;
>
> /* uart port features */
>
> @@ -1742,7 +1743,6 @@ static void s3c24xx_serial_init_port_default(int index) {
>
> spin_lock_init(&port->lock);
>
> - port->iotype = UPIO_MEM;
> port->uartclk = 0;
> port->fifosize = 16;
> port->flags = UPF_BOOT_AUTOCONF;
> @@ -1989,6 +1989,8 @@ static int s3c24xx_serial_probe(struct platform_device *pdev)
> break;
> }
>
> + ourport->port.iotype = ourport->info->iotype;
> +
> if (np) {
> of_property_read_u32(np,
> "samsung,uart-fifosize", &ourport->port.fifosize);
> @@ -2401,6 +2403,7 @@ static const struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
> .name = "Samsung S3C6400 UART",
> .type = TYPE_S3C6400,
> .port_type = PORT_S3C6400,
> + .iotype = UPIO_MEM,
> .fifosize = 64,
> .has_divslot = 1,
> .rx_fifomask = S3C2440_UFSTAT_RXMASK,
> @@ -2430,6 +2433,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
> .name = "Samsung S5PV210 UART",
> .type = TYPE_S3C6400,
> .port_type = PORT_S3C6400,
> + .iotype = UPIO_MEM,
> .has_divslot = 1,
> .rx_fifomask = S5PV210_UFSTAT_RXMASK,
> .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
> @@ -2459,6 +2463,7 @@ static const struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
> .name = "Samsung Exynos UART", \
> .type = TYPE_S3C6400, \
> .port_type = PORT_S3C6400, \
> + .iotype = UPIO_MEM, \
> .has_divslot = 1, \
> .rx_fifomask = S5PV210_UFSTAT_RXMASK, \
> .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT, \
> @@ -2519,6 +2524,7 @@ static const struct s3c24xx_serial_drv_data s5l_serial_drv_data = {
> .name = "Apple S5L UART",
> .type = TYPE_APPLE_S5L,
> .port_type = PORT_8250,
> + .iotype = UPIO_MEM,
> .fifosize = 16,
> .rx_fifomask = S3C2410_UFSTAT_RXMASK,
> .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
> @@ -2548,6 +2554,7 @@ static const struct s3c24xx_serial_drv_data artpec8_serial_drv_data = {
> .name = "Axis ARTPEC-8 UART",
> .type = TYPE_S3C6400,
> .port_type = PORT_S3C6400,
> + .iotype = UPIO_MEM,
> .fifosize = 64,
> .has_divslot = 1,
> .rx_fifomask = S5PV210_UFSTAT_RXMASK,
> --
> 2.43.0.472.g3155946c3a-goog
>
>
On Tue, Jan 9, 2024 at 7:00 AM Tudor Ambarus <[email protected]> wrote:
>
> The entire bus (PERIC) on which the GS101 serial resides only allows
> 32-bit register accesses. The reg-io-width dt property is disallowed
> for the "google,gs101-uart" compatible and instead the iotype is
> inferred from the compatible. Always set UPIO_MEM32 iotype for the
> gs101 earlycon.
>
> Reviewed-by: Peter Griffin <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> v3: collect Peter's R-b tag
> v2: update commit message
>
> drivers/tty/serial/samsung_tty.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index a81b61953a28..fed50423b7c1 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -2812,6 +2812,17 @@ OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
> OF_EARLYCON_DECLARE(artpec8, "axis,artpec8-uart",
> s5pv210_early_console_setup);
>
> +static int __init gs101_early_console_setup(struct earlycon_device *device,
> + const char *opt)
> +{
> + /* gs101 always expects MMIO32 register accesses. */
> + device->port.iotype = UPIO_MEM32;
> +
> + return s5pv210_early_console_setup(device, opt);
> +}
> +
> +OF_EARLYCON_DECLARE(gs101, "google,gs101-uart", gs101_early_console_setup);
> +
> /* Apple S5L */
> static int __init apple_s5l_early_console_setup(struct earlycon_device *device,
> const char *opt)
> --
> 2.43.0.472.g3155946c3a-goog
>
>
On Tue, Jan 9, 2024 at 7:00 AM Tudor Ambarus <[email protected]> wrote:
>
> Remove the reg-io-width property in order to comply with the bindings.
>
> The entire bus (PERIC) on which the GS101 serial resides only allows
> 32-bit register accesses. The reg-io-width dt property is disallowed
> for the "google,gs101-uart" compatible and instead the iotype is
> inferred from the compatible.
>
> Reviewed-by: Peter Griffin <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
Just out of curiosity (I probably missed the relevant discussion
earlier): what is the actual reason for moving 'reg-io-width' to the
driver's code as 'iotype'? I mean, what is the actual problem that's
being solved by this -- is it to make the earlycon functional for
gs101? I'm asking because the bus width looks like a part of HW
description, which usually belongs to dts, from the design point of
view. Anyways, that's not a concern, just trying to understand the
decision.
> v3: collect Peter's R-b tag
> v2: new patch
>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index d838e3a7af6e..4e5f4c748906 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -366,7 +366,6 @@ usi_uart: usi@10a000c0 {
> serial_0: serial@10a00000 {
> compatible = "google,gs101-uart";
> reg = <0x10a00000 0xc0>;
> - reg-io-width = <4>;
> interrupts = <GIC_SPI 634
> IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> --
> 2.43.0.472.g3155946c3a-goog
>
>
On Tue, Jan 9, 2024 at 7:01 AM Tudor Ambarus <[email protected]> wrote:
>
> Get rid of the dummy clock and start using the cmu_peric0 clocks
> for the usi_uart and serial_0 nodes.
>
> Tested the serial at 115200, 1000000 and 3000000 baudrates,
> everthing went fine.
>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
> v3: no change
> v2: identify and use gate clocks instead of divider clocks
>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 14 ++++----------
> 1 file changed, 4 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 2d1344a202a9..6aa25cc4676e 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -180,14 +180,6 @@ HERA_CPU_SLEEP: cpu-hera-sleep {
> };
> };
>
> - /* TODO replace with CCF clock */
> - dummy_clk: clock-3 {
> - compatible = "fixed-clock";
> - #clock-cells = <0>;
> - clock-frequency = <12345>;
> - clock-output-names = "pclk";
> - };
> -
> /* ect node is required to be present by bootloader */
> ect {
> };
> @@ -367,7 +359,8 @@ usi_uart: usi@10a000c0 {
> ranges;
> #address-cells = <1>;
> #size-cells = <1>;
> - clocks = <&dummy_clk>, <&dummy_clk>;
> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>,
> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
That looks much better.
Reviewed-by: Sam Protsenko <[email protected]>
> clock-names = "pclk", "ipclk";
> samsung,sysreg = <&sysreg_peric0 0x1020>;
> samsung,mode = <USI_V2_UART>;
> @@ -378,7 +371,8 @@ serial_0: serial@10a00000 {
> reg = <0x10a00000 0xc0>;
> interrupts = <GIC_SPI 634
> IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&dummy_clk 0>, <&dummy_clk 0>;
> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK>,
> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0>;
> clock-names = "uart", "clk_uart_baud0";
> samsung,uart-fifosize = <256>;
> status = "disabled";
> --
> 2.43.0.472.g3155946c3a-goog
>
>
On Tue, Jan 9, 2024 at 7:01 AM Tudor Ambarus <[email protected]> wrote:
>
> USI8 I2C is used to communicate with an eeprom found on the battery
> connector. Define USI8 in I2C configuration.
>
> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
> selection of the protocol is intentionally left for the board dts file.
>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
> v3: reorder usi8 clock order (thanks Andre'!). Did not make any
> difference at testing as the usi driver treats the clocks in bulk.
> v2:
> - identify and use gate clocks instead of dividers
> - move cells and pinctrl properties from dts to dtsi
> - move IRQ type constant on the previous line
>
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 6aa25cc4676e..f14a24628d04 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 {
> interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + usi8: usi@109700c0 {
> + compatible = "google,gs101-usi",
> + "samsung,exynos850-usi";
> + reg = <0x109700c0 0x20>;
> + ranges;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>,
> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>;
> + clock-names = "pclk", "ipclk";
> + samsung,sysreg = <&sysreg_peric0 0x101c>;
I'd also add samsung,mode for the "default" USI mode here, just to
avoid providing it later in the board's dts. But that's a matter of
taste I guess.
Reviewed-by: Sam Protsenko <[email protected]>
> + status = "disabled";
> +
> + hsi2c_8: i2c@10970000 {
> + compatible = "google,gs101-hsi2c",
> + "samsung,exynosautov9-hsi2c";
> + reg = <0x10970000 0xc0>;
> + interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hsi2c8_bus>;
> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>,
> + <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>;
> + clock-names = "hsi2c", "hsi2c_pclk";
> + status = "disabled";
> + };
> + };
> +
> usi_uart: usi@10a000c0 {
> compatible = "google,gs101-usi",
> "samsung,exynos850-usi";
> --
> 2.43.0.472.g3155946c3a-goog
>
>
On Tue, Jan 9, 2024 at 7:00 AM Tudor Ambarus <[email protected]> wrote:
>
> GS101's Connectivity Peripheral blocks (peric0/1 blocks) which
> include the I3C and USI (I2C, SPI, UART) only allow 32-bit
> register accesses.
>
> Instead of specifying the reg-io-width = 4 everywhere, for each node,
> the requirement should be deduced from the compatible.
>
> Infer UPIO_MEM32 iotype from the "google,gs101-uart" compatible.
> Update the uart info name to be GS101 specific in order to
> differentiate from the other exynos platforms. All the other settings
> are not changed.
>
> exynos_fifoszdt_serial_drv_data was replaced by gs101_serial_drv_data
> because the iotype restriction is gs101 specific and there was no other
> user of exynos_fifoszdt_serial_drv_data.
>
> Reviewed-by: Peter Griffin <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> v3: collect Peter's R-b tag
> v2: new patch
>
> drivers/tty/serial/samsung_tty.c | 38 +++++++++++++++++++++++---------
> 1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/tty/serial/samsung_tty.c b/drivers/tty/serial/samsung_tty.c
> index ff646cddd3f8..a81b61953a28 100644
> --- a/drivers/tty/serial/samsung_tty.c
> +++ b/drivers/tty/serial/samsung_tty.c
> @@ -2497,25 +2497,43 @@ static const struct s3c24xx_serial_drv_data exynos850_serial_drv_data = {
> .fifosize = { 256, 64, 64, 64 },
> };
>
> -/*
> - * Common drv_data struct for platforms that specify samsung,uart-fifosize in
> - * device tree.
> - */
> -static const struct s3c24xx_serial_drv_data exynos_fifoszdt_serial_drv_data = {
> - EXYNOS_COMMON_SERIAL_DRV_DATA(),
> +static const struct s3c24xx_serial_drv_data gs101_serial_drv_data = {
> + .info = {
> + .name = "Google GS101 UART",
> + .type = TYPE_S3C6400,
> + .port_type = PORT_S3C6400,
> + .iotype = UPIO_MEM32,
> + .has_divslot = 1,
> + .rx_fifomask = S5PV210_UFSTAT_RXMASK,
> + .rx_fifoshift = S5PV210_UFSTAT_RXSHIFT,
> + .rx_fifofull = S5PV210_UFSTAT_RXFULL,
> + .tx_fifofull = S5PV210_UFSTAT_TXFULL,
> + .tx_fifomask = S5PV210_UFSTAT_TXMASK,
> + .tx_fifoshift = S5PV210_UFSTAT_TXSHIFT,
> + .def_clk_sel = S3C2410_UCON_CLKSEL0,
> + .num_clks = 1,
> + .clksel_mask = 0,
> + .clksel_shift = 0,
> + },
> + .def_cfg = {
> + .ucon = S5PV210_UCON_DEFAULT,
> + .ufcon = S5PV210_UFCON_DEFAULT,
> + .has_fracval = 1,
> + },
> + /* samsung,uart-fifosize must be specified in the device tree. */
> .fifosize = { 0 },
> };
>
> #define EXYNOS4210_SERIAL_DRV_DATA (&exynos4210_serial_drv_data)
> #define EXYNOS5433_SERIAL_DRV_DATA (&exynos5433_serial_drv_data)
> #define EXYNOS850_SERIAL_DRV_DATA (&exynos850_serial_drv_data)
> -#define EXYNOS_FIFOSZDT_DRV_DATA (&exynos_fifoszdt_serial_drv_data)
> +#define GS101_SERIAL_DRV_DATA (&gs101_serial_drv_data)
>
> #else
> #define EXYNOS4210_SERIAL_DRV_DATA NULL
> #define EXYNOS5433_SERIAL_DRV_DATA NULL
> #define EXYNOS850_SERIAL_DRV_DATA NULL
> -#define EXYNOS_FIFOSZDT_DRV_DATA NULL
> +#define GS101_SERIAL_DRV_DATA NULL
> #endif
>
> #ifdef CONFIG_ARCH_APPLE
> @@ -2603,7 +2621,7 @@ static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
> .driver_data = (kernel_ulong_t)ARTPEC8_SERIAL_DRV_DATA,
> }, {
> .name = "gs101-uart",
> - .driver_data = (kernel_ulong_t)EXYNOS_FIFOSZDT_DRV_DATA,
> + .driver_data = (kernel_ulong_t)GS101_SERIAL_DRV_DATA,
> },
> { },
> };
> @@ -2626,7 +2644,7 @@ static const struct of_device_id s3c24xx_uart_dt_match[] = {
> { .compatible = "axis,artpec8-uart",
> .data = ARTPEC8_SERIAL_DRV_DATA },
> { .compatible = "google,gs101-uart",
> - .data = EXYNOS_FIFOSZDT_DRV_DATA },
> + .data = GS101_SERIAL_DRV_DATA },
> {},
> };
> MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
> --
> 2.43.0.472.g3155946c3a-goog
>
>
On Tue, Jan 9, 2024 at 6:59 AM Tudor Ambarus <[email protected]> wrote:
>
> All gs101 serial ports are restricted to 32-bit register accesses.
> This requirement will be inferred from the compatible. Do not allow
> the reg-io-width property for the google,gs101-uart compatible.
>
> Suggested-by: Krzysztof Kozlowski <[email protected]>
> Reviewed-by: Peter Griffin <[email protected]>
> Signed-off-by: Tudor Ambarus <[email protected]>
> ---
Reviewed-by: Sam Protsenko <[email protected]>
> v3: collect Peter's R-b tag
> v2: new patch
>
> Documentation/devicetree/bindings/serial/samsung_uart.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> index 133259ed3a34..0f0131026911 100644
> --- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> +++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
> @@ -143,6 +143,8 @@ allOf:
> then:
> required:
> - samsung,uart-fifosize
> + properties:
> + reg-io-width: false
>
> unevaluatedProperties: false
>
> --
> 2.43.0.472.g3155946c3a-goog
>
>
Hi, Sam,
Thanks for reviewing the series!
On 1/16/24 17:42, Sam Protsenko wrote:
cut
>> Few clocks are marked as critical because when either of them is
>> disabled, the system hangs even if their clock parents are enabled.
>>
>> Reviewed-by: Peter Griffin <[email protected]>
>> Signed-off-by: Tudor Ambarus <[email protected]>
>> ---
cut
>>
>> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
>> index 782993951fff..f3f0f5feb28d 100644
>> --- a/drivers/clk/samsung/clk-gs101.c
>> +++ b/drivers/clk/samsung/clk-gs101.c
cut
>> +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
>> + /* Disabling this clock makes the system hang. Mark the clock as critical. */
>> + GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
>> + "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user",
>> + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
>> + 21, CLK_IS_CRITICAL, 0),
> Why not just CLK_IGNORE_UNUSED? As I understand this gate clock can be
When either of the clocks that I marked as critical is disabled, the
system hangs, even if their clock parent is enabled. I tested this by
enabling the clock debugfs with write permissions. I prepared-enabled
the parent clock to increase their user count so that when the child
gets disabled to not disable the parent as well. When disabling the
child the system hung, even if its parent was enabled. Thus I considered
that the child is critical. I mentioned this in the commit message as
well. Please tell if get this wrong.
> used to disable PCLK (bus clock) provided to the whole CMU_PERIC0.
> Aren't there any valid cases for disabling this clock, like during
> some PM transitions? For Exynos850 clock driver I marked all clocks of
They aren't, because if one switches off any of these clocks that are
marked as critical, the system hangs and it will not be able to resume.
> this kind as CLK_IGNORE_UNUSED and it works fine. In other words: I'd
> say CLK_IS_CRITICAL flag is more "strong" than CLK_IGNORE_UNUSED, and
> requires better and more specific explanation, to make sure we are not
> abusing it. And I'm not sure this is the case.
Is the explanation from the commit message enough?
>
> The same goes for the rest of clocks marked as CLK_IS_CRITICAL in this
> patch. Please check if maybe using CLK_IGNORE_UNUSED makes sense for
> any of those as well.
I've already checked and all behave as described above.
Thanks,
ta
On 1/16/24 17:57, Sam Protsenko wrote:
> On Tue, Jan 9, 2024 at 7:00 AM Tudor Ambarus <[email protected]> wrote:
>> Remove the reg-io-width property in order to comply with the bindings.
>>
>> The entire bus (PERIC) on which the GS101 serial resides only allows
>> 32-bit register accesses. The reg-io-width dt property is disallowed
>> for the "google,gs101-uart" compatible and instead the iotype is
>> inferred from the compatible.
>>
>> Reviewed-by: Peter Griffin <[email protected]>
>> Signed-off-by: Tudor Ambarus <[email protected]>
>> ---
> Reviewed-by: Sam Protsenko <[email protected]>
>
> Just out of curiosity (I probably missed the relevant discussion
> earlier): what is the actual reason for moving 'reg-io-width' to the
> driver's code as 'iotype'? I mean, what is the actual problem that's
The majority (if not all?) of the hardware blocks in GS101 SoC require
32 bit register access widths. Instead of specifying reg-io-width = 4
everywhere in the device tree, we infer it from the compatibles.
The relevant discussion is here:
https://lore.kernel.org/linux-arm-kernel/[email protected]/
Cheers,
ta
> being solved by this -- is it to make the earlycon functional for
> gs101? I'm asking because the bus width looks like a part of HW
> description, which usually belongs to dts, from the design point of
> view. Anyways, that's not a concern, just trying to understand the
> decision.
On 1/16/24 18:03, Sam Protsenko wrote:
>> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
>> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
>> selection of the protocol is intentionally left for the board dts file.
>>
>> Signed-off-by: Tudor Ambarus <[email protected]>
>> ---
>> v3: reorder usi8 clock order (thanks Andre'!). Did not make any
>> difference at testing as the usi driver treats the clocks in bulk.
>> v2:
>> - identify and use gate clocks instead of dividers
>> - move cells and pinctrl properties from dts to dtsi
>> - move IRQ type constant on the previous line
>>
>> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++
>> 1 file changed, 29 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
>> index 6aa25cc4676e..f14a24628d04 100644
>> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
>> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
>> @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 {
>> interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
>> };
>>
>> + usi8: usi@109700c0 {
>> + compatible = "google,gs101-usi",
>> + "samsung,exynos850-usi";
>> + reg = <0x109700c0 0x20>;
>> + ranges;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>,
>> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>;
>> + clock-names = "pclk", "ipclk";
>> + samsung,sysreg = <&sysreg_peric0 0x101c>;
> I'd also add samsung,mode for the "default" USI mode here, just to
> avoid providing it later in the board's dts. But that's a matter of
> taste I guess.
>
USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
selection of the protocol is intentionally left for the board dts file.
I wanted to emphasize that USI8 doesn't have any HW defaults and its
mode must be chosen by each particular board.
I mentioned the same in the commit message, please tell if you feel it
needs updating.
Cheers,
ta
On Wed, Jan 17, 2024 at 8:49 AM Tudor Ambarus <tudor.ambarus@linaroorg> wrote:
>
> Hi, Sam,
>
> Thanks for reviewing the series!
>
> On 1/16/24 17:42, Sam Protsenko wrote:
>
> cut
>
> >> Few clocks are marked as critical because when either of them is
> >> disabled, the system hangs even if their clock parents are enabled.
> >>
> >> Reviewed-by: Peter Griffin <[email protected]>
> >> Signed-off-by: Tudor Ambarus <[email protected]>
> >> ---
> cut
> >>
> >> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> >> index 782993951fff..f3f0f5feb28d 100644
> >> --- a/drivers/clk/samsung/clk-gs101.c
> >> +++ b/drivers/clk/samsung/clk-gs101.c
>
> cut
>
> >> +static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
> >> + /* Disabling this clock makes the system hang. Mark the clock as critical. */
> >> + GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
> >> + "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user",
> >> + CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
> >> + 21, CLK_IS_CRITICAL, 0),
> > Why not just CLK_IGNORE_UNUSED? As I understand this gate clock can be
>
> When either of the clocks that I marked as critical is disabled, the
> system hangs, even if their clock parent is enabled. I tested this by
> enabling the clock debugfs with write permissions. I prepared-enabled
> the parent clock to increase their user count so that when the child
> gets disabled to not disable the parent as well. When disabling the
> child the system hung, even if its parent was enabled. Thus I considered
> that the child is critical. I mentioned this in the commit message as
> well. Please tell if get this wrong.
>
Ok, if you already tested this particular clock with CLK_IGNORE_UNUSED
and it didn't help:
Reviewed-by: Sam Protsenko <[email protected]>
> > used to disable PCLK (bus clock) provided to the whole CMU_PERIC0.
> > Aren't there any valid cases for disabling this clock, like during
> > some PM transitions? For Exynos850 clock driver I marked all clocks of
>
> They aren't, because if one switches off any of these clocks that are
> marked as critical, the system hangs and it will not be able to resume.
>
> > this kind as CLK_IGNORE_UNUSED and it works fine. In other words: I'd
> > say CLK_IS_CRITICAL flag is more "strong" than CLK_IGNORE_UNUSED, and
> > requires better and more specific explanation, to make sure we are not
> > abusing it. And I'm not sure this is the case.
>
> Is the explanation from the commit message enough?
> >
> > The same goes for the rest of clocks marked as CLK_IS_CRITICAL in this
> > patch. Please check if maybe using CLK_IGNORE_UNUSED makes sense for
> > any of those as well.
>
> I've already checked and all behave as described above.
>
> Thanks,
> ta
On Wed, Jan 17, 2024 at 9:08 AM Tudor Ambarus <tudor.ambarus@linaroorg> wrote:
>
>
>
> On 1/16/24 18:03, Sam Protsenko wrote:
> >> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
> >> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
> >> selection of the protocol is intentionally left for the board dts file.
> >>
> >> Signed-off-by: Tudor Ambarus <[email protected]>
> >> ---
> >> v3: reorder usi8 clock order (thanks Andre'!). Did not make any
> >> difference at testing as the usi driver treats the clocks in bulk.
> >> v2:
> >> - identify and use gate clocks instead of dividers
> >> - move cells and pinctrl properties from dts to dtsi
> >> - move IRQ type constant on the previous line
> >>
> >> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 29 ++++++++++++++++++++
> >> 1 file changed, 29 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> >> index 6aa25cc4676e..f14a24628d04 100644
> >> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> >> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> >> @@ -352,6 +352,35 @@ pinctrl_peric0: pinctrl@10840000 {
> >> interrupts = <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH 0>;
> >> };
> >>
> >> + usi8: usi@109700c0 {
> >> + compatible = "google,gs101-usi",
> >> + "samsung,exynos850-usi";
> >> + reg = <0x109700c0 0x20>;
> >> + ranges;
> >> + #address-cells = <1>;
> >> + #size-cells = <1>;
> >> + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK>,
> >> + <&cmu_peric0 CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7>;
> >> + clock-names = "pclk", "ipclk";
> >> + samsung,sysreg = <&sysreg_peric0 0x101c>;
> > I'd also add samsung,mode for the "default" USI mode here, just to
> > avoid providing it later in the board's dts. But that's a matter of
> > taste I guess.
> >
>
> USI8 CONFIG register comes with a 0x0 reset value, meaning that USI8
> doesn't have a default protocol (I2C, SPI, UART) at reset. Thus the
> selection of the protocol is intentionally left for the board dts file.
>
> I wanted to emphasize that USI8 doesn't have any HW defaults and its
> mode must be chosen by each particular board.
>
> I mentioned the same in the commit message, please tell if you feel it
> needs updating.
>
No, thanks, everything LGTM, I already added my R-b tag above.
> Cheers,
> ta