2022-10-30 07:53:30

by Marijn Suijten

Subject: [PATCH 01/10] arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2

Make sure the SDHCI hardware is properly reset before interacting with
it, to protect against any possibly indeterminate state left by the
bootloader.

Suggested-by: Konrad Dybcio <[email protected]>
Signed-off-by: Marijn Suijten <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++
1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index c39de7d3ace0..a3ae765d9781 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -490,6 +490,7 @@ sdhc_1: mmc@7c4000 {
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC1_BCR>;
qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM6350_CX>;
@@ -1068,6 +1069,7 @@ sdhc_2: mmc@8804000 {
<&gcc GCC_SDCC2_APPS_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "core", "xo";
+ resets = <&gcc GCC_SDCC2_BCR>;
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr", "cpu-sdhc";
--
2.38.1

2022-10-31 09:15:04

by Luca Weiss

Subject: Re: [PATCH 01/10] arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2

On Sun Oct 30, 2022 at 8:32 AM CET, Marijn Suijten wrote:
> Make sure the SDHCI hardware is properly reset before interacting with
> it, to protect against any possibly indeterminate state left by the
> bootloader.
>
> Suggested-by: Konrad Dybcio <[email protected]>
> Signed-off-by: Marijn Suijten <[email protected]>

Reviewed-by: Luca Weiss <[email protected]>
Tested-by: Luca Weiss <[email protected]> # sm7225-fairphone-fp4

Regards
Luca

> ---
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index c39de7d3ace0..a3ae765d9781 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -490,6 +490,7 @@ sdhc_1: mmc@7c4000 {
> <&gcc GCC_SDCC1_APPS_CLK>,
> <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "iface", "core", "xo";
> + resets = <&gcc GCC_SDCC1_BCR>;
> qcom,dll-config = <0x000f642c>;
> qcom,ddr-config = <0x80040868>;
> power-domains = <&rpmhpd SM6350_CX>;
> @@ -1068,6 +1069,7 @@ sdhc_2: mmc@8804000 {
> <&gcc GCC_SDCC2_APPS_CLK>,
> <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "iface", "core", "xo";
> + resets = <&gcc GCC_SDCC2_BCR>;
> interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
> <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> interconnect-names = "sdhc-ddr", "cpu-sdhc";
> --
> 2.38.1

2022-10-31 22:00:13

by Konrad Dybcio

Subject: Re: [PATCH 01/10] arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2

On 30.10.2022 08:32, Marijn Suijten wrote:
> Make sure the SDHCI hardware is properly reset before interacting with
> it, to protect against any possibly indeterminate state left by the
> bootloader.
>
> Suggested-by: Konrad Dybcio <[email protected]>
> Signed-off-by: Marijn Suijten <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>

Konrad
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index c39de7d3ace0..a3ae765d9781 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -490,6 +490,7 @@ sdhc_1: mmc@7c4000 {
> <&gcc GCC_SDCC1_APPS_CLK>,
> <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "iface", "core", "xo";
> + resets = <&gcc GCC_SDCC1_BCR>;
> qcom,dll-config = <0x000f642c>;
> qcom,ddr-config = <0x80040868>;
> power-domains = <&rpmhpd SM6350_CX>;
> @@ -1068,6 +1069,7 @@ sdhc_2: mmc@8804000 {
> <&gcc GCC_SDCC2_APPS_CLK>,
> <&rpmhcc RPMH_CXO_CLK>;
> clock-names = "iface", "core", "xo";
> + resets = <&gcc GCC_SDCC2_BCR>;
> interconnects = <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH0 0>,
> <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
> interconnect-names = "sdhc-ddr", "cpu-sdhc";