The patches depend on the following patch adding SM6115:
* https://lore.kernel.org/linux-arm-msm/[email protected]/
The only remaining validation issues I see in the UFS bindings are solved with
the following patches, but this series doesn't depend on them:
* https://lore.kernel.org/linux-arm-msm/[email protected]/
* https://lore.kernel.org/linux-arm-msm/[email protected]/
To: Andy Gross <[email protected]>
To: Bjorn Andersson <[email protected]>
To: Konrad Dybcio <[email protected]>
To: Alim Akhtar <[email protected]>
To: Avri Altman <[email protected]>
To: Bart Van Assche <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Iskren Chernev <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: ~postmarketos/[email protected]
Cc: [email protected]
Signed-off-by: Luca Weiss <[email protected]>
---
Changes in v2:
- Add new patch adding reg-names to sm6115 & rebase series on top of sm6115
addition
- Fix binding example after sm8450 move, split this patch from original patch
since it became too big
- Move reg-names definition to top-level
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Luca Weiss (3):
arm64: dts: qcom: sm6115: Add missing reg-names property for UFS
dt-bindings: ufs: qcom: Add reg-names property for ICE
dt-bindings: ufs: qcom: Fix sm8450 bindings
.../devicetree/bindings/ufs/qcom,ufs.yaml | 35 ++++++++++++++++++----
arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 +
2 files changed, 31 insertions(+), 5 deletions(-)
---
base-commit: 98d95cb05f231dd0f155f912ec7823475b112f6e
change-id: 20221209-dt-binding-ufs-2d7f64797ff2
Best regards,
--
Luca Weiss <[email protected]>
The UFS driver expects the second reg to be named "ice" otherwise the
Inline Crypto Engine won't get enabled.
Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi")
Signed-off-by: Luca Weiss <[email protected]>
---
arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index 572bf04adf90..85673d562723 100644
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -704,6 +704,7 @@ opp-202000000 {
ufs_mem_hc: ufs@4804000 {
compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
+ reg-names = "std", "ice";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufs_mem_phy_lanes>;
phy-names = "ufsphy";
--
2.39.0
The code in ufs-qcom-ice.c needs the ICE reg to be named "ice". Add this
in the bindings so the existing dts can validate successfully.
Signed-off-by: Luca Weiss <[email protected]>
---
Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
index b517d76215e3..a8d896e1617b 100644
--- a/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/qcom,ufs.yaml
@@ -72,6 +72,10 @@ properties:
minItems: 1
maxItems: 2
+ reg-names:
+ minItems: 1
+ maxItems: 2
+
resets:
maxItems: 1
@@ -122,6 +126,8 @@ allOf:
reg:
minItems: 1
maxItems: 1
+ reg-names:
+ maxItems: 1
- if:
properties:
@@ -150,6 +156,12 @@ allOf:
reg:
minItems: 2
maxItems: 2
+ reg-names:
+ items:
+ - const: std
+ - const: ice
+ required:
+ - reg-names
- if:
properties:
@@ -178,6 +190,8 @@ allOf:
reg:
minItems: 1
maxItems: 1
+ reg-names:
+ maxItems: 1
- if:
properties:
@@ -203,6 +217,12 @@ allOf:
reg:
minItems: 2
maxItems: 2
+ reg-names:
+ items:
+ - const: std
+ - const: ice
+ required:
+ - reg-names
# TODO: define clock bindings for qcom,msm8994-ufshc
--
2.39.0
On 30/12/2022 08:42, Luca Weiss wrote:
> The code in ufs-qcom-ice.c needs the ICE reg to be named "ice". Add this
> in the bindings so the existing dts can validate successfully.
>
> Signed-off-by: Luca Weiss <[email protected]>
> ---
> Documentation/devicetree/bindings/ufs/qcom,ufs.yaml | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Fri Dec 30, 2022 at 10:12 AM CET, Konrad Dybcio wrote:
>
>
> On 30.12.2022 08:42, Luca Weiss wrote:
> > The UFS driver expects the second reg to be named "ice" otherwise the
> > Inline Crypto Engine won't get enabled.
> >
> > Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi")
> > Signed-off-by: Luca Weiss <[email protected]>
> > ---
>
> https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?h=for-next&id=01b6041454e8bc4f5feb76e6bcdc83a48cea21f2
Oh, thanks!
Disregard this patch then please.
>
> Konrad
> > arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > index 572bf04adf90..85673d562723 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> > @@ -704,6 +704,7 @@ opp-202000000 {
> > ufs_mem_hc: ufs@4804000 {
> > compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> > reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
> > + reg-names = "std", "ice";
> > interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> > phys = <&ufs_mem_phy_lanes>;
> > phy-names = "ufsphy";
> >
On 30.12.2022 08:42, Luca Weiss wrote:
> The UFS driver expects the second reg to be named "ice" otherwise the
> Inline Crypto Engine won't get enabled.
>
> Fixes: 97e563bf5ba1 ("arm64: dts: qcom: sm6115: Add basic soc dtsi")
> Signed-off-by: Luca Weiss <[email protected]>
> ---
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git/commit/?h=for-next&id=01b6041454e8bc4f5feb76e6bcdc83a48cea21f2
Konrad
> arch/arm64/boot/dts/qcom/sm6115.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> index 572bf04adf90..85673d562723 100644
> --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
> @@ -704,6 +704,7 @@ opp-202000000 {
> ufs_mem_hc: ufs@4804000 {
> compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
> + reg-names = "std", "ice";
> interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> phys = <&ufs_mem_phy_lanes>;
> phy-names = "ufsphy";
>