From: Tomasz Figa <[email protected]>
Before this patch, the order of memory resources requested by the driver
was controller base as first and OneNAND chip base as second for
S3C64xx/S5PC100 variant and the opposite for S5PC110/S5PV210 variant.
To make this more consistent, this patch swaps the order of resources
for the latter and updates platform code accordingly. As a nice side
effect there is a slight reduction in line count of probe function.
This will make the transition to DT-based probing much easier.
Signed-off-by: Tomasz Figa <[email protected]>
Signed-off-by: Paweł Chmiel <[email protected]>
Signed-off-by: Jonathan Bakker <[email protected]>
---
drivers/mtd/nand/onenand/onenand_samsung.c | 48 ++++++++++------------
1 file changed, 22 insertions(+), 26 deletions(-)
diff --git a/drivers/mtd/nand/onenand/onenand_samsung.c b/drivers/mtd/nand/onenand/onenand_samsung.c
index 924f5ddc9505..a3ef4add865a 100644
--- a/drivers/mtd/nand/onenand/onenand_samsung.c
+++ b/drivers/mtd/nand/onenand/onenand_samsung.c
@@ -123,14 +123,13 @@ struct s3c_onenand {
struct mtd_info *mtd;
struct platform_device *pdev;
enum soc_type type;
- void __iomem *base;
- void __iomem *ahb_addr;
+ void __iomem *ctrl_base;
+ void __iomem *chip_base;
int bootram_command;
void *page_buf;
void *oob_buf;
unsigned int (*mem_addr)(int fba, int fpa, int fsa);
unsigned int (*cmd_map)(unsigned int type, unsigned int val);
- void __iomem *dma_addr;
unsigned long phys_base;
struct completion complete;
};
@@ -144,22 +143,22 @@ static struct s3c_onenand *onenand;
static inline int s3c_read_reg(int offset)
{
- return readl(onenand->base + offset);
+ return readl(onenand->ctrl_base + offset);
}
static inline void s3c_write_reg(int value, int offset)
{
- writel(value, onenand->base + offset);
+ writel(value, onenand->ctrl_base + offset);
}
static inline int s3c_read_cmd(unsigned int cmd)
{
- return readl(onenand->ahb_addr + cmd);
+ return readl(onenand->chip_base + cmd);
}
static inline void s3c_write_cmd(int value, unsigned int cmd)
{
- writel(value, onenand->ahb_addr + cmd);
+ writel(value, onenand->chip_base + cmd);
}
#ifdef SAMSUNG_DEBUG
@@ -517,7 +516,7 @@ static int (*s5pc110_dma_ops)(dma_addr_t dst, dma_addr_t src, size_t count, int
static int s5pc110_dma_poll(dma_addr_t dst, dma_addr_t src, size_t count, int direction)
{
- void __iomem *base = onenand->dma_addr;
+ void __iomem *base = onenand->ctrl_base;
int status;
unsigned long timeout;
@@ -561,7 +560,7 @@ static int s5pc110_dma_poll(dma_addr_t dst, dma_addr_t src, size_t count, int di
static irqreturn_t s5pc110_onenand_irq(int irq, void *data)
{
- void __iomem *base = onenand->dma_addr;
+ void __iomem *base = onenand->ctrl_base;
int status, cmd = 0;
status = readl(base + S5PC110_INTC_DMA_STATUS);
@@ -583,7 +582,7 @@ static irqreturn_t s5pc110_onenand_irq(int irq, void *data)
static int s5pc110_dma_irq(dma_addr_t dst, dma_addr_t src, size_t count, int direction)
{
- void __iomem *base = onenand->dma_addr;
+ void __iomem *base = onenand->ctrl_base;
int status;
status = readl(base + S5PC110_INTC_DMA_MASK);
@@ -632,7 +631,7 @@ static int s5pc110_read_bufferram(struct mtd_info *mtd, int area,
}
if (offset & 3 || (size_t) buf & 3 ||
- !onenand->dma_addr || count != mtd->writesize)
+ !onenand->ctrl_base || count != mtd->writesize)
goto normal;
/* Handle vmalloc address */
@@ -862,23 +861,22 @@ static int s3c_onenand_probe(struct platform_device *pdev)
s3c_onenand_setup(mtd);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- onenand->base = devm_ioremap_resource(&pdev->dev, r);
- if (IS_ERR(onenand->base))
- return PTR_ERR(onenand->base);
-
+ onenand->ctrl_base = devm_ioremap_resource(&pdev->dev, r);
+ if (IS_ERR(onenand->ctrl_base))
+ return PTR_ERR(onenand->ctrl_base);
+
+ r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ onenand->chip_base = devm_ioremap_resource(&pdev->dev, r);
+ if (IS_ERR(onenand->chip_base))
+ return PTR_ERR(onenand->chip_base);
onenand->phys_base = r->start;
- /* Set onenand_chip also */
- this->base = onenand->base;
-
/* Use runtime badblock check */
this->options |= ONENAND_SKIP_UNLOCK_CHECK;
if (onenand->type != TYPE_S5PC110) {
- r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- onenand->ahb_addr = devm_ioremap_resource(&pdev->dev, r);
- if (IS_ERR(onenand->ahb_addr))
- return PTR_ERR(onenand->ahb_addr);
+ /* Set onenand_chip also */
+ this->base = onenand->ctrl_base;
/* Allocate 4KiB BufferRAM */
onenand->page_buf = devm_kzalloc(&pdev->dev, SZ_4K,
@@ -896,10 +894,8 @@ static int s3c_onenand_probe(struct platform_device *pdev)
this->subpagesize = mtd->writesize;
} else { /* S5PC110 */
- r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- onenand->dma_addr = devm_ioremap_resource(&pdev->dev, r);
- if (IS_ERR(onenand->dma_addr))
- return PTR_ERR(onenand->dma_addr);
+ /* Set onenand_chip also */
+ this->base = onenand->chip_base;
s5pc110_dma_ops = s5pc110_dma_poll;
/* Interrupt support */
--
2.30.2
On 23/04/2022 05:46, Jonathan Bakker wrote:
> From: Tomasz Figa <[email protected]>
>
> Before this patch, the order of memory resources requested by the driver
> was controller base as first and OneNAND chip base as second for
> S3C64xx/S5PC100 variant and the opposite for S5PC110/S5PV210 variant.
>
> To make this more consistent, this patch swaps the order of resources
> for the latter and updates platform code accordingly. As a nice side
> effect there is a slight reduction in line count of probe function.
>
> This will make the transition to DT-based probing much easier.
>
> Signed-off-by: Tomasz Figa <[email protected]>
> Signed-off-by: Paweł Chmiel <[email protected]>
> Signed-off-by: Jonathan Bakker <[email protected]>
> ---
> drivers/mtd/nand/onenand/onenand_samsung.c | 48 ++++++++++------------
> 1 file changed, 22 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/mtd/nand/onenand/onenand_samsung.c b/drivers/mtd/nand/onenand/onenand_samsung.c
> index 924f5ddc9505..a3ef4add865a 100644
> --- a/drivers/mtd/nand/onenand/onenand_samsung.c
> +++ b/drivers/mtd/nand/onenand/onenand_samsung.c
> @@ -123,14 +123,13 @@ struct s3c_onenand {
> struct mtd_info *mtd;
> struct platform_device *pdev;
> enum soc_type type;
> - void __iomem *base;
> - void __iomem *ahb_addr;
> + void __iomem *ctrl_base;
> + void __iomem *chip_base;
> int bootram_command;
> void *page_buf;
> void *oob_buf;
> unsigned int (*mem_addr)(int fba, int fpa, int fsa);
> unsigned int (*cmd_map)(unsigned int type, unsigned int val);
> - void __iomem *dma_addr;
> unsigned long phys_base;
> struct completion complete;
> };
> @@ -144,22 +143,22 @@ static struct s3c_onenand *onenand;
>
> static inline int s3c_read_reg(int offset)
> {
> - return readl(onenand->base + offset);
> + return readl(onenand->ctrl_base + offset);
> }
>
> static inline void s3c_write_reg(int value, int offset)
> {
> - writel(value, onenand->base + offset);
> + writel(value, onenand->ctrl_base + offset);
> }
>
> static inline int s3c_read_cmd(unsigned int cmd)
> {
> - return readl(onenand->ahb_addr + cmd);
> + return readl(onenand->chip_base + cmd);
> }
>
> static inline void s3c_write_cmd(int value, unsigned int cmd)
> {
> - writel(value, onenand->ahb_addr + cmd);
> + writel(value, onenand->chip_base + cmd);
> }
>
> #ifdef SAMSUNG_DEBUG
> @@ -517,7 +516,7 @@ static int (*s5pc110_dma_ops)(dma_addr_t dst, dma_addr_t src, size_t count, int
>
> static int s5pc110_dma_poll(dma_addr_t dst, dma_addr_t src, size_t count, int direction)
> {
> - void __iomem *base = onenand->dma_addr;
> + void __iomem *base = onenand->ctrl_base;
> int status;
> unsigned long timeout;
>
> @@ -561,7 +560,7 @@ static int s5pc110_dma_poll(dma_addr_t dst, dma_addr_t src, size_t count, int di
>
> static irqreturn_t s5pc110_onenand_irq(int irq, void *data)
> {
> - void __iomem *base = onenand->dma_addr;
> + void __iomem *base = onenand->ctrl_base;
This is confusing a bit. Before dma_addr was IORESOURCE_MEM no. 1, now
it is no. 0, so it's reversed for S5P. However DTS is not updated, so
what's there? What does the DTS follow here?
Best regards,
Krzysztof