The current Xilinx AXI PCIe Host Bridge driver uses generic PCIe
subsystem framework. This driver works on both Microblaze and Zynq
architecture based platforms.
The microblaze architecture specific code has unused PCIe host bridge
supported API's which are no longer needed.
This series of patch removes unused architecture specific
microblaze PCIe code.
Thippeswamy Havalige (13):
microblaze/PCI: Remove unused early_read_config_byte() et al
declarations
microblaze/PCI: Remove Null PCI config access unused functions
microblaze/PCI: Remove unused PCI bus scan if configured as a host
microblaze/PCI: Remove unused PCI legacy IO's access on a bus
microblaze/PCI: Remove unused device tree parsing for a host bridge
resources
microblaze/PCI: Remove unused allocation & free of PCI host bridge
structure
microblaze/PCI: Remove unused PCI BIOS resource allocation
microblaze/PCI: Remove unused PCI Indirect ops
microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU
address to I/O port
microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al
declaration
microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
microblaze/PCI: Remove support for Xilinx PCI host bridge
microblaze/PCI: Moving PCI iounmap and dependent code
arch/microblaze/Kconfig | 8 -
arch/microblaze/include/asm/pci-bridge.h | 92 ---
arch/microblaze/include/asm/pci.h | 29 -
arch/microblaze/pci/Makefile | 3 +-
arch/microblaze/pci/indirect_pci.c | 158 -----
arch/microblaze/pci/iomap.c | 36 +
arch/microblaze/pci/pci-common.c | 1067 ------------------------------
arch/microblaze/pci/xilinx_pci.c | 170 -----
8 files changed, 37 insertions(+), 1526 deletions(-)
delete mode 100644 arch/microblaze/pci/indirect_pci.c
delete mode 100644 arch/microblaze/pci/pci-common.c
delete mode 100644 arch/microblaze/pci/xilinx_pci.c
--
1.8.3.1
This routine is meant to be used early during boot, when the
PCI bus numbers have not yet been assigned, and you need to
issue PCI config cycles to an OF device.
It could also be used to "fix" RTAS config cycles if you want
to set pci_assign_all_buses to 1 and still use RTAS for PCI
config cycles.
Signed-off-by: Thippeswamy Havalige <[email protected]>
---
arch/microblaze/include/asm/pci-bridge.h | 4 ----
arch/microblaze/pci/pci-common.c | 19 -------------------
2 files changed, 23 deletions(-)
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index a9d3940..ce74b0c 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -107,10 +107,6 @@ extern void setup_indirect_pci(struct pci_controller *hose,
resource_size_t cfg_addr,
resource_size_t cfg_data, u32 flags);
-/* Get the PCI host controller for an OF device */
-extern struct pci_controller *pci_find_hose_for_OF_device(
- struct device_node *node);
-
/* Fill up host controller resources from the OF node */
extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
struct device_node *dev, int primary);
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 58397cf..6ccaf33 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -122,25 +122,6 @@ unsigned long pci_address_to_pio(phys_addr_t address)
}
EXPORT_SYMBOL_GPL(pci_address_to_pio);
-/* This routine is meant to be used early during boot, when the
- * PCI bus numbers have not yet been assigned, and you need to
- * issue PCI config cycles to an OF device.
- * It could also be used to "fix" RTAS config cycles if you want
- * to set pci_assign_all_buses to 1 and still use RTAS for PCI
- * config cycles.
- */
-struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
-{
- while (node) {
- struct pci_controller *hose, *tmp;
- list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
- if (hose->dn == node)
- return hose;
- node = node->parent;
- }
- return NULL;
-}
-
void pcibios_set_master(struct pci_dev *dev)
{
/* No special bus mastering setup handling */
--
1.8.3.1
early_read_config_byte() and similar are declared but never defined.
Remove the unused declarations.
Signed-off-by: Thippeswamy Havalige <[email protected]>
---
arch/microblaze/include/asm/pci-bridge.h | 18 ------------
arch/microblaze/pci/pci-common.c | 5 ----
arch/microblaze/pci/xilinx_pci.c | 48 --------------------------------
3 files changed, 71 deletions(-)
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index 171b40a..a9d3940 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -103,24 +103,6 @@ static inline int isa_vaddr_is_ioport(void __iomem *address)
}
#endif /* CONFIG_PCI */
-/* These are used for config access before all the PCI probing
- has been done. */
-extern int early_read_config_byte(struct pci_controller *hose, int bus,
- int dev_fn, int where, u8 *val);
-extern int early_read_config_word(struct pci_controller *hose, int bus,
- int dev_fn, int where, u16 *val);
-extern int early_read_config_dword(struct pci_controller *hose, int bus,
- int dev_fn, int where, u32 *val);
-extern int early_write_config_byte(struct pci_controller *hose, int bus,
- int dev_fn, int where, u8 val);
-extern int early_write_config_word(struct pci_controller *hose, int bus,
- int dev_fn, int where, u16 val);
-extern int early_write_config_dword(struct pci_controller *hose, int bus,
- int dev_fn, int where, u32 val);
-
-extern int early_find_capability(struct pci_controller *hose, int bus,
- int dev_fn, int cap);
-
extern void setup_indirect_pci(struct pci_controller *hose,
resource_size_t cfg_addr,
resource_size_t cfg_data, u32 flags);
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 33bab7e..69ce51c 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -1060,8 +1060,3 @@ long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
EARLY_PCI_OP(write, word, u16)
EARLY_PCI_OP(write, dword, u32)
-int early_find_capability(struct pci_controller *hose, int bus, int devfn,
- int cap)
-{
- return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
-}
diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c
index f4cb86f..7ed6647 100644
--- a/arch/microblaze/pci/xilinx_pci.c
+++ b/arch/microblaze/pci/xilinx_pci.c
@@ -76,44 +76,6 @@ static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
{
return (bus != 0);
}
-
-/**
- * xilinx_early_pci_scan - List pci config space for available devices
- *
- * List pci devices in very early phase.
- */
-static void __init xilinx_early_pci_scan(struct pci_controller *hose)
-{
- u32 bus = 0;
- u32 val, dev, func, offset;
-
- /* Currently we have only 2 device connected - up-to 32 devices */
- for (dev = 0; dev < 2; dev++) {
- /* List only first function number - up-to 8 functions */
- for (func = 0; func < 1; func++) {
- pr_info("%02x:%02x:%02x", bus, dev, func);
- /* read the first 64 standardized bytes */
- /* Up-to 192 bytes can be list of capabilities */
- for (offset = 0; offset < 64; offset += 4) {
- early_read_config_dword(hose, bus,
- PCI_DEVFN(dev, func), offset, &val);
- if (offset == 0 && val == 0xFFFFFFFF) {
- pr_cont("\nABSENT");
- break;
- }
- if (!(offset % 0x10))
- pr_cont("\n%04x: ", offset);
-
- pr_cont("%08x ", val);
- }
- pr_info("\n");
- }
- }
-}
-#else
-static void __init xilinx_early_pci_scan(struct pci_controller *hose)
-{
-}
#endif
/**
@@ -146,15 +108,6 @@ void __init xilinx_pci_init(void)
r.start + XPLB_PCI_DATA,
INDIRECT_TYPE_SET_CFG_TYPE);
- /* According to the xilinx plbv46_pci documentation the soft-core starts
- * a self-init when the bus master enable bit is set. Without this bit
- * set the pci bus can't be scanned.
- */
- early_write_config_word(hose, 0, 0, PCI_COMMAND, PCI_HOST_ENABLE_CMD);
-
- /* Set the max latency timer to 255 */
- early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0xff);
-
/* Set the max bus number to 255, and bus/subbus no's to 0 */
pci_reg = of_iomap(pci_node, 0);
WARN_ON(!pci_reg);
@@ -166,5 +119,4 @@ void __init xilinx_pci_init(void)
INDIRECT_TYPE_SET_CFG_TYPE);
pr_info("xilinx-pci: Registered PCI host bridge\n");
- xilinx_early_pci_scan(hose);
}
--
1.8.3.1
This patch removes support for the Xilinx PCI host
bridge IPcore.
Signed-off-by: Thippeswamy Havalige <[email protected]>
---
arch/microblaze/Kconfig | 8 ---
arch/microblaze/include/asm/pci-bridge.h | 6 --
arch/microblaze/include/asm/pci.h | 5 --
arch/microblaze/pci/Makefile | 1 -
arch/microblaze/pci/xilinx_pci.c | 105 -------------------------------
5 files changed, 125 deletions(-)
delete mode 100644 arch/microblaze/pci/xilinx_pci.c
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 996132a..9bacdab 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -205,11 +205,3 @@ config TASK_SIZE
default "0x80000000"
endmenu
-
-menu "Bus Options"
-
-config PCI_XILINX
- bool "Xilinx PCI host bridge support"
- depends on PCI
-
-endmenu
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h
index 5db2c66..be5f504 100644
--- a/arch/microblaze/include/asm/pci-bridge.h
+++ b/arch/microblaze/include/asm/pci-bridge.h
@@ -25,7 +25,6 @@ static inline int pcibios_vaddr_is_ioport(void __iomem *address)
*/
struct pci_controller {
struct pci_bus *bus;
- struct device_node *dn;
struct list_head list_node;
void __iomem *io_base_virt;
@@ -37,11 +36,6 @@ struct pci_controller {
};
#ifdef CONFIG_PCI
-static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
-{
- return bus->sysdata;
-}
-
static inline int isa_vaddr_is_ioport(void __iomem *address)
{
/* No specific ISA handling on ppc32 at this stage, it
diff --git a/arch/microblaze/include/asm/pci.h b/arch/microblaze/include/asm/pci.h
index a75bf3b..91f1f71 100644
--- a/arch/microblaze/include/asm/pci.h
+++ b/arch/microblaze/include/asm/pci.h
@@ -38,12 +38,7 @@
struct file;
-/* This part of code was originally in xilinx-pci.h */
-#ifdef CONFIG_PCI_XILINX
-extern void __init xilinx_pci_init(void);
-#else
static inline void __init xilinx_pci_init(void) { return; }
-#endif
#endif /* __KERNEL__ */
#endif /* __ASM_MICROBLAZE_PCI_H */
diff --git a/arch/microblaze/pci/Makefile b/arch/microblaze/pci/Makefile
index 3cbdf25..293b416 100644
--- a/arch/microblaze/pci/Makefile
+++ b/arch/microblaze/pci/Makefile
@@ -4,4 +4,3 @@
#
obj-$(CONFIG_PCI) += pci-common.o iomap.o
-obj-$(CONFIG_PCI_XILINX) += xilinx_pci.o
diff --git a/arch/microblaze/pci/xilinx_pci.c b/arch/microblaze/pci/xilinx_pci.c
deleted file mode 100644
index 5dc4182..0000000
--- a/arch/microblaze/pci/xilinx_pci.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * PCI support for Xilinx plbv46_pci soft-core which can be used on
- * Xilinx Virtex ML410 / ML510 boards.
- *
- * Copyright 2009 Roderick Colenbrander
- * Copyright 2009 Secret Lab Technologies Ltd.
- *
- * The pci bridge fixup code was copied from ppc4xx_pci.c and was written
- * by Benjamin Herrenschmidt.
- * Copyright 2007 Ben. Herrenschmidt <[email protected]>, IBM Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/ioport.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/pci.h>
-#include <linux/io.h>
-
-#define XPLB_PCI_ADDR 0x10c
-#define XPLB_PCI_DATA 0x110
-#define XPLB_PCI_BUS 0x114
-
-#define PCI_HOST_ENABLE_CMD (PCI_COMMAND_SERR | PCI_COMMAND_PARITY | \
- PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY)
-
-static const struct of_device_id xilinx_pci_match[] = {
- { .compatible = "xlnx,plbv46-pci-1.03.a", },
- {}
-};
-
-/**
- * xilinx_pci_fixup_bridge - Block Xilinx PHB configuration.
- */
-static void xilinx_pci_fixup_bridge(struct pci_dev *dev)
-{
- struct pci_controller *hose;
- int i;
-
- if (dev->devfn || dev->bus->self)
- return;
-
- hose = pci_bus_to_host(dev->bus);
- if (!hose)
- return;
-
- if (!of_match_node(xilinx_pci_match, hose->dn))
- return;
-
- /* Hide the PCI host BARs from the kernel as their content doesn't
- * fit well in the resource management
- */
- for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
- dev->resource[i].start = 0;
- dev->resource[i].end = 0;
- dev->resource[i].flags = 0;
- }
-
- dev_info(&dev->dev, "Hiding Xilinx plb-pci host bridge resources %s\n",
- pci_name(dev));
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, xilinx_pci_fixup_bridge);
-
-#ifdef DEBUG
-/**
- * xilinx_pci_exclude_device - Don't do config access for non-root bus
- *
- * This is a hack. Config access to any bus other than bus 0 does not
- * currently work on the ML510 so we prevent it here.
- */
-static int
-xilinx_pci_exclude_device(struct pci_controller *hose, u_char bus, u8 devfn)
-{
- return (bus != 0);
-}
-#endif
-
-/**
- * xilinx_pci_init - Find and register a Xilinx PCI host bridge
- */
-void __init xilinx_pci_init(void)
-{
- struct resource r;
- void __iomem *pci_reg;
- struct device_node *pci_node;
-
- pci_node = of_find_matching_node(NULL, xilinx_pci_match);
- if (!pci_node)
- return;
-
- if (of_address_to_resource(pci_node, 0, &r)) {
- pr_err("xilinx-pci: cannot resolve base address\n");
- return;
- }
-
- /* Set the max bus number to 255, and bus/subbus no's to 0 */
- pci_reg = of_iomap(pci_node, 0);
- WARN_ON(!pci_reg);
- out_be32(pci_reg + XPLB_PCI_BUS, 0x000000ff);
- iounmap(pci_reg);
-
-}
--
1.8.3.1
Hi,
On 10/25/22 08:52, Thippeswamy Havalige wrote:
> The current Xilinx AXI PCIe Host Bridge driver uses generic PCIe
> subsystem framework. This driver works on both Microblaze and Zynq
> architecture based platforms.
>
> The microblaze architecture specific code has unused PCIe host bridge
> supported API's which are no longer needed.
>
> This series of patch removes unused architecture specific
> microblaze PCIe code.
>
> Thippeswamy Havalige (13):
> microblaze/PCI: Remove unused early_read_config_byte() et al
> declarations
> microblaze/PCI: Remove Null PCI config access unused functions
> microblaze/PCI: Remove unused PCI bus scan if configured as a host
> microblaze/PCI: Remove unused PCI legacy IO's access on a bus
> microblaze/PCI: Remove unused device tree parsing for a host bridge
> resources
> microblaze/PCI: Remove unused allocation & free of PCI host bridge
> structure
> microblaze/PCI: Remove unused PCI BIOS resource allocation
> microblaze/PCI: Remove unused PCI Indirect ops
> microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU
> address to I/O port
> microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al
> declaration
> microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
> microblaze/PCI: Remove support for Xilinx PCI host bridge
> microblaze/PCI: Moving PCI iounmap and dependent code
>
> arch/microblaze/Kconfig | 8 -
> arch/microblaze/include/asm/pci-bridge.h | 92 ---
> arch/microblaze/include/asm/pci.h | 29 -
> arch/microblaze/pci/Makefile | 3 +-
> arch/microblaze/pci/indirect_pci.c | 158 -----
> arch/microblaze/pci/iomap.c | 36 +
> arch/microblaze/pci/pci-common.c | 1067 ------------------------------
> arch/microblaze/pci/xilinx_pci.c | 170 -----
> 8 files changed, 37 insertions(+), 1526 deletions(-)
> delete mode 100644 arch/microblaze/pci/indirect_pci.c
> delete mode 100644 arch/microblaze/pci/pci-common.c
> delete mode 100644 arch/microblaze/pci/xilinx_pci.c
>
Why are you sending it again?
M
Hi,
> -----Original Message-----
> From: Simek, Michal <[email protected]>
> Sent: Tuesday, October 25, 2022 1:02 PM
> To: Havalige, Thippeswamy <[email protected]>; linux-
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; Gogada, Bharat Kumar
> <[email protected]>
> Subject: Re: [PATCH 00/13] Remove unused microblaze PCIe bus architecture
>
> Hi,
>
> On 10/25/22 08:52, Thippeswamy Havalige wrote:
> > The current Xilinx AXI PCIe Host Bridge driver uses generic PCIe
> > subsystem framework. This driver works on both Microblaze and Zynq
> > architecture based platforms.
> >
> > The microblaze architecture specific code has unused PCIe host bridge
> > supported API's which are no longer needed.
> >
> > This series of patch removes unused architecture specific microblaze
> > PCIe code.
> >
> > Thippeswamy Havalige (13):
> > microblaze/PCI: Remove unused early_read_config_byte() et al
> > declarations
> > microblaze/PCI: Remove Null PCI config access unused functions
> > microblaze/PCI: Remove unused PCI bus scan if configured as a host
> > microblaze/PCI: Remove unused PCI legacy IO's access on a bus
> > microblaze/PCI: Remove unused device tree parsing for a host bridge
> > resources
> > microblaze/PCI: Remove unused allocation & free of PCI host bridge
> > structure
> > microblaze/PCI: Remove unused PCI BIOS resource allocation
> > microblaze/PCI: Remove unused PCI Indirect ops
> > microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU
> > address to I/O port
> > microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al
> > declaration
> > microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
> > microblaze/PCI: Remove support for Xilinx PCI host bridge
> > microblaze/PCI: Moving PCI iounmap and dependent code
> >
> > arch/microblaze/Kconfig | 8 -
> > arch/microblaze/include/asm/pci-bridge.h | 92 ---
> > arch/microblaze/include/asm/pci.h | 29 -
> > arch/microblaze/pci/Makefile | 3 +-
> > arch/microblaze/pci/indirect_pci.c | 158 -----
> > arch/microblaze/pci/iomap.c | 36 +
> > arch/microblaze/pci/pci-common.c | 1067 ------------------------------
> > arch/microblaze/pci/xilinx_pci.c | 170 -----
> > 8 files changed, 37 insertions(+), 1526 deletions(-)
> > delete mode 100644 arch/microblaze/pci/indirect_pci.c
> > delete mode 100644 arch/microblaze/pci/pci-common.c
> > delete mode 100644 arch/microblaze/pci/xilinx_pci.c
> >
>
> Why are you sending it again?
>
> M
Last time mails were not delivered to opensource maintainers due to some access permissions.
Regards,
Thippeswamy H
On 10/25/22 10:26, Havalige, Thippeswamy wrote:
> Hi,
>> -----Original Message-----
>> From: Simek, Michal <[email protected]>
>> Sent: Tuesday, October 25, 2022 1:02 PM
>> To: Havalige, Thippeswamy <[email protected]>; linux-
>> [email protected]; [email protected];
>> [email protected]; [email protected]
>> Cc: [email protected]; [email protected]; [email protected];
>> [email protected]; Gogada, Bharat Kumar
>> <[email protected]>
>> Subject: Re: [PATCH 00/13] Remove unused microblaze PCIe bus architecture
>>
>> Hi,
>>
>> On 10/25/22 08:52, Thippeswamy Havalige wrote:
>>> The current Xilinx AXI PCIe Host Bridge driver uses generic PCIe
>>> subsystem framework. This driver works on both Microblaze and Zynq
>>> architecture based platforms.
>>>
>>> The microblaze architecture specific code has unused PCIe host bridge
>>> supported API's which are no longer needed.
>>>
>>> This series of patch removes unused architecture specific microblaze
>>> PCIe code.
>>>
>>> Thippeswamy Havalige (13):
>>> microblaze/PCI: Remove unused early_read_config_byte() et al
>>> declarations
>>> microblaze/PCI: Remove Null PCI config access unused functions
>>> microblaze/PCI: Remove unused PCI bus scan if configured as a host
>>> microblaze/PCI: Remove unused PCI legacy IO's access on a bus
>>> microblaze/PCI: Remove unused device tree parsing for a host bridge
>>> resources
>>> microblaze/PCI: Remove unused allocation & free of PCI host bridge
>>> structure
>>> microblaze/PCI: Remove unused PCI BIOS resource allocation
>>> microblaze/PCI: Remove unused PCI Indirect ops
>>> microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU
>>> address to I/O port
>>> microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al
>>> declaration
>>> microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
>>> microblaze/PCI: Remove support for Xilinx PCI host bridge
>>> microblaze/PCI: Moving PCI iounmap and dependent code
>>>
>>> arch/microblaze/Kconfig | 8 -
>>> arch/microblaze/include/asm/pci-bridge.h | 92 ---
>>> arch/microblaze/include/asm/pci.h | 29 -
>>> arch/microblaze/pci/Makefile | 3 +-
>>> arch/microblaze/pci/indirect_pci.c | 158 -----
>>> arch/microblaze/pci/iomap.c | 36 +
>>> arch/microblaze/pci/pci-common.c | 1067 ------------------------------
>>> arch/microblaze/pci/xilinx_pci.c | 170 -----
>>> 8 files changed, 37 insertions(+), 1526 deletions(-)
>>> delete mode 100644 arch/microblaze/pci/indirect_pci.c
>>> delete mode 100644 arch/microblaze/pci/pci-common.c
>>> delete mode 100644 arch/microblaze/pci/xilinx_pci.c
>>>
>>
>> Why are you sending it again?
>>
>> M
>
>
> Last time mails were not delivered to opensource maintainers due to some access permissions.
But people in TO/CC got it. It means you should send it as RESEND or v2 to avoid
confusion.
Thanks,
Michal
> -----Original Message-----
> From: Simek, Michal <[email protected]>
> Sent: Tuesday, October 25, 2022 2:53 PM
> To: Havalige, Thippeswamy <[email protected]>; linux-
> [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; Gogada, Bharat Kumar
> <[email protected]>
> Subject: Re: [PATCH 00/13] Remove unused microblaze PCIe bus architecture
>
>
>
> On 10/25/22 10:26, Havalige, Thippeswamy wrote:
> > Hi,
> >> -----Original Message-----
> >> From: Simek, Michal <[email protected]>
> >> Sent: Tuesday, October 25, 2022 1:02 PM
> >> To: Havalige, Thippeswamy <[email protected]>; linux-
> >> [email protected]; [email protected];
> >> [email protected]; [email protected]
> >> Cc: [email protected]; [email protected]; [email protected];
> >> [email protected]; Gogada, Bharat Kumar
> >> <[email protected]>
> >> Subject: Re: [PATCH 00/13] Remove unused microblaze PCIe bus
> >> architecture
> >>
> >> Hi,
> >>
> >> On 10/25/22 08:52, Thippeswamy Havalige wrote:
> >>> The current Xilinx AXI PCIe Host Bridge driver uses generic PCIe
> >>> subsystem framework. This driver works on both Microblaze and Zynq
> >>> architecture based platforms.
> >>>
> >>> The microblaze architecture specific code has unused PCIe host
> >>> bridge supported API's which are no longer needed.
> >>>
> >>> This series of patch removes unused architecture specific microblaze
> >>> PCIe code.
> >>>
> >>> Thippeswamy Havalige (13):
> >>> microblaze/PCI: Remove unused early_read_config_byte() et al
> >>> declarations
> >>> microblaze/PCI: Remove Null PCI config access unused functions
> >>> microblaze/PCI: Remove unused PCI bus scan if configured as a host
> >>> microblaze/PCI: Remove unused PCI legacy IO's access on a bus
> >>> microblaze/PCI: Remove unused device tree parsing for a host bridge
> >>> resources
> >>> microblaze/PCI: Remove unused allocation & free of PCI host bridge
> >>> structure
> >>> microblaze/PCI: Remove unused PCI BIOS resource allocation
> >>> microblaze/PCI: Remove unused PCI Indirect ops
> >>> microblaze/PCI: Remove unused pci_address_to_pio() conversion of
> CPU
> >>> address to I/O port
> >>> microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al
> >>> declaration
> >>> microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
> >>> microblaze/PCI: Remove support for Xilinx PCI host bridge
> >>> microblaze/PCI: Moving PCI iounmap and dependent code
> >>>
> >>> arch/microblaze/Kconfig | 8 -
> >>> arch/microblaze/include/asm/pci-bridge.h | 92 ---
> >>> arch/microblaze/include/asm/pci.h | 29 -
> >>> arch/microblaze/pci/Makefile | 3 +-
> >>> arch/microblaze/pci/indirect_pci.c | 158 -----
> >>> arch/microblaze/pci/iomap.c | 36 +
> >>> arch/microblaze/pci/pci-common.c | 1067 ------------------------------
> >>> arch/microblaze/pci/xilinx_pci.c | 170 -----
> >>> 8 files changed, 37 insertions(+), 1526 deletions(-)
> >>> delete mode 100644 arch/microblaze/pci/indirect_pci.c
> >>> delete mode 100644 arch/microblaze/pci/pci-common.c
> >>> delete mode 100644 arch/microblaze/pci/xilinx_pci.c
> >>>
> >>
> >> Why are you sending it again?
> >>
> >> M
> >
> >
> > Last time mails were not delivered to opensource maintainers due to some
> access permissions.
>
> But people in TO/CC got it. It means you should send it as RESEND or v2 to
> avoid confusion.
>
> Thanks,
> Michal
Hi Michal,
Check this link, I could only see the patches were listed that are sent today, initially I had some issue or permission issues to send mails outside AMD.
https://patchwork.ozlabs.org/project/linux-pci/list/
Regards,
Thippeswamy H
On Tue, Oct 25, 2022 at 09:31:37AM +0200, Michal Simek wrote:
> Hi,
>
> On 10/25/22 08:52, Thippeswamy Havalige wrote:
> > The current Xilinx AXI PCIe Host Bridge driver uses generic PCIe
> > subsystem framework. This driver works on both Microblaze and Zynq
> > architecture based platforms.
> >
> > The microblaze architecture specific code has unused PCIe host bridge
> > supported API's which are no longer needed.
> >
> > This series of patch removes unused architecture specific
> > microblaze PCIe code.
> >
> > Thippeswamy Havalige (13):
> > microblaze/PCI: Remove unused early_read_config_byte() et al
> > declarations
> > microblaze/PCI: Remove Null PCI config access unused functions
> > microblaze/PCI: Remove unused PCI bus scan if configured as a host
> > microblaze/PCI: Remove unused PCI legacy IO's access on a bus
> > microblaze/PCI: Remove unused device tree parsing for a host bridge
> > resources
> > microblaze/PCI: Remove unused allocation & free of PCI host bridge
> > structure
> > microblaze/PCI: Remove unused PCI BIOS resource allocation
> > microblaze/PCI: Remove unused PCI Indirect ops
> > microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU
> > address to I/O port
> > microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al
> > declaration
> > microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
> > microblaze/PCI: Remove support for Xilinx PCI host bridge
> > microblaze/PCI: Moving PCI iounmap and dependent code
> >
> > arch/microblaze/Kconfig | 8 -
> > arch/microblaze/include/asm/pci-bridge.h | 92 ---
> > arch/microblaze/include/asm/pci.h | 29 -
> > arch/microblaze/pci/Makefile | 3 +-
> > arch/microblaze/pci/indirect_pci.c | 158 -----
> > arch/microblaze/pci/iomap.c | 36 +
> > arch/microblaze/pci/pci-common.c | 1067 ------------------------------
> > arch/microblaze/pci/xilinx_pci.c | 170 -----
> > 8 files changed, 37 insertions(+), 1526 deletions(-)
> > delete mode 100644 arch/microblaze/pci/indirect_pci.c
> > delete mode 100644 arch/microblaze/pci/pci-common.c
> > delete mode 100644 arch/microblaze/pci/xilinx_pci.c
> >
>
> Why are you sending it again?
Michal,
it looks like you don't need anything from me or Bjorn on this series so
I shall drop it from the PCI queue and let you handle it.
If you need any help please let me know.
Thanks,
Lorenzo
Hi Michal,
Can you review/check on this series of patches.
Regards,
Thippeswamy H
> -----Original Message-----
> From: Lorenzo Pieralisi <[email protected]>
> Sent: Thursday, October 27, 2022 3:17 PM
> To: Simek, Michal <[email protected]>
> Cc: Havalige, Thippeswamy <[email protected]>; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; Gogada, Bharat Kumar
> <[email protected]>
> Subject: Re: [PATCH 00/13] Remove unused microblaze PCIe bus architecture
>
> On Tue, Oct 25, 2022 at 09:31:37AM +0200, Michal Simek wrote:
> > Hi,
> >
> > On 10/25/22 08:52, Thippeswamy Havalige wrote:
> > > The current Xilinx AXI PCIe Host Bridge driver uses generic PCIe
> > > subsystem framework. This driver works on both Microblaze and Zynq
> > > architecture based platforms.
> > >
> > > The microblaze architecture specific code has unused PCIe host
> > > bridge supported API's which are no longer needed.
> > >
> > > This series of patch removes unused architecture specific microblaze
> > > PCIe code.
> > >
> > > Thippeswamy Havalige (13):
> > > microblaze/PCI: Remove unused early_read_config_byte() et al
> > > declarations
> > > microblaze/PCI: Remove Null PCI config access unused functions
> > > microblaze/PCI: Remove unused PCI bus scan if configured as a host
> > > microblaze/PCI: Remove unused PCI legacy IO's access on a bus
> > > microblaze/PCI: Remove unused device tree parsing for a host bridge
> > > resources
> > > microblaze/PCI: Remove unused allocation & free of PCI host bridge
> > > structure
> > > microblaze/PCI: Remove unused PCI BIOS resource allocation
> > > microblaze/PCI: Remove unused PCI Indirect ops
> > > microblaze/PCI: Remove unused pci_address_to_pio() conversion of
> CPU
> > > address to I/O port
> > > microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al
> > > declaration
> > > microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
> > > microblaze/PCI: Remove support for Xilinx PCI host bridge
> > > microblaze/PCI: Moving PCI iounmap and dependent code
> > >
> > > arch/microblaze/Kconfig | 8 -
> > > arch/microblaze/include/asm/pci-bridge.h | 92 ---
> > > arch/microblaze/include/asm/pci.h | 29 -
> > > arch/microblaze/pci/Makefile | 3 +-
> > > arch/microblaze/pci/indirect_pci.c | 158 -----
> > > arch/microblaze/pci/iomap.c | 36 +
> > > arch/microblaze/pci/pci-common.c | 1067 ------------------------------
> > > arch/microblaze/pci/xilinx_pci.c | 170 -----
> > > 8 files changed, 37 insertions(+), 1526 deletions(-)
> > > delete mode 100644 arch/microblaze/pci/indirect_pci.c
> > > delete mode 100644 arch/microblaze/pci/pci-common.c
> > > delete mode 100644 arch/microblaze/pci/xilinx_pci.c
> > >
> >
> > Why are you sending it again?
>
> Michal,
>
> it looks like you don't need anything from me or Bjorn on this series so I shall
> drop it from the PCI queue and let you handle it.
>
> If you need any help please let me know.
>
> Thanks,
> Lorenzo
On 10/25/22 08:52, Thippeswamy Havalige wrote:
> The current Xilinx AXI PCIe Host Bridge driver uses generic PCIe
> subsystem framework. This driver works on both Microblaze and Zynq
> architecture based platforms.
>
> The microblaze architecture specific code has unused PCIe host bridge
> supported API's which are no longer needed.
>
> This series of patch removes unused architecture specific
> microblaze PCIe code.
>
> Thippeswamy Havalige (13):
> microblaze/PCI: Remove unused early_read_config_byte() et al
> declarations
> microblaze/PCI: Remove Null PCI config access unused functions
> microblaze/PCI: Remove unused PCI bus scan if configured as a host
> microblaze/PCI: Remove unused PCI legacy IO's access on a bus
> microblaze/PCI: Remove unused device tree parsing for a host bridge
> resources
> microblaze/PCI: Remove unused allocation & free of PCI host bridge
> structure
> microblaze/PCI: Remove unused PCI BIOS resource allocation
> microblaze/PCI: Remove unused PCI Indirect ops
> microblaze/PCI: Remove unused pci_address_to_pio() conversion of CPU
> address to I/O port
> microblaze/PCI: Remove unused sys_pciconfig_iobase() and et al
> declaration
> microblaze/PCI: Remove unused pci_iobar_pfn() and et al declarations
> microblaze/PCI: Remove support for Xilinx PCI host bridge
> microblaze/PCI: Moving PCI iounmap and dependent code
>
> arch/microblaze/Kconfig | 8 -
> arch/microblaze/include/asm/pci-bridge.h | 92 ---
> arch/microblaze/include/asm/pci.h | 29 -
> arch/microblaze/pci/Makefile | 3 +-
> arch/microblaze/pci/indirect_pci.c | 158 -----
> arch/microblaze/pci/iomap.c | 36 +
> arch/microblaze/pci/pci-common.c | 1067 ------------------------------
> arch/microblaze/pci/xilinx_pci.c | 170 -----
> 8 files changed, 37 insertions(+), 1526 deletions(-)
> delete mode 100644 arch/microblaze/pci/indirect_pci.c
> delete mode 100644 arch/microblaze/pci/pci-common.c
> delete mode 100644 arch/microblaze/pci/xilinx_pci.c
>
Applied with also removing PCI_XILINX from defconfig.
Thanks,
Michal