add spi nor support for cv1800 series
Jingbao Qiu (2):
dt-bindings: mtd: add sophgo spi-nor-controller
spi: add support for sophgo spi-nor controller
.../bindings/spi/sophgo,spi-cv1800-nor.yaml | 33 ++
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-sophgo-cv1800.c | 370 ++++++++++++++++++
4 files changed, 413 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
create mode 100644 drivers/spi/spi-sophgo-cv1800.c
base-commit: 4cece764965020c22cff7665b18a012006359095
--
2.25.1
Add YAML bindings for cv1800 spi nor controller.
Signed-off-by: Jingbao Qiu <[email protected]>
---
.../bindings/spi/sophgo,spi-cv1800-nor.yaml | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
diff --git a/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml b/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
new file mode 100644
index 000000000000..121a80fbf2d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
@@ -0,0 +1,33 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/sophgo,spi-cv1800-nor.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SPI controller for Sophgo RISC-V SoCs
+
+maintainers:
+ - Jingbao Qiu <[email protected]>
+
+allOf:
+ - $ref: /schemas/spi/spi-controller.yaml#
+
+properties:
+ compatible:
+ const: sophgo,cv1800b-nor
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ spi@10000000 {
+ compatible = "sophgo,cv1800b-nor";
+ reg = <0x10000000 0x10000000>;
+ };
--
2.25.1
This is a driver for sophgo spi-nor controller using spi-mem interface.
Signed-off-by: Jingbao Qiu <[email protected]>
---
drivers/spi/Kconfig | 9 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-sophgo-cv1800.c | 370 ++++++++++++++++++++++++++++++++
3 files changed, 380 insertions(+)
create mode 100644 drivers/spi/spi-sophgo-cv1800.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index bc7021da2fe9..41ad7c0aaab8 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -971,6 +971,15 @@ config SPI_SN_F_OSPI
for connecting an SPI Flash memory over up to 8-bit wide bus.
It supports indirect access mode only.
+config SPI_SOPHGO_CV1800
+ tristate "Sophgo SPI NOR Controller"
+ depends on ARCH_SOPHGO || COMPILE_TEST
+ help
+ This enables support for the Sophgo SPI NOR controller,
+ which supports Dual/Qual read and write operations while
+ also supporting 3Byte address devices and 4Byte address
+ devices.
+
config SPI_SPRD
tristate "Spreadtrum SPI controller"
depends on ARCH_SPRD || COMPILE_TEST
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 4ff8d725ba5e..a25549155106 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -128,6 +128,7 @@ obj-$(CONFIG_SPI_SH_SCI) += spi-sh-sci.o
obj-$(CONFIG_SPI_SIFIVE) += spi-sifive.o
obj-$(CONFIG_SPI_SLAVE_MT27XX) += spi-slave-mt27xx.o
obj-$(CONFIG_SPI_SN_F_OSPI) += spi-sn-f-ospi.o
+obj-$(CONFIG_SPI_SOPHGO_CV1800) += spi-sophgo-cv1800.o
obj-$(CONFIG_SPI_SPRD) += spi-sprd.o
obj-$(CONFIG_SPI_SPRD_ADI) += spi-sprd-adi.o
obj-$(CONFIG_SPI_STM32) += spi-stm32.o
diff --git a/drivers/spi/spi-sophgo-cv1800.c b/drivers/spi/spi-sophgo-cv1800.c
new file mode 100644
index 000000000000..2e453b7d45f0
--- /dev/null
+++ b/drivers/spi/spi-sophgo-cv1800.c
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Sophgo SPI NOR controller driver
+//
+// Copyright (C) 2020 Jingbao Qiu <[email protected]>
+
+#include <linux/bitfield.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/spi-mem.h>
+
+#define SOPHGO_SPI_CTRL 0x000
+#define SOPHGO_SPI_CE_CTRL 0x004
+#define SOPHGO_SPI_DLY_CTRL 0x008
+#define SOPHGO_SPI_DMMR 0x00C
+#define SOPHGO_SPI_TRAN_CSR 0x010
+#define SOPHGO_SPI_TRAN_NUM 0x014
+#define SOPHGO_SPI_FIFO_PORT 0x018
+#define SOPHGO_SPI_FIFO_PT 0x020
+#define SOPHGO_SPI_INT_STS 0x028
+
+#define SOPHGO_NOR_CTRL_SCK_DIV_MASK GENMASK(10, 0)
+#define SOPHGO_NOR_CTRL_DEFAULT_DIV 4
+#define SOPHGO_NOR_DLY_CTRL_NEG_SAMPLE BIT(14)
+
+#define SOPHGO_NOR_CE_MANUAL BIT(0)
+#define SOPHGO_NOR_CE_MANUAL_EN BIT(1)
+#define SOPHGO_NOR_CE_ENABLE (SOPHGO_NOR_CE_MANUAL | SOPHGO_NOR_CE_MANUAL_EN)
+#define SOPHGO_NOR_CE_DISABLE SOPHGO_NOR_CE_MANUAL_EN
+#define SOPHGO_NOR_CE_HARDWARE 0
+
+#define SOPHGO_NOR_TRAN_MODE_RX BIT(0)
+#define SOPHGO_NOR_TRAN_MODE_TX BIT(1)
+#define SOPHGO_NOR_TRAN_MODE_MASK GENMASK(1, 0)
+#define SOPHGO_NOR_TRANS_FAST BIT(3)
+#define SOPHGO_NOR_TRANS_BUS_WIDTH(n) (n << 4)
+#define SOPHGO_NOR_TRANS_BUS_WIDTH_MASK GENMASK(5, 4)
+
+#define SOPHGO_NOR_TRANS_MIOS BIT(7)
+
+#define SOPHGO_NOR_TRAN_ADDR(n) (n << 8)
+#define SOPHGO_NOR_TRANS_ADDR_MASK GENMASK(10, 8)
+#define SOPHGO_NOR_TRANS_CMD BIT(11)
+#define SOPHGO_NOR_TRAN_FIFO_MASK GENMASK(13, 12)
+#define SOPHGO_NOR_TRAN_FIFO_8_BYTE GENMASK(13, 12)
+#define SOPHGO_NOR_TRAN_GO_BUSY BIT(15)
+
+#define SOPHGO_NOR_TRANS_DMMR_EN BIT(20)
+#define SOPHGO_NOR_TRANS_DMMR_CMD BIT(21)
+
+#define SOPHGO_NOR_TRANS_MMIO \
+ (SOPHGO_NOR_TRANS_FAST | SOPHGO_NOR_TRANS_DMMR_EN | \
+ SOPHGO_NOR_TRANS_DMMR_CMD | SOPHGO_NOR_TRANS_MIOS | \
+ SOPHGO_NOR_TRAN_MODE_RX | SOPHGO_NOR_TRAN_FIFO_8_BYTE)
+
+#define SOPHGO_NOR_TRANS_PORT \
+ (SOPHGO_NOR_TRAN_MODE_MASK | SOPHGO_NOR_TRANS_ADDR_MASK | \
+ SOPHGO_NOR_TRAN_FIFO_MASK | SOPHGO_NOR_TRANS_BUS_WIDTH_MASK | \
+ SOPHGO_NOR_TRANS_BUS_WIDTH_MASK)
+
+#define SOPHGO_NOR_FIFO_CAPACITY 8
+#define SOPHGO_NOR_FIFO_AVAI_MASK GENMASK(3, 0)
+
+#define SOPHGO_NOR_INT_TRAN_DONE BIT(0)
+#define SOPHGO_NOR_INT_RD_FIFO BIT(1)
+#define SOPHGO_NOR_INT_WR_FIFO BIT(2)
+
+struct sophgo_nor {
+ struct spi_controller *ctlr;
+ struct device *dev;
+ void __iomem *io_base;
+ uint32_t tran_csr_orig;
+ uint32_t sck_div_orig;
+ struct mutex lock;
+};
+
+static uint32_t sophgo_nor_clk_setup(struct sophgo_nor *spif, uint32_t sck_div)
+{
+ uint32_t reg;
+ uint32_t old_clk;
+
+ reg = readl(spif->io_base + SOPHGO_SPI_DLY_CTRL);
+
+ if (sck_div < SOPHGO_NOR_CTRL_DEFAULT_DIV)
+ reg |= SOPHGO_NOR_DLY_CTRL_NEG_SAMPLE;
+
+ writel(reg, spif->io_base + SOPHGO_SPI_DLY_CTRL);
+
+ reg = readl(spif->io_base + SOPHGO_SPI_CTRL);
+ old_clk = FIELD_GET(SOPHGO_NOR_CTRL_SCK_DIV_MASK, reg);
+
+ reg &= ~SOPHGO_NOR_CTRL_SCK_DIV_MASK;
+ reg |= sck_div;
+ writel(reg, spif->io_base + SOPHGO_SPI_CTRL);
+
+ return old_clk;
+}
+
+static inline uint32_t sophgo_nor_trans_csr_config(struct sophgo_nor *spif,
+ const struct spi_mem_op *op)
+{
+ uint32_t tran_csr = 0;
+
+ if (op->dummy.nbytes)
+ tran_csr |= (op->dummy.nbytes * 8) / op->dummy.buswidth << 16;
+
+ tran_csr |= SOPHGO_NOR_TRANS_MMIO;
+ tran_csr |= SOPHGO_NOR_TRANS_BUS_WIDTH(op->data.buswidth / 2);
+ tran_csr |= SOPHGO_NOR_TRAN_ADDR(op->addr.nbytes);
+
+ return tran_csr;
+}
+
+static void sophgo_nor_config_mmio(struct sophgo_nor *spif,
+ const struct spi_mem_op *op,
+ uint32_t enabled)
+{
+ uint32_t ctrl, tran_csr;
+
+ if (enabled) {
+ spif->tran_csr_orig =
+ readl(spif->io_base + SOPHGO_SPI_TRAN_CSR);
+ tran_csr = sophgo_nor_trans_csr_config(spif, op);
+ ctrl = SOPHGO_NOR_CE_HARDWARE;
+ } else {
+ tran_csr = spif->tran_csr_orig;
+ ctrl = SOPHGO_NOR_CE_ENABLE;
+ }
+
+ writel(tran_csr, spif->io_base + SOPHGO_SPI_TRAN_CSR);
+ writel(ctrl, spif->io_base + SOPHGO_SPI_CE_CTRL);
+ writel(enabled, spif->io_base + SOPHGO_SPI_DMMR);
+}
+
+static void sophgo_nor_config_port(struct sophgo_nor *spif, uint32_t enabled)
+{
+ uint32_t ctrl = SOPHGO_NOR_CE_ENABLE;
+
+ if (enabled) {
+ ctrl = SOPHGO_NOR_CE_MANUAL_EN;
+ writel(!enabled, spif->io_base + SOPHGO_SPI_DMMR);
+ }
+
+ writel(ctrl, spif->io_base + SOPHGO_SPI_CE_CTRL);
+}
+
+static int sophgo_nor_xfer(struct sophgo_nor *spif, const uint8_t *dout,
+ uint8_t *din, uint32_t data_bytes,
+ uint32_t bus_width)
+{
+ uint32_t xfer_size, off;
+ uint32_t fifo_cnt;
+ uint32_t interrupt_mask = 0;
+ uint32_t stat, tran_csr = 0;
+ int ret = 0;
+
+ writel(0, spif->io_base + SOPHGO_SPI_INT_STS);
+ writel(0, spif->io_base + SOPHGO_SPI_FIFO_PT);
+
+ writew(data_bytes, spif->io_base + SOPHGO_SPI_TRAN_NUM);
+
+ if (din && dout)
+ return -1;
+ else if (!din && !dout)
+ return -1;
+
+ tran_csr = readw(spif->io_base + SOPHGO_SPI_TRAN_CSR);
+
+ tran_csr &= ~SOPHGO_NOR_TRANS_PORT;
+
+ tran_csr |= SOPHGO_NOR_TRAN_FIFO_8_BYTE;
+ tran_csr |= SOPHGO_NOR_TRAN_GO_BUSY;
+ tran_csr |= (bus_width / 2) << 4;
+
+ interrupt_mask |= SOPHGO_NOR_INT_TRAN_DONE;
+
+ if (din) {
+ tran_csr |= SOPHGO_NOR_TRAN_MODE_RX;
+ interrupt_mask |= SOPHGO_NOR_INT_RD_FIFO;
+ spif->sck_div_orig =
+ sophgo_nor_clk_setup(spif, SOPHGO_NOR_CTRL_DEFAULT_DIV);
+ } else if (dout) {
+ tran_csr |= SOPHGO_NOR_TRAN_MODE_TX;
+ interrupt_mask |= SOPHGO_NOR_INT_WR_FIFO;
+ }
+
+ writew(tran_csr, spif->io_base + SOPHGO_SPI_TRAN_CSR);
+
+ ret = readb_poll_timeout(spif->io_base + SOPHGO_SPI_INT_STS, stat,
+ stat & interrupt_mask, 10, 30);
+ if (ret)
+ dev_warn(spif->dev, "%s stat timedout\n", __func__);
+
+ off = 0;
+ while (off < data_bytes) {
+ xfer_size = min_t(uint32_t, data_bytes - off,
+ SOPHGO_NOR_FIFO_CAPACITY);
+
+ fifo_cnt = readl(spif->io_base + SOPHGO_SPI_FIFO_PT) &
+ SOPHGO_NOR_FIFO_AVAI_MASK;
+
+ if (fifo_cnt > SOPHGO_NOR_FIFO_CAPACITY)
+ goto exit;
+
+ if (din)
+ xfer_size = min(xfer_size, fifo_cnt);
+ else
+ xfer_size = min_t(uint32_t, xfer_size,
+ SOPHGO_NOR_FIFO_CAPACITY - fifo_cnt);
+
+ while (xfer_size--) {
+ if (din)
+ *(din + off) = readb(spif->io_base +
+ SOPHGO_SPI_FIFO_PORT);
+ else
+ writeb(*(dout + off),
+ spif->io_base + SOPHGO_SPI_FIFO_PORT);
+ off++;
+ }
+ }
+
+ ret = readb_poll_timeout(spif->io_base + SOPHGO_SPI_INT_STS, stat,
+ (stat & interrupt_mask), 10, 30);
+ if (ret) {
+ dev_warn(spif->dev, " %s command timed out %x\n", __func__,
+ stat);
+ }
+
+exit:
+ writeb(0, spif->io_base + SOPHGO_SPI_FIFO_PT);
+ stat = readb(spif->io_base + SOPHGO_SPI_INT_STS) & ~interrupt_mask;
+ writeb(stat, spif->io_base + SOPHGO_SPI_INT_STS);
+
+ if (din)
+ sophgo_nor_clk_setup(spif, spif->sck_div_orig);
+
+ return 0;
+}
+
+static int sophgo_nor_port_trans(struct sophgo_nor *spif,
+ const struct spi_mem_op *op)
+{
+ const uint8_t *dout = NULL;
+ uint8_t *din = NULL;
+ uint32_t addr;
+
+ sophgo_nor_config_port(spif, 1);
+
+ if (op->cmd.nbytes)
+ sophgo_nor_xfer(spif, (uint8_t *)&op->cmd.opcode, NULL,
+ op->cmd.nbytes, op->cmd.buswidth);
+
+ if (op->addr.nbytes) {
+ addr = cpu_to_be32(op->addr.val);
+ sophgo_nor_xfer(spif, (uint8_t *)&addr, NULL, op->addr.nbytes,
+ op->addr.buswidth);
+ }
+
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ din = op->data.buf.in;
+ else if (op->data.dir == SPI_MEM_DATA_OUT)
+ dout = op->data.buf.out;
+
+ sophgo_nor_xfer(spif, dout, din, op->data.nbytes, op->data.buswidth);
+
+ sophgo_nor_config_port(spif, 0);
+
+ return 0;
+}
+
+static void sophgo_nore_read_mmio(struct sophgo_nor *spif,
+ const struct spi_mem_op *op)
+{
+ sophgo_nor_config_mmio(spif, op, 1);
+ memcpy_fromio(op->data.buf.in, spif->io_base + op->addr.val,
+ op->data.nbytes);
+ sophgo_nor_config_mmio(spif, op, 0);
+}
+
+static int sophgo_nor_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
+{
+ struct sophgo_nor *spif;
+
+ spif = spi_controller_get_devdata(mem->spi->controller);
+
+ mutex_lock(&spif->lock);
+ if (op->data.dir == SPI_MEM_DATA_IN && op->data.nbytes &&
+ op->addr.nbytes == 4) {
+ sophgo_nore_read_mmio(spif, op);
+ goto exit;
+ }
+
+ sophgo_nor_port_trans(spif, op);
+
+exit:
+ mutex_unlock(&spif->lock);
+ return 0;
+}
+
+static const struct spi_controller_mem_ops sophgo_nor_mem_ops = {
+ .exec_op = sophgo_nor_exec_op,
+};
+
+static const struct of_device_id sophgo_nor_match[] = {
+ { .compatible = "sophgo,cv1800b-nor" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sophgo_nor_match);
+
+static int sophgo_nor_probe(struct platform_device *pdev)
+{
+ struct spi_controller *ctlr;
+ struct sophgo_nor *sp;
+ void __iomem *base;
+
+ ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*sp));
+ if (!ctlr)
+ return -ENOMEM;
+
+ sp = spi_controller_get_devdata(ctlr);
+ dev_set_drvdata(&pdev->dev, ctlr);
+
+ sp->dev = &pdev->dev;
+ sp->ctlr = ctlr;
+
+ sp->io_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ ctlr->num_chipselect = 1;
+ ctlr->dev.of_node = pdev->dev.of_node;
+ ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
+ ctlr->auto_runtime_pm = false;
+ ctlr->mem_ops = &sophgo_nor_mem_ops;
+ ctlr->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL | SPI_RX_QUAD | SPI_TX_QUAD;
+
+ mutex_init(&sp->lock);
+
+ sophgo_nor_config_port(sp, 1);
+
+ return devm_spi_register_controller(&pdev->dev, ctlr);
+}
+
+static int sophgo_nor_remove(struct platform_device *pdev)
+{
+ struct sophgo_nor *spif = platform_get_drvdata(pdev);
+
+ mutex_destroy(&spif->lock);
+ return 0;
+}
+
+static struct platform_driver sophgo_nor_driver = {
+ .driver = {
+ .name = "sophgo-spif",
+ .of_match_table = sophgo_nor_match,
+ },
+ .probe = sophgo_nor_probe,
+ .remove = sophgo_nor_remove,
+};
+
+module_platform_driver(sophgo_nor_driver);
+
+MODULE_DESCRIPTION("Sophgo SPI NOR controller driver");
+MODULE_AUTHOR("Jingbao Qiu <[email protected]>");
+MODULE_LICENSE("GPL");
--
2.25.1
On 27/04/2024 09:54, Jingbao Qiu wrote:
> Add YAML bindings for cv1800 spi nor controller.
>
> Signed-off-by: Jingbao Qiu <[email protected]>
> ---
> .../bindings/spi/sophgo,spi-cv1800-nor.yaml | 33 +++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml b/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
> new file mode 100644
> index 000000000000..121a80fbf2d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
Filename like compatible.
> @@ -0,0 +1,33 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/sophgo,spi-cv1800-nor.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SPI controller for Sophgo RISC-V SoCs
> +
> +maintainers:
> + - Jingbao Qiu <[email protected]>
> +
> +allOf:
> + - $ref: /schemas/spi/spi-controller.yaml#
> +
> +properties:
> + compatible:
> + const: sophgo,cv1800b-nor
A bit unusual that compatible has nothing in common with tile of the
binding, thus the name of the hardware block.
> +
> + reg:
> + maxItems: 1
No clocks? No interrupts? This looks incomplete.
> +
> +required:
> + - compatible
> + - reg
Best regards,
Krzysztof
On Mon, Apr 29, 2024 at 2:18 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 27/04/2024 09:54, Jingbao Qiu wrote:
> > Add YAML bindings for cv1800 spi nor controller.
> >
> > Signed-off-by: Jingbao Qiu <[email protected]>
> > ---
> > .../bindings/spi/sophgo,spi-cv1800-nor.yaml | 33 +++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml b/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
> > new file mode 100644
> > index 000000000000..121a80fbf2d5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/spi/sophgo,spi-cv1800-nor.yaml
>
> Filename like compatible.
>
I will fix it.
>
> > @@ -0,0 +1,33 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/spi/sophgo,spi-cv1800-nor.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: SPI controller for Sophgo RISC-V SoCs
> > +
> > +maintainers:
> > + - Jingbao Qiu <[email protected]>
> > +
> > +allOf:
> > + - $ref: /schemas/spi/spi-controller.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: sophgo,cv1800b-nor
>
> A bit unusual that compatible has nothing in common with tile of the
> binding, thus the name of the hardware block.
I will modify the title.
>
> > +
> > + reg:
> > + maxItems: 1
>
> No clocks? No interrupts? This looks incomplete.
If necessary, I will add clocks and interrupts.
Thank you for your suggestion.
Best regards,
Jingbao Qiu
On 29/04/2024 08:41, Jingbao Qiu wrote:
>
>>
>>> +
>>> + reg:
>>> + maxItems: 1
>>
>> No clocks? No interrupts? This looks incomplete.
>
> If necessary, I will add clocks and interrupts.
Does your hardware has them? Binding should be complete, so fully
describe your hardware.
Best regards,
Krzysztof
On Mon, Apr 29, 2024 at 2:43 PM Krzysztof Kozlowski
<[email protected]> wrote:
>
> On 29/04/2024 08:41, Jingbao Qiu wrote:
> >
> >>
> >>> +
> >>> + reg:
> >>> + maxItems: 1
> >>
> >> No clocks? No interrupts? This looks incomplete.
> >
> > If necessary, I will add clocks and interrupts.
>
> Does your hardware has them? Binding should be complete, so fully
> describe your hardware.
>
I will provide a complete description of the hardware.
Best regards,
Jingbao QIu
Hi Jingbao,
kernel test robot noticed the following build warnings:
[auto build test WARNING on 4cece764965020c22cff7665b18a012006359095]
url: https://github.com/intel-lab-lkp/linux/commits/Jingbao-Qiu/dt-bindings-mtd-add-sophgo-spi-nor-controller/20240427-155533
base: 4cece764965020c22cff7665b18a012006359095
patch link: https://lore.kernel.org/r/20240427075426.662671-3-qiujingbao.dlmu%40gmail.com
patch subject: [PATCH v1 2/2] spi: add support for sophgo spi-nor controller
config: powerpc-randconfig-r111-20240430 (https://download.01.org/0day-ci/archive/20240430/[email protected]/config)
compiler: clang version 15.0.7 (https://github.com/llvm/llvm-project.git 8dfdcc7b7bf66834a761bd8de445840ef68e4d1a)
reproduce: (https://download.01.org/0day-ci/archive/20240430/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
sparse warnings: (new ones prefixed by >>)
>> drivers/spi/spi-sophgo-cv1800.c:259:22: sparse: sparse: incorrect type in assignment (different base types) @@ expected unsigned int [usertype] addr @@ got restricted __be32 [usertype] @@
drivers/spi/spi-sophgo-cv1800.c:259:22: sparse: expected unsigned int [usertype] addr
drivers/spi/spi-sophgo-cv1800.c:259:22: sparse: got restricted __be32 [usertype]
vim +259 drivers/spi/spi-sophgo-cv1800.c
244
245 static int sophgo_nor_port_trans(struct sophgo_nor *spif,
246 const struct spi_mem_op *op)
247 {
248 const uint8_t *dout = NULL;
249 uint8_t *din = NULL;
250 uint32_t addr;
251
252 sophgo_nor_config_port(spif, 1);
253
254 if (op->cmd.nbytes)
255 sophgo_nor_xfer(spif, (uint8_t *)&op->cmd.opcode, NULL,
256 op->cmd.nbytes, op->cmd.buswidth);
257
258 if (op->addr.nbytes) {
> 259 addr = cpu_to_be32(op->addr.val);
260 sophgo_nor_xfer(spif, (uint8_t *)&addr, NULL, op->addr.nbytes,
261 op->addr.buswidth);
262 }
263
264 if (op->data.dir == SPI_MEM_DATA_IN)
265 din = op->data.buf.in;
266 else if (op->data.dir == SPI_MEM_DATA_OUT)
267 dout = op->data.buf.out;
268
269 sophgo_nor_xfer(spif, dout, din, op->data.nbytes, op->data.buswidth);
270
271 sophgo_nor_config_port(spif, 0);
272
273 return 0;
274 }
275
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
Hi,
On Sat Apr 27, 2024 at 9:54 AM CEST, Jingbao Qiu wrote:
> Add YAML bindings for cv1800 spi nor controller.
nit: SPI NOR
Is this really just an SPI NOR controller? Doesn't it work with
SPI NAND? Or in general, any memory like SPI device.
-michael
On Tue, Apr 30, 2024 at 7:13 PM Michael Walle <[email protected]> wrote:
>
> Hi,
>
> On Sat Apr 27, 2024 at 9:54 AM CEST, Jingbao Qiu wrote:
> > Add YAML bindings for cv1800 spi nor controller.
>
> nit: SPI NOR
I will fix it.
>
> Is this really just an SPI NOR controller? Doesn't it work with
> SPI NAND? Or in general, any memory like SPI device.
>
Yes, This hardware is only suitable for NOR flash and does not support NAND.
This is a detailed document.
Link: https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM/contents/en
Best Regards
Jingbao Qiu