From: Anson Huang <[email protected]>
The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.
Signed-off-by: Anson Huang <[email protected]>
---
Changes since V4:
- to solve the clock driver probed after system counter driver issue, now we can easily switch to
use fixed clock defined in DT and get its rate, then divided by 3 to get real clock rate for
system counter driver, no need to add "clock-frequency" property in DT.
---
drivers/clocksource/timer-imx-sysctr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
index fd7d680..b7c80a3 100644
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -20,6 +20,8 @@
#define SYS_CTR_EN 0x1
#define SYS_CTR_IRQ_MASK 0x2
+#define SYS_CTR_CLK_DIV 0x3
+
static void __iomem *sys_ctr_base;
static u32 cmpcr;
@@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
if (ret)
return ret;
+ /* system counter clock is divided by 3 internally */
+ to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+
sys_ctr_base = timer_of_base(&to_sysctr);
cmpcr = readl(sys_ctr_base + CMPCR);
cmpcr &= ~SYS_CTR_EN;
--
2.7.4
From: Anson Huang <[email protected]>
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <[email protected]>
---
Changes since V4:
- update the clock info using fixed clock node;
- correct the reg range;
- update the interrupt number as the system counter driver ONLY uses 1 irq now.
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index a1bbd80..2991172 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -644,6 +644,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_25m>;
+ clock-names = "per";
+ };
};
bus@30800000 { /* AIPS3 */
--
2.7.4
Gentle ping...
> From: Anson Huang <[email protected]>
>
> The system counter block guide states that the base clock is internally divided
> by 3 before use, that means the clock input of system counter defined in DT
> should be base clock which is normally from OSC, and then internally divided
> by 3 before use.
>
> Signed-off-by: Anson Huang <[email protected]>
> ---
> Changes since V4:
> - to solve the clock driver probed after system counter driver issue,
> now we can easily switch to
> use fixed clock defined in DT and get its rate, then divided by 3 to
> get real clock rate for
> system counter driver, no need to add "clock-frequency" property in
> DT.
> ---
> drivers/clocksource/timer-imx-sysctr.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/clocksource/timer-imx-sysctr.c
> b/drivers/clocksource/timer-imx-sysctr.c
> index fd7d680..b7c80a3 100644
> --- a/drivers/clocksource/timer-imx-sysctr.c
> +++ b/drivers/clocksource/timer-imx-sysctr.c
> @@ -20,6 +20,8 @@
> #define SYS_CTR_EN 0x1
> #define SYS_CTR_IRQ_MASK 0x2
>
> +#define SYS_CTR_CLK_DIV 0x3
> +
> static void __iomem *sys_ctr_base;
> static u32 cmpcr;
>
> @@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node
> *np)
> if (ret)
> return ret;
>
> + /* system counter clock is divided by 3 internally */
> + to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
> +
> sys_ctr_base = timer_of_base(&to_sysctr);
> cmpcr = readl(sys_ctr_base + CMPCR);
> cmpcr &= ~SYS_CTR_EN;
> --
> 2.7.4
On 06/08/2019 03:55, Anson Huang wrote:
> Gentle ping...
Coming back from vacation. It is in the pipe ... :)
>> From: Anson Huang <[email protected]>
>>
>> The system counter block guide states that the base clock is internally divided
>> by 3 before use, that means the clock input of system counter defined in DT
>> should be base clock which is normally from OSC, and then internally divided
>> by 3 before use.
>>
>> Signed-off-by: Anson Huang <[email protected]>
>> ---
>> Changes since V4:
>> - to solve the clock driver probed after system counter driver issue,
>> now we can easily switch to
>> use fixed clock defined in DT and get its rate, then divided by 3 to
>> get real clock rate for
>> system counter driver, no need to add "clock-frequency" property in
>> DT.
>> ---
>> drivers/clocksource/timer-imx-sysctr.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/clocksource/timer-imx-sysctr.c
>> b/drivers/clocksource/timer-imx-sysctr.c
>> index fd7d680..b7c80a3 100644
>> --- a/drivers/clocksource/timer-imx-sysctr.c
>> +++ b/drivers/clocksource/timer-imx-sysctr.c
>> @@ -20,6 +20,8 @@
>> #define SYS_CTR_EN 0x1
>> #define SYS_CTR_IRQ_MASK 0x2
>>
>> +#define SYS_CTR_CLK_DIV 0x3
>> +
>> static void __iomem *sys_ctr_base;
>> static u32 cmpcr;
>>
>> @@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node
>> *np)
>> if (ret)
>> return ret;
>>
>> + /* system counter clock is divided by 3 internally */
>> + to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
>> +
>> sys_ctr_base = timer_of_base(&to_sysctr);
>> cmpcr = readl(sys_ctr_base + CMPCR);
>> cmpcr &= ~SYS_CTR_EN;
>> --
>> 2.7.4
>
--
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