2020-11-02 02:18:05

by Joakim Zhang

[permalink] [raw]
Subject: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support

Add CAN device node and pinctrl on i.MX8MP evk board.

Signed-off-by: Joakim Zhang <[email protected]>
---
ChangeLogs:
V1->V2:
* add missing space before '=',
fsl,clk-source= /bits/ 8 <0> -> fsl,clk-source = /bits/ 8 <0>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 62 ++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 30 ++++++++++
2 files changed, 92 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 908b92bb4dcd..b10dce8767a4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -33,6 +33,28 @@
<0x1 0x00000000 0 0xc0000000>;
};

+ reg_can1_stby: regulator-can1-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can1-stby";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can2_stby: regulator-can2-stby {
+ compatible = "regulator-fixed";
+ regulator-name = "can2-stby";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2_reg>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -45,6 +67,20 @@
};
};

+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <&reg_can1_stby>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <&reg_can2_stby>;
+ status = "disabled";/* can2 pin conflict with pdm */
+};
+
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>;
@@ -144,6 +180,32 @@
>;
};

+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
+ MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
+ MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
+ >;
+ };
+
+ pinctrl_flexcan1_reg: flexcan1reggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
+ >;
+ };
+
+ pinctrl_flexcan2_reg: flexcan2reggrp {
+ fsl,pins = <
+ MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
+ >;
+ };
+
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 479312293036..ecccfbb4f5ad 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -552,6 +552,36 @@
status = "disabled";
};

+ flexcan1: can@308c0000 {
+ compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x308c0000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
+ <&clk IMX8MP_CLK_CAN1_ROOT>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ fsl,stop-mode = <&gpr 0x10 4>;
+ status = "disabled";
+ };
+
+ flexcan2: can@308d0000 {
+ compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
+ reg = <0x308d0000 0x10000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
+ <&clk IMX8MP_CLK_CAN2_ROOT>;
+ clock-names = "ipg", "per";
+ assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
+ assigned-clock-rates = <40000000>;
+ fsl,clk-source = /bits/ 8 <0>;
+ fsl,stop-mode = <&gpr 0x10 5>;
+ status = "disabled";
+ };
+
crypto: crypto@30900000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
--
2.17.1


2020-11-02 08:31:23

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support

On Mon, Nov 02, 2020 at 10:16:34AM +0800, Joakim Zhang wrote:
> Add CAN device node and pinctrl on i.MX8MP evk board.
>
> Signed-off-by: Joakim Zhang <[email protected]>
> ---
> ChangeLogs:
> V1->V2:
> * add missing space before '=',
> fsl,clk-source= /bits/ 8 <0> -> fsl,clk-source = /bits/ 8 <0>
> ---
> arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 62 ++++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 30 ++++++++++
> 2 files changed, 92 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> index 908b92bb4dcd..b10dce8767a4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> @@ -33,6 +33,28 @@
> <0x1 0x00000000 0 0xc0000000>;
> };
>
> + reg_can1_stby: regulator-can1-stby {
> + compatible = "regulator-fixed";
> + regulator-name = "can1-stby";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1_reg>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_can2_stby: regulator-can2-stby {
> + compatible = "regulator-fixed";
> + regulator-name = "can2-stby";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2_reg>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> reg_usdhc2_vmmc: regulator-usdhc2 {
> compatible = "regulator-fixed";
> pinctrl-names = "default";
> @@ -45,6 +67,20 @@
> };
> };
>
> +&flexcan1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + xceiver-supply = <&reg_can1_stby>;
> + status = "okay";
> +};
> +
> +&flexcan2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + xceiver-supply = <&reg_can2_stby>;
> + status = "disabled";/* can2 pin conflict with pdm */
> +};
> +
> &fec {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_fec>;
> @@ -144,6 +180,32 @@
> >;
> };
>
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
> + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
> + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
> + >;
> + };
> +
> + pinctrl_flexcan1_reg: flexcan1reggrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /* CAN1_STBY */
> + >;
> + };
> +
> + pinctrl_flexcan2_reg: flexcan2reggrp {
> + fsl,pins = <
> + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154 /* CAN2_STBY */
> + >;
> + };
> +
> pinctrl_gpio_led: gpioledgrp {
> fsl,pins = <
> MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 479312293036..ecccfbb4f5ad 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -552,6 +552,36 @@
> status = "disabled";
> };
>
> + flexcan1: can@308c0000 {
> + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";

Undocumented compatible in Documentation/devicetree/bindings/net/can/fsl-flexcan.txt

Best regards,
Krzysztof

> + reg = <0x308c0000 0x10000>;
> + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
> + <&clk IMX8MP_CLK_CAN1_ROOT>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
> + assigned-clock-rates = <40000000>;
> + fsl,clk-source = /bits/ 8 <0>;
> + fsl,stop-mode = <&gpr 0x10 4>;
> + status = "disabled";
> + };
> +
> + flexcan2: can@308d0000 {
> + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
> + reg = <0x308d0000 0x10000>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
> + <&clk IMX8MP_CLK_CAN2_ROOT>;
> + clock-names = "ipg", "per";
> + assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
> + assigned-clock-rates = <40000000>;
> + fsl,clk-source = /bits/ 8 <0>;
> + fsl,stop-mode = <&gpr 0x10 5>;
> + status = "disabled";
> + };
> +
> crypto: crypto@30900000 {
> compatible = "fsl,sec-v4.0";
> #address-cells = <1>;
> --
> 2.17.1
>

2020-11-03 01:27:53

by Joakim Zhang

[permalink] [raw]
Subject: RE: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support


> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: 2020年11月2日 16:29
> To: Joakim Zhang <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> dl-linux-imx <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support
>
> On Mon, Nov 02, 2020 at 10:16:34AM +0800, Joakim Zhang wrote:
> > Add CAN device node and pinctrl on i.MX8MP evk board.
> >
> > Signed-off-by: Joakim Zhang <[email protected]>
> > ---
> > ChangeLogs:
> > V1->V2:
> > * add missing space before '=',
> > fsl,clk-source= /bits/ 8 <0> -> fsl,clk-source = /bits/ 8 <0>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 62
> ++++++++++++++++++++
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 30 ++++++++++
> > 2 files changed, 92 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > index 908b92bb4dcd..b10dce8767a4 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > @@ -33,6 +33,28 @@
> > <0x1 0x00000000 0 0xc0000000>;
> > };
> >
> > + reg_can1_stby: regulator-can1-stby {
> > + compatible = "regulator-fixed";
> > + regulator-name = "can1-stby";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan1_reg>;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
> > +
> > + reg_can2_stby: regulator-can2-stby {
> > + compatible = "regulator-fixed";
> > + regulator-name = "can2-stby";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan2_reg>;
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > + };
> > +
> > reg_usdhc2_vmmc: regulator-usdhc2 {
> > compatible = "regulator-fixed";
> > pinctrl-names = "default";
> > @@ -45,6 +67,20 @@
> > };
> > };
> >
> > +&flexcan1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan1>;
> > + xceiver-supply = <&reg_can1_stby>;
> > + status = "okay";
> > +};
> > +
> > +&flexcan2 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_flexcan2>;
> > + xceiver-supply = <&reg_can2_stby>;
> > + status = "disabled";/* can2 pin conflict with pdm */ };
> > +
> > &fec {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_fec>;
> > @@ -144,6 +180,32 @@
> > >;
> > };
> >
> > + pinctrl_flexcan1: flexcan1grp {
> > + fsl,pins = <
> > + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
> > + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
> > + >;
> > + };
> > +
> > + pinctrl_flexcan2: flexcan2grp {
> > + fsl,pins = <
> > + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
> > + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
> > + >;
> > + };
> > +
> > + pinctrl_flexcan1_reg: flexcan1reggrp {
> > + fsl,pins = <
> > + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /*
> CAN1_STBY */
> > + >;
> > + };
> > +
> > + pinctrl_flexcan2_reg: flexcan2reggrp {
> > + fsl,pins = <
> > + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154
> /* CAN2_STBY */
> > + >;
> > + };
> > +
> > pinctrl_gpio_led: gpioledgrp {
> > fsl,pins = <
> > MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index 479312293036..ecccfbb4f5ad 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -552,6 +552,36 @@
> > status = "disabled";
> > };
> >
> > + flexcan1: can@308c0000 {
> > + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
>
> Undocumented compatible in
> Documentation/devicetree/bindings/net/can/fsl-flexcan.txt

Hi Krzsztof,

Yes, I will resend the patch after below patch goes into mainline. Thanks.
https://www.spinics.net/lists/linux-can/msg04896.html


Best Regards,
Joakim Zhang
> Best regards,
> Krzysztof
>
> > + reg = <0x308c0000 0x10000>;
> > + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
> > + <&clk IMX8MP_CLK_CAN1_ROOT>;
> > + clock-names = "ipg", "per";
> > + assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
> > + assigned-clock-rates = <40000000>;
> > + fsl,clk-source = /bits/ 8 <0>;
> > + fsl,stop-mode = <&gpr 0x10 4>;
> > + status = "disabled";
> > + };
> > +
> > + flexcan2: can@308d0000 {
> > + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
> > + reg = <0x308d0000 0x10000>;
> > + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
> > + <&clk IMX8MP_CLK_CAN2_ROOT>;
> > + clock-names = "ipg", "per";
> > + assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
> > + assigned-clock-rates = <40000000>;
> > + fsl,clk-source = /bits/ 8 <0>;
> > + fsl,stop-mode = <&gpr 0x10 5>;
> > + status = "disabled";
> > + };
> > +
> > crypto: crypto@30900000 {
> > compatible = "fsl,sec-v4.0";
> > #address-cells = <1>;
> > --
> > 2.17.1
> >

2020-11-03 07:41:13

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support

On Tue, Nov 03, 2020 at 01:23:12AM +0000, Joakim Zhang wrote:
>
> > -----Original Message-----
> > From: Krzysztof Kozlowski <[email protected]>
> > Sent: 2020年11月2日 16:29
> > To: Joakim Zhang <[email protected]>
> > Cc: [email protected]; [email protected]; [email protected];
> > dl-linux-imx <[email protected]>; [email protected];
> > [email protected]; [email protected];
> > [email protected]
> > Subject: Re: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support
> >
> > On Mon, Nov 02, 2020 at 10:16:34AM +0800, Joakim Zhang wrote:
> > > Add CAN device node and pinctrl on i.MX8MP evk board.
> > >
> > > Signed-off-by: Joakim Zhang <[email protected]>
> > > ---
> > > ChangeLogs:
> > > V1->V2:
> > > * add missing space before '=',
> > > fsl,clk-source= /bits/ 8 <0> -> fsl,clk-source = /bits/ 8 <0>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 62
> > ++++++++++++++++++++
> > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 30 ++++++++++
> > > 2 files changed, 92 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > index 908b92bb4dcd..b10dce8767a4 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > @@ -33,6 +33,28 @@
> > > <0x1 0x00000000 0 0xc0000000>;
> > > };
> > >
> > > + reg_can1_stby: regulator-can1-stby {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "can1-stby";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_flexcan1_reg>;
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
> > > + enable-active-high;
> > > + };
> > > +
> > > + reg_can2_stby: regulator-can2-stby {
> > > + compatible = "regulator-fixed";
> > > + regulator-name = "can2-stby";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_flexcan2_reg>;
> > > + regulator-min-microvolt = <3300000>;
> > > + regulator-max-microvolt = <3300000>;
> > > + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
> > > + enable-active-high;
> > > + };
> > > +
> > > reg_usdhc2_vmmc: regulator-usdhc2 {
> > > compatible = "regulator-fixed";
> > > pinctrl-names = "default";
> > > @@ -45,6 +67,20 @@
> > > };
> > > };
> > >
> > > +&flexcan1 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_flexcan1>;
> > > + xceiver-supply = <&reg_can1_stby>;
> > > + status = "okay";
> > > +};
> > > +
> > > +&flexcan2 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_flexcan2>;
> > > + xceiver-supply = <&reg_can2_stby>;
> > > + status = "disabled";/* can2 pin conflict with pdm */ };
> > > +
> > > &fec {
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&pinctrl_fec>;
> > > @@ -144,6 +180,32 @@
> > > >;
> > > };
> > >
> > > + pinctrl_flexcan1: flexcan1grp {
> > > + fsl,pins = <
> > > + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
> > > + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
> > > + >;
> > > + };
> > > +
> > > + pinctrl_flexcan2: flexcan2grp {
> > > + fsl,pins = <
> > > + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
> > > + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
> > > + >;
> > > + };
> > > +
> > > + pinctrl_flexcan1_reg: flexcan1reggrp {
> > > + fsl,pins = <
> > > + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154 /*
> > CAN1_STBY */
> > > + >;
> > > + };
> > > +
> > > + pinctrl_flexcan2_reg: flexcan2reggrp {
> > > + fsl,pins = <
> > > + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154
> > /* CAN2_STBY */
> > > + >;
> > > + };
> > > +
> > > pinctrl_gpio_led: gpioledgrp {
> > > fsl,pins = <
> > > MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index 479312293036..ecccfbb4f5ad 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -552,6 +552,36 @@
> > > status = "disabled";
> > > };
> > >
> > > + flexcan1: can@308c0000 {
> > > + compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
> >
> > Undocumented compatible in
> > Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
>
> Hi Krzsztof,
>
> Yes, I will resend the patch after below patch goes into mainline. Thanks.
> https://www.spinics.net/lists/linux-can/msg04896.html

Thanks for the link. It's all good and there is no need to resend
because your compatible is mentioned there.

Best regards,
Krzysztof

2020-11-03 07:51:01

by Joakim Zhang

[permalink] [raw]
Subject: RE: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support


> -----Original Message-----
> From: Krzysztof Kozlowski <[email protected]>
> Sent: 2020年11月3日 15:39
> To: Joakim Zhang <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> dl-linux-imx <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support
>
> On Tue, Nov 03, 2020 at 01:23:12AM +0000, Joakim Zhang wrote:
> >
> > > -----Original Message-----
> > > From: Krzysztof Kozlowski <[email protected]>
> > > Sent: 2020年11月2日 16:29
> > > To: Joakim Zhang <[email protected]>
> > > Cc: [email protected]; [email protected];
> [email protected];
> > > dl-linux-imx <[email protected]>; [email protected];
> > > [email protected]; [email protected];
> > > [email protected]
> > > Subject: Re: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support
> > >
> > > On Mon, Nov 02, 2020 at 10:16:34AM +0800, Joakim Zhang wrote:
> > > > Add CAN device node and pinctrl on i.MX8MP evk board.
> > > >
> > > > Signed-off-by: Joakim Zhang <[email protected]>
> > > > ---
> > > > ChangeLogs:
> > > > V1->V2:
> > > > * add missing space before '=',
> > > > fsl,clk-source= /bits/ 8 <0> -> fsl,clk-source = /bits/ 8 <0>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 62
> > > ++++++++++++++++++++
> > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 30 ++++++++++
> > > > 2 files changed, 92 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > index 908b92bb4dcd..b10dce8767a4 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
> > > > @@ -33,6 +33,28 @@
> > > > <0x1 0x00000000 0 0xc0000000>;
> > > > };
> > > >
> > > > + reg_can1_stby: regulator-can1-stby {
> > > > + compatible = "regulator-fixed";
> > > > + regulator-name = "can1-stby";
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&pinctrl_flexcan1_reg>;
> > > > + regulator-min-microvolt = <3300000>;
> > > > + regulator-max-microvolt = <3300000>;
> > > > + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
> > > > + enable-active-high;
> > > > + };
> > > > +
> > > > + reg_can2_stby: regulator-can2-stby {
> > > > + compatible = "regulator-fixed";
> > > > + regulator-name = "can2-stby";
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&pinctrl_flexcan2_reg>;
> > > > + regulator-min-microvolt = <3300000>;
> > > > + regulator-max-microvolt = <3300000>;
> > > > + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
> > > > + enable-active-high;
> > > > + };
> > > > +
> > > > reg_usdhc2_vmmc: regulator-usdhc2 {
> > > > compatible = "regulator-fixed";
> > > > pinctrl-names = "default";
> > > > @@ -45,6 +67,20 @@
> > > > };
> > > > };
> > > >
> > > > +&flexcan1 {
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&pinctrl_flexcan1>;
> > > > + xceiver-supply = <&reg_can1_stby>;
> > > > + status = "okay";
> > > > +};
> > > > +
> > > > +&flexcan2 {
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&pinctrl_flexcan2>;
> > > > + xceiver-supply = <&reg_can2_stby>;
> > > > + status = "disabled";/* can2 pin conflict with pdm */ };
> > > > +
> > > > &fec {
> > > > pinctrl-names = "default";
> > > > pinctrl-0 = <&pinctrl_fec>;
> > > > @@ -144,6 +180,32 @@
> > > > >;
> > > > };
> > > >
> > > > + pinctrl_flexcan1: flexcan1grp {
> > > > + fsl,pins = <
> > > > + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
> > > > + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_flexcan2: flexcan2grp {
> > > > + fsl,pins = <
> > > > + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX
> 0x154
> > > > + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_flexcan1_reg: flexcan1reggrp {
> > > > + fsl,pins = <
> > > > + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x154
> /*
> > > CAN1_STBY */
> > > > + >;
> > > > + };
> > > > +
> > > > + pinctrl_flexcan2_reg: flexcan2reggrp {
> > > > + fsl,pins = <
> > > > + MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x154
> > > /* CAN2_STBY */
> > > > + >;
> > > > + };
> > > > +
> > > > pinctrl_gpio_led: gpioledgrp {
> > > > fsl,pins = <
> > > > MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > index 479312293036..ecccfbb4f5ad 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > @@ -552,6 +552,36 @@
> > > > status = "disabled";
> > > > };
> > > >
> > > > + flexcan1: can@308c0000 {
> > > > + compatible = "fsl,imx8mp-flexcan",
> "fsl,imx6q-flexcan";
> > >
> > > Undocumented compatible in
> > > Documentation/devicetree/bindings/net/can/fsl-flexcan.txt
> >
> > Hi Krzsztof,
> >
> > Yes, I will resend the patch after below patch goes into mainline. Thanks.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.
> >
> spinics.net%2Flists%2Flinux-can%2Fmsg04896.html&amp;data=04%7C01%7Cq
> ia
> >
> ngqing.zhang%40nxp.com%7C2f9b2df0480f4de63a6f08d87fcb8ad8%7C686ea1
> d3bc
> >
> 2b4c6fa92cd99c5c301635%7C0%7C0%7C637399859470358123%7CUnknown
> %7CTWFpbG
> >
> Zsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6M
> n0%
> >
> 3D%7C1000&amp;sdata=0Dhxa3tOXVsHySV8wblYoORpwcupGsZzThSdauJH8T
> M%3D&amp
> > ;reserved=0
>
> Thanks for the link. It's all good and there is no need to resend because your
> compatible is mentioned there.


Yes, "fsl,imx8mp-flexcan" compatible string is mentioned there, then could anyone apply this patch? Shawn?

Best Regards,
Joakim Zhang
> Best regards,
> Krzysztof

2020-11-10 00:53:45

by Shawn Guo

[permalink] [raw]
Subject: Re: [PATCH V2] arm64: dts: imx8mp-evk: add CAN support

On Mon, Nov 02, 2020 at 10:16:34AM +0800, Joakim Zhang wrote:
> Add CAN device node and pinctrl on i.MX8MP evk board.
>
> Signed-off-by: Joakim Zhang <[email protected]>

Applied, thanks.