From: Nick Hawkins <[email protected]>
Add support for the SPI flash interface on the GXP SoC.
Signed-off-by: Nick Hawkins <[email protected]>
---
v6:
*No change
v5:
*No change
v4:
*No change
v3:
*No change
v2:
*No change
---
arch/arm/boot/dts/hpe-bmc-dl360gen10.dts | 58 ++++++++++++++++++++++++
arch/arm/boot/dts/hpe-gxp.dtsi | 21 ++++++++-
2 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
index 3a7382ce40ef..d49dcef95c5c 100644
--- a/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
+++ b/arch/arm/boot/dts/hpe-bmc-dl360gen10.dts
@@ -24,3 +24,61 @@
reg = <0x40000000 0x20000000>;
};
};
+
+&spifi {
+ status = "okay";
+ flash@0 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ u-boot@0 {
+ label = "u-boot";
+ reg = <0x0 0x60000>;
+ };
+
+ u-boot-env@60000 {
+ label = "u-boot-env";
+ reg = <0x60000 0x20000>;
+ };
+
+ kernel@80000 {
+ label = "kernel";
+ reg = <0x80000 0x4c0000>;
+ };
+
+ rofs@540000 {
+ label = "rofs";
+ reg = <0x540000 0x1740000>;
+ };
+
+ rwfs@1c80000 {
+ label = "rwfs";
+ reg = <0x1c80000 0x250000>;
+ };
+
+ section@1ed0000{
+ label = "section";
+ reg = <0x1ed0000 0x130000>;
+ };
+ };
+ };
+ flash@1 {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ host-prime@0 {
+ label = "host-prime";
+ reg = <0x0 0x02000000>;
+ };
+
+ host-second@2000000 {
+ label = "host-second";
+ reg = <0x02000000 0x02000000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/hpe-gxp.dtsi b/arch/arm/boot/dts/hpe-gxp.dtsi
index cf735b3c4f35..f28349bdeee1 100644
--- a/arch/arm/boot/dts/hpe-gxp.dtsi
+++ b/arch/arm/boot/dts/hpe-gxp.dtsi
@@ -56,9 +56,28 @@
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
- ranges = <0x0 0xc0000000 0x30000000>;
+ ranges = <0x0 0xc0000000 0x40000000>;
dma-ranges;
+ spifi: spi@200 {
+ compatible = "hpe,gxp-spifi";
+ reg = <0x200 0x80>, <0xc000 0x100>, <0x38000000 0x8000000>;
+ interrupts = <20>;
+ interrupt-parent = <&vic0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ flash@0 {
+ reg = <0>;
+ compatible = "jedec,spi-nor";
+ };
+
+ flash@1 {
+ reg = <1>;
+ compatible = "jedec,spi-nor";
+ };
+ };
+
vic0: interrupt-controller@eff0000 {
compatible = "arm,pl192-vic";
reg = <0xeff0000 0x1000>;
--
2.17.1
Greetings all,
Was there a particular issue with this patch? I just realized that patches 1,2, and 5 were accepted but not 3 or 4.
Thanks,
-Nick Hawkins
On Wed, Oct 5, 2022, at 10:33 PM, Hawkins, Nick wrote:
>
> Was there a particular issue with this patch? I just realized that
> patches 1,2, and 5 were accepted but not 3 or 4.
It looks like you sent the patch to a lot of people, without addressing
anyone in particular. I certainly did not expect to pick it up like this.
When you resend the missing patches after 6.1-rc1, please send the
ones you want to be merged through the soc tree to:[email protected],
with reviewers and mailing lists on Cc, but nobody else as the
recipient.
For the SoC tree, I usually have separate branches for code
changes (usually just Kconfig and MAINTAINERS entries in case of
arm64), devicetree changes, defconfig changes and driver (typically
drivers/soc, but could be others that have no separate subsystem
maintainers), so ideally you send a set of patches or a pull request
for each such topic branch.
Arnd