From: Peng Fan <[email protected]>
V2:
Add R-b tag
Missed to add mailbox maintainer in V1, add in V2
To i.MX generic MU, when linux stop remote core, the MU-B side is not
reset because of hardware design, so MU-B contains valid configuration
when remote core stops. Then when linux start remote core again, linux
may notify remote core before remote core is ready for incoming message.
So we need make sure MU is in reset state before remote core start. So
add a RST channel which is only to reset MU when shutdown the RST mbox
channel.
Peng Fan (2):
dt-bindings: mailbox: imx-mu: add RST channel
mailbox: imx: support RST channel
.../devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++--
drivers/mailbox/imx-mailbox.c | 29 +++++++++++++++----
2 files changed, 27 insertions(+), 8 deletions(-)
--
2.25.1
From: Peng Fan <[email protected]>
i.MX generic MU supports MU-A/B reset feature.
When stop/start remotecore, MU is not reset. So when Linux stop
remotecore, the MU-B side BCR may contain valid configuration,
because MU-B is not reset. So when linux start Mcore
again and notify Mcore, Mcore is not ready to handle MU interrupt
and cause issues. So need reset MU when stop Mcore.
Signed-off-by: Peng Fan <[email protected]>
---
drivers/mailbox/imx-mailbox.c | 29 +++++++++++++++++++++++------
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index b10239d6ef93..37fc765783f8 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -19,7 +19,7 @@
#include <linux/suspend.h>
#include <linux/slab.h>
-#define IMX_MU_CHANS 16
+#define IMX_MU_CHANS 17
/* TX0/RX0/RXDB[0-3] */
#define IMX_MU_SCU_CHANS 6
/* TX0/RX0 */
@@ -35,9 +35,11 @@ enum imx_mu_chan_type {
IMX_MU_TYPE_RX = 1, /* Rx */
IMX_MU_TYPE_TXDB = 2, /* Tx doorbell */
IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
+ IMX_MU_TYPE_RST = 4, /* Reset */
};
enum imx_mu_xcr {
+ IMX_MU_CR,
IMX_MU_GIER,
IMX_MU_GCR,
IMX_MU_TCR,
@@ -50,6 +52,7 @@ enum imx_mu_xsr {
IMX_MU_GSR,
IMX_MU_TSR,
IMX_MU_RSR,
+ IMX_MU_xSR_MAX,
};
struct imx_sc_rpc_msg_max {
@@ -85,7 +88,7 @@ struct imx_mu_priv {
int irq[IMX_MU_CHANS];
bool suspend;
- u32 xcr[4];
+ u32 xcr[IMX_MU_xCR_MAX];
bool side_b;
};
@@ -105,8 +108,8 @@ struct imx_mu_dcfg {
enum imx_mu_type type;
u32 xTR; /* Transmit Register0 */
u32 xRR; /* Receive Register0 */
- u32 xSR[4]; /* Status Registers */
- u32 xCR[4]; /* Control Registers */
+ u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */
+ u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */
};
#define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
@@ -121,6 +124,9 @@ struct imx_mu_dcfg {
#define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
/* General Purpose Interrupt Request */
#define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
+/* MU reset */
+#define IMX_MU_xCR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(5))
+#define IMX_MU_xSR_RST(type) (type & IMX_MU_V2 ? BIT(0) : BIT(7))
static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox)
@@ -497,6 +503,8 @@ static irqreturn_t imx_mu_isr(int irq, void *p)
val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) &
(ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
break;
+ case IMX_MU_TYPE_RST:
+ return IRQ_NONE;
default:
dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n",
cp->type);
@@ -581,6 +589,8 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
{
struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox);
struct imx_mu_con_priv *cp = chan->con_priv;
+ int ret;
+ u32 sr;
if (cp->type == IMX_MU_TYPE_TXDB) {
tasklet_kill(&cp->txdb_tasklet);
@@ -598,6 +608,13 @@ static void imx_mu_shutdown(struct mbox_chan *chan)
case IMX_MU_TYPE_RXDB:
imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx));
break;
+ case IMX_MU_TYPE_RST:
+ imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0);
+ ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr,
+ !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5);
+ if (ret)
+ dev_warn(priv->dev, "RST channel timeout\n");
+ break;
default:
break;
}
@@ -865,7 +882,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = {
.xTR = 0x0,
.xRR = 0x10,
.xSR = {0x20, 0x20, 0x20, 0x20},
- .xCR = {0x24, 0x24, 0x24, 0x24},
+ .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
@@ -888,7 +905,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
.xTR = 0x200,
.xRR = 0x280,
.xSR = {0xC, 0x118, 0x124, 0x12C},
- .xCR = {0x110, 0x114, 0x120, 0x128},
+ .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
--
2.25.1
From: Peng Fan <[email protected]>
i.MX MU has a MUR bit which is to reset both the Processor B and the
Processor A sides of the MU module, forcing all control and status
registers to return to their default values (except the BHR bit in the ACR
register and BHRM bit in BCR register), and all internal states to be
cleared.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
index 7a86e7926dd2..191c1ce15009 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
@@ -72,14 +72,16 @@ properties:
type : Channel type
channel : Channel number
- This MU support 4 type of unidirectional channels, each type
- has 4 channels. A total of 16 channels. Following types are
+ This MU support 5 type of unidirectional channels, each type
+ has 4 channels except RST channel which only has 1 channel.
+ A total of 17 channels. Following types are
supported:
0 - TX channel with 32bit transmit register and IRQ transmit
acknowledgment support.
1 - RX channel with 32bit receive register and IRQ support
2 - TX doorbell channel. Without own register and no ACK support.
3 - RX doorbell channel.
+ 4 - RST channel
const: 2
clocks:
--
2.25.1
Hi,
On Wed, 2022-06-15 at 21:00 +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <[email protected]>
>
> i.MX generic MU supports MU-A/B reset feature.
>
> When stop/start remotecore, MU is not reset. So when Linux stop
> remotecore, the MU-B side BCR may contain valid configuration,
> because MU-B is not reset. So when linux start Mcore
> again and notify Mcore, Mcore is not ready to handle MU interrupt
> and cause issues. So need reset MU when stop Mcore.
>
> Signed-off-by: Peng Fan <[email protected]>
It looks like this patch causes i.MX8qxp MEK boot failure with v6.0-
rc1. After reverting commit 82ab513baed5895c8b0e991557a12fd38d5f25f0,
it boots ok.
There are a lot imx_mu and imx-scu error logs:
----------------------------8<------------------------------------
[ 1.166567] imx-scu system-controller: RPC send msg timeout
[ 1.171843] imx_scu_soc_id: get soc info failed, ret -110
[ 1.177221] imx-scu system-controller: failed to initialize SoC
info: -22
[ 1.184019] imx-scu system-controller: NXP i.MX SCU Initialized
[ 1.230605] imx-scu system-controller: RPC send msg timeout
[ 1.270559] imx-scu system-controller: RPC send msg timeout
[ 1.310561] imx-scu system-controller: RPC send msg timeout
[ 1.350560] imx-scu system-controller: RPC send msg timeout
[ 1.390560] imx-scu system-controller: RPC send msg timeout
[ 1.430561] imx-scu system-controller: RPC send msg timeout
[ 1.470559] imx-scu system-controller: RPC send msg timeout
[ 1.510559] imx-scu system-controller: RPC send msg timeout
[ 1.550559] imx-scu system-controller: RPC send msg timeout
[ 1.590559] imx-scu system-controller: RPC send msg timeout
[ 1.630561] imx-scu system-controller: RPC send msg timeout
[ 1.670558] imx-scu system-controller: RPC send msg timeout
[ 1.710559] imx-scu system-controller: RPC send msg timeout
[ 1.750558] imx-scu system-controller: RPC send msg timeout
[ 1.790559] imx-scu system-controller: RPC send msg timeout
[ 1.830562] imx-scu system-controller: RPC send msg timeout
[ 1.870559] imx-scu system-controller: RPC send msg timeout
[ 1.910559] imx-scu system-controller: RPC send msg timeout
[ 1.950561] imx-scu system-controller: RPC send msg timeout
[ 1.990592] imx-scu system-controller: RPC send msg timeout
[ 1.995838] imx_mu 5d1c0000.mailbox: Try increasing
MBOX_TX_QUEUE_LEN
[ 2.002262] imx-scu system-controller: RPC send msg failed: -105
[ 2.008260] imx_mu 5d1c0000.mailbox: Try increasing
MBOX_TX_QUEUE_LEN
[ 2.014682] imx-scu system-controller: RPC send msg failed: -105
[ 2.020681] imx_mu 5d1c0000.mailbox: Try increasing
MBOX_TX_QUEUE_LEN
[ 2.027103] imx-scu system-controller: RPC send msg failed: -105
[ 2.033105] imx_mu 5d1c0000.mailbox: Try increasing
MBOX_TX_QUEUE_LEN
[ 2.039526] imx-scu system-controller: RPC send msg failed: -105
[ 2.045526] imx_mu 5d1c0000.mailbox: Try increasing
MBOX_TX_QUEUE_LEN
[ 2.051949] imx-scu system-controller: RPC send msg failed: -105
----------------------------8<------------------------------------
Regards,
Liu Ying
> Subject: Re: [PATCH V2 2/2] mailbox: imx: support RST channel
>
> Hi,
>
> On Wed, 2022-06-15 at 21:00 +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <[email protected]>
> >
> > i.MX generic MU supports MU-A/B reset feature.
> >
> > When stop/start remotecore, MU is not reset. So when Linux stop
> > remotecore, the MU-B side BCR may contain valid configuration, because
> > MU-B is not reset. So when linux start Mcore again and notify Mcore,
> > Mcore is not ready to handle MU interrupt and cause issues. So need
> > reset MU when stop Mcore.
> >
> > Signed-off-by: Peng Fan <[email protected]>
>
> It looks like this patch causes i.MX8qxp MEK boot failure with v6.0- rc1. After
> reverting commit 82ab513baed5895c8b0e991557a12fd38d5f25f0,
> it boots ok.
Thanks for your test. Indeed, I only take generic MU into consideration and broke
i.MX8QXP SCU MU. The following patch could resolve the issue, after more
test, I will send a formal patch:
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index f36cb0048ce7..e373ea8b4705 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -893,7 +893,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = {
.xTR = 0x20,
.xRR = 0x40,
.xSR = {0x60, 0x60, 0x60, 0x60},
- .xCR = {0x64, 0x64, 0x64, 0x64},
+ .xCR = {0x64, 0x64, 0x64, 0x64, 0x64},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = {
@@ -916,7 +916,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp_s4 = {
.xTR = 0x200,
.xRR = 0x280,
.xSR = {0xC, 0x118, 0x124, 0x12C},
- .xCR = {0x110, 0x114, 0x120, 0x128},
+ .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
@@ -927,7 +927,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx93_s4 = {
.xTR = 0x200,
.xRR = 0x280,
.xSR = {0xC, 0x118, 0x124, 0x12C},
- .xCR = {0x110, 0x114, 0x120, 0x128},
+ .xCR = {0x8, 0x110, 0x114, 0x120, 0x128},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
@@ -938,7 +938,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_scu = {
.xTR = 0x0,
.xRR = 0x10,
.xSR = {0x20, 0x20, 0x20, 0x20},
- .xCR = {0x24, 0x24, 0x24, 0x24},
+ .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
};
static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
@@ -949,7 +949,7 @@ static const struct imx_mu_dcfg imx_mu_cfg_imx8_seco = {
.xTR = 0x0,
.xRR = 0x10,
.xSR = {0x20, 0x20, 0x20, 0x20},
- .xCR = {0x24, 0x24, 0x24, 0x24},
+ .xCR = {0x24, 0x24, 0x24, 0x24, 0x24},
};
static const struct of_device_id imx_mu_dt_ids[] = {
--
2.37.1
Thanks,
Peng.
>
> There are a lot imx_mu and imx-scu error logs:
>
> ----------------------------8<------------------------------------
> [ 1.166567] imx-scu system-controller: RPC send msg timeout
> [ 1.171843] imx_scu_soc_id: get soc info failed, ret -110
> [ 1.177221] imx-scu system-controller: failed to initialize SoC
> info: -22
> [ 1.184019] imx-scu system-controller: NXP i.MX SCU Initialized
> [ 1.230605] imx-scu system-controller: RPC send msg timeout
> [ 1.270559] imx-scu system-controller: RPC send msg timeout
> [ 1.310561] imx-scu system-controller: RPC send msg timeout
> [ 1.350560] imx-scu system-controller: RPC send msg timeout
> [ 1.390560] imx-scu system-controller: RPC send msg timeout
> [ 1.430561] imx-scu system-controller: RPC send msg timeout
> [ 1.470559] imx-scu system-controller: RPC send msg timeout
> [ 1.510559] imx-scu system-controller: RPC send msg timeout
> [ 1.550559] imx-scu system-controller: RPC send msg timeout
> [ 1.590559] imx-scu system-controller: RPC send msg timeout
> [ 1.630561] imx-scu system-controller: RPC send msg timeout
> [ 1.670558] imx-scu system-controller: RPC send msg timeout
> [ 1.710559] imx-scu system-controller: RPC send msg timeout
> [ 1.750558] imx-scu system-controller: RPC send msg timeout
> [ 1.790559] imx-scu system-controller: RPC send msg timeout
> [ 1.830562] imx-scu system-controller: RPC send msg timeout
> [ 1.870559] imx-scu system-controller: RPC send msg timeout
> [ 1.910559] imx-scu system-controller: RPC send msg timeout
> [ 1.950561] imx-scu system-controller: RPC send msg timeout
> [ 1.990592] imx-scu system-controller: RPC send msg timeout
> [ 1.995838] imx_mu 5d1c0000.mailbox: Try increasing
> MBOX_TX_QUEUE_LEN
> [ 2.002262] imx-scu system-controller: RPC send msg failed: -105
> [ 2.008260] imx_mu 5d1c0000.mailbox: Try increasing
> MBOX_TX_QUEUE_LEN
> [ 2.014682] imx-scu system-controller: RPC send msg failed: -105
> [ 2.020681] imx_mu 5d1c0000.mailbox: Try increasing
> MBOX_TX_QUEUE_LEN
> [ 2.027103] imx-scu system-controller: RPC send msg failed: -105
> [ 2.033105] imx_mu 5d1c0000.mailbox: Try increasing
> MBOX_TX_QUEUE_LEN
> [ 2.039526] imx-scu system-controller: RPC send msg failed: -105
> [ 2.045526] imx_mu 5d1c0000.mailbox: Try increasing
> MBOX_TX_QUEUE_LEN
> [ 2.051949] imx-scu system-controller: RPC send msg failed: -105
> ----------------------------8<------------------------------------
>
> Regards,
> Liu Ying