- Add dt-bindings
- i.MX95 ELE/V2X use same register layout as i.MX8ULP S4 MU, but
the TR/RR num is different. To make code reusable and not add too much
macros, add runtime detect number of TR and RR by reading PAR_OFF
registers.
- Add i.MX95 ELE/V2X MU entry in driver
Signed-off-by: Peng Fan <[email protected]>
---
Peng Fan (3):
dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible
mailbox: imx: get RR/TR registers num from Parameter register
mailbox: imx: support i.MX95 ELE/V2X MU
.../devicetree/bindings/mailbox/fsl,mu.yaml | 8 +++-
drivers/mailbox/imx-mailbox.c | 48 +++++++++++++++++-----
2 files changed, 43 insertions(+), 13 deletions(-)
---
base-commit: ad5c60d66016e544c51ed98635a74073f761f45d
change-id: 20240122-imx-mailbox-243021d12030
Best regards,
--
Peng Fan <[email protected]>
From: Peng Fan <[email protected]>
Add i.MX95 Generic, Secure Enclave and V2X Message Unit compatible string.
Signed-off-by: Peng Fan <[email protected]>
---
Documentation/devicetree/bindings/mailbox/fsl,mu.yaml | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
index 12e7a7d536a3..24e3d8dbc34a 100644
--- a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
@@ -29,10 +29,14 @@ properties:
- const: fsl,imx8ulp-mu
- const: fsl,imx8-mu-scu
- const: fsl,imx8-mu-seco
- - const: fsl,imx93-mu-s4
- const: fsl,imx8ulp-mu-s4
+ - const: fsl,imx93-mu-s4
+ - const: fsl,imx95-mu-ele
+ - const: fsl,imx95-mu-v2x
- items:
- - const: fsl,imx93-mu
+ - enum:
+ - fsl,imx93-mu
+ - fsl,imx95-mu
- const: fsl,imx8ulp-mu
- items:
- enum:
--
2.37.1
From: Peng Fan <[email protected]>
i.MX8ULP, i.MX93 MU has a Parameter register encoded as below:
BIT: 15 --- 8 | 7 --- 0
RR_NUM TR_NUM
So to make driver easy to support more variants, get the RR/TR
registers number from Parameter register.
The patch only adds support the specific MU, such as ELE MU.
For generic MU, not add support for number larger than 4.
Signed-off-by: Peng Fan <[email protected]>
---
drivers/mailbox/imx-mailbox.c | 46 ++++++++++++++++++++++++++++++++-----------
1 file changed, 35 insertions(+), 11 deletions(-)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 656171362fe9..f2a21baded29 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -29,7 +29,9 @@
#define IMX_MU_S4_CHANS 2
#define IMX_MU_CHAN_NAME_SIZE 20
-#define IMX_MU_NUM_RR 4
+#define IMX_MU_V2_PAR_OFF 0x4
+#define IMX_MU_V2_TR_MASK GENMASK(7, 0)
+#define IMX_MU_V2_RR_MASK GENMASK(15, 8)
#define IMX_MU_SECO_TX_TOUT (msecs_to_jiffies(3000))
#define IMX_MU_SECO_RX_TOUT (msecs_to_jiffies(3000))
@@ -93,10 +95,11 @@ struct imx_mu_priv {
struct clk *clk;
int irq[IMX_MU_CHANS];
bool suspend;
-
- u32 xcr[IMX_MU_xCR_MAX];
-
bool side_b;
+
+ u32 xcr[IMX_MU_xCR_MAX];
+ u32 num_tr;
+ u32 num_rr;
};
enum imx_mu_type {
@@ -264,18 +267,17 @@ static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
static int imx_mu_specific_tx(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp, void *data)
{
u32 *arg = data;
+ u32 num_tr = priv->num_tr;
int i, ret;
u32 xsr;
- u32 size, max_size, num_tr;
+ u32 size, max_size;
if (priv->dcfg->type & IMX_MU_V2_S4) {
size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size;
max_size = sizeof(struct imx_s4_rpc_msg_max);
- num_tr = 8;
} else {
size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size;
max_size = sizeof(struct imx_sc_rpc_msg_max);
- num_tr = 4;
}
switch (cp->type) {
@@ -324,6 +326,7 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
int i, ret;
u32 xsr;
u32 size, max_size;
+ u32 num_rr = priv->num_rr;
data = (u32 *)priv->msg;
@@ -345,13 +348,13 @@ static int imx_mu_specific_rx(struct imx_mu_priv *priv, struct imx_mu_con_priv *
for (i = 1; i < size; i++) {
ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr,
- xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0,
+ xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % num_rr), 0,
5 * USEC_PER_SEC);
if (ret) {
dev_err(priv->dev, "timeout read idx %d\n", i);
return ret;
}
- *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
+ *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % num_rr) * 4);
}
imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0);
@@ -737,11 +740,30 @@ static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox,
return imx_mu_xlate(mbox, sp);
}
+static void imx_mu_get_tr_rr(struct imx_mu_priv *priv)
+{
+ u32 val;
+
+ if (priv->dcfg->type & IMX_MU_V2) {
+ val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF);
+ priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
+ priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
+ } else {
+ priv->num_tr = 4;
+ priv->num_rr = 4;
+ }
+}
+
static void imx_mu_init_generic(struct imx_mu_priv *priv)
{
unsigned int i;
unsigned int val;
+ if (priv->num_rr > 4 || priv->num_tr > 4) {
+ WARN_ONCE(true, "%s not support TR/RR larger than 4\n", __func__);
+ return;
+ }
+
for (i = 0; i < IMX_MU_CHANS; i++) {
struct imx_mu_con_priv *cp = &priv->con_priv[i];
@@ -768,8 +790,8 @@ static void imx_mu_init_generic(struct imx_mu_priv *priv)
imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]);
/* Clear any pending RSR */
- for (i = 0; i < IMX_MU_NUM_RR; i++)
- imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4);
+ for (i = 0; i < priv->num_rr; i++)
+ imx_mu_read(priv, priv->dcfg->xRR + i * 4);
}
static void imx_mu_init_specific(struct imx_mu_priv *priv)
@@ -864,6 +886,8 @@ static int imx_mu_probe(struct platform_device *pdev)
return ret;
}
+ imx_mu_get_tr_rr(priv);
+
priv->side_b = of_property_read_bool(np, "fsl,mu-side-b");
priv->dcfg->init(priv);
--
2.37.1
From: Peng Fan <[email protected]>
Add i.MX95 ELE/V2X MU support, its register layout is same as
i.MX8ULP, but the Parameter registers would show different
TR/RR. Since the driver already supports get TR/RR from Parameter
registers, not hardcoding the number, this patch just add
the compatible entry to reuse i.MX8ULP S4 cfg data.
Signed-off-by: Peng Fan <[email protected]>
---
drivers/mailbox/imx-mailbox.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index f2a21baded29..966503a5e9e3 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -1018,6 +1018,8 @@ static const struct of_device_id imx_mu_dt_ids[] = {
{ .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
{ .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
{ .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
+ { .compatible = "fsl,imx95-mu-ele", .data = &imx_mu_cfg_imx8ulp_s4 },
+ { .compatible = "fsl,imx95-mu-v2x", .data = &imx_mu_cfg_imx8ulp_s4 },
{ .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
{ .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
{ },
--
2.37.1
Sorry, please ignore this patchset, button pushed early.
Thanks,
Peng.
> Subject: [PATCH 0/3] mailbox: imx: support i.MX95 ELE/V2X MU
>
> - Add dt-bindings
> - i.MX95 ELE/V2X use same register layout as i.MX8ULP S4 MU, but
> the TR/RR num is different. To make code reusable and not add too much
> macros, add runtime detect number of TR and RR by reading PAR_OFF
> registers.
> - Add i.MX95 ELE/V2X MU entry in driver
>
> Signed-off-by: Peng Fan <[email protected]>
> ---
> Peng Fan (3):
> dt-bindings: mailbox: fsl,mu: add i.MX95 Generic/ELE/V2X MU compatible
> mailbox: imx: get RR/TR registers num from Parameter register
> mailbox: imx: support i.MX95 ELE/V2X MU
>
> .../devicetree/bindings/mailbox/fsl,mu.yaml | 8 +++-
> drivers/mailbox/imx-mailbox.c | 48 +++++++++++++++++-----
> 2 files changed, 43 insertions(+), 13 deletions(-)
> ---
> base-commit: ad5c60d66016e544c51ed98635a74073f761f45d
> change-id: 20240122-imx-mailbox-243021d12030
>
> Best regards,
> --
> Peng Fan <[email protected]>
Hi Peng,
kernel test robot noticed the following build errors:
[auto build test ERROR on ad5c60d66016e544c51ed98635a74073f761f45d]
url: https://github.com/intel-lab-lkp/linux/commits/Peng-Fan-OSS/dt-bindings-mailbox-fsl-mu-add-i-MX95-Generic-ELE-V2X-MU-compatible/20240122-100424
base: ad5c60d66016e544c51ed98635a74073f761f45d
patch link: https://lore.kernel.org/r/20240122-imx-mailbox-v1-2-81413f655210%40nxp.com
patch subject: [PATCH 2/3] mailbox: imx: get RR/TR registers num from Parameter register
config: i386-buildonly-randconfig-003-20240123 (https://download.01.org/0day-ci/archive/20240123/[email protected]/config)
compiler: gcc-11 (Debian 11.3.0-12) 11.3.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20240123/[email protected]/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
All errors (new ones prefixed by >>):
drivers/mailbox/imx-mailbox.c: In function 'imx_mu_get_tr_rr':
>> drivers/mailbox/imx-mailbox.c:749:32: error: implicit declaration of function 'FIELD_GET' [-Werror=implicit-function-declaration]
749 | priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
| ^~~~~~~~~
cc1: some warnings being treated as errors
vim +/FIELD_GET +749 drivers/mailbox/imx-mailbox.c
742
743 static void imx_mu_get_tr_rr(struct imx_mu_priv *priv)
744 {
745 u32 val;
746
747 if (priv->dcfg->type & IMX_MU_V2) {
748 val = imx_mu_read(priv, IMX_MU_V2_PAR_OFF);
> 749 priv->num_tr = FIELD_GET(IMX_MU_V2_TR_MASK, val);
750 priv->num_rr = FIELD_GET(IMX_MU_V2_RR_MASK, val);
751 } else {
752 priv->num_tr = 4;
753 priv->num_rr = 4;
754 }
755 }
756
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki