I am _not_ obsessed with power management.
I am _not_ obsessed with power management.
I am _not_ obsessed with power management.
Ok now that that's been cleared up, this patch enables suspend-on-hlt
(Geode GXn CPU power management) and enables the SUSP# pin on the CPU
which allows APM to function. Which brings me on to my next question, does
APM on Geode GXn work? The datasheet specifies that in order for the
processor to enter suspend mode (in response to SUSP# assertion) the first
criteria which must be met is that the USE_SUSP bit must be set (CCR2 bit
7). Part two of the patch simply enables extended MMX instructions for the
GXn.
I'd be interested to hear of any problems with this.
Cheers,
Zwane
Diffed against 2.4.19-pre2-ac3
--- arch/i386/kernel/setup.c.orig Sat Mar 16 09:45:46 2002
+++ arch/i386/kernel/setup.c Sat Mar 16 11:14:56 2002
@@ -71,6 +71,9 @@
* CacheSize bug workaround updates for AMD, Intel & VIA Cyrix.
* Dave Jones <[email protected]>, September, October 2001.
*
+ * Added additional support for Natsemi/Cyrix Geode GXn CPUs,
+ * Enabled power management and extended MMX instructions.
+ * Zwane Mwaikambo <[email protected]>, March 2002.
*/
/*
@@ -1509,6 +1512,12 @@
/* GXm supports extended cpuid levels 'ala' AMD */
if (c->cpuid_level == 2) {
+ /* Enable Natsemi MMX extensions */
+ setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
+
+ /* Suspend on halt power saving and enable #SUSP pin */
+ setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x88);
+
get_model_name(c); /* get CPU marketing name */
/*
* The 5510/5520 companion chips have a funky PIT
> which allows APM to function. Which brings me on to my next question, does
> APM on Geode GXn work? The datasheet specifies that in order for the
> processor to enter suspend mode (in response to SUSP# assertion) the first
> criteria which must be met is that the USE_SUSP bit must be set (CCR2 bit
> 7). Part two of the patch simply enables extended MMX instructions for the
> GXn.
Be very careful playing with Cyrix/Geode stuff. In the APM case the BIOS
is doing the right thing on every box I have ever seen. The extended MMX
one looks right, providing we don't turn it on for any CPU lacking it
On Sat, 16 Mar 2002, Alan Cox wrote:
> Be very careful playing with Cyrix/Geode stuff. In the APM case the BIOS
> is doing the right thing on every box I have ever seen. The extended MMX
> one looks right, providing we don't turn it on for any CPU lacking it
Hmm thanks for the warning, i wonder if the BIOS enables most of the APM
features of the CPU as well.
Zwane
Here it is without the PM stuff, also i seemed to have diffed it wrong
last time.
Zwane
--- linux-2.4.19-pre2-ac/arch/i386/kernel/setup.c.orig Sun Mar 17 10:14:20 2002
+++ linux-2.4.19-pre2-ac/arch/i386/kernel/setup.c Sun Mar 17 10:32:52 2002
@@ -1509,6 +1509,9 @@
/* GXm supports extended cpuid levels 'ala' AMD */
if (c->cpuid_level == 2) {
+ /* Enable Natsemi MMX extensions */
+ setCx86(CX86_CCR7, getCx86(CX86_CCR7) | 1);
+
get_model_name(c); /* get CPU marketing name */
/*
* The 5510/5520 companion chips have a funky PIT
> > is doing the right thing on every box I have ever seen. The extended MMX
> > one looks right, providing we don't turn it on for any CPU lacking it
>
> Hmm thanks for the warning, i wonder if the BIOS enables most of the APM
> features of the CPU as well.
The ones I've looked at do - remember any Geode BIOS is customised for that
CPU alone and already has either VSA1 or VSA2 built into it - its not like
a socket 7 board where many machines have CPU's newer than the bios
On Sun, 17 Mar 2002, Alan Cox wrote:
> The ones I've looked at do - remember any Geode BIOS is customised for that
> CPU alone and already has either VSA1 or VSA2 built into it - its not like
> a socket 7 board where many machines have CPU's newer than the bios
Cool, it all makes sense i'll back off this one, for now...
/me goes back to evil-power-management-scheming drawing board >8)
Thanks,
Zwane