2024-06-12 08:16:07

by Thomas Bonnefille

Subject: [PATCH v2 0/6] Add board support for Sipeed LicheeRV Nano

The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
minimal device tree files for this board to make it boot to a basic
shell.

Signed-off-by: Thomas Bonnefille <[email protected]>
---
Changes in v2:
- Add SDHCI support
- Change device tree name to match the Makefile
- Add oscillator frequency
- Add aliases to other UARTs
- Add aliases to GPIOs
- Move compatible for SDHCI from common DT to specific DT
- Link to v1: https://lore.kernel.org/r/[email protected]

---
Thomas Bonnefille (6):
riscv: dts: sophgo: Put sdhci compatible in dt of specific SoC
dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
dt-bindings: timer: Add SOPHGO SG2002 clint
dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
riscv: dts: sophgo: Add initial SG2002 SoC device tree
riscv: dts: sophgo: Add LicheeRV Nano board device tree

.../interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/sophgo.yaml | 5 ++
.../devicetree/bindings/timer/sifive,clint.yaml | 1 +
arch/riscv/boot/dts/sophgo/Makefile | 1 +
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 1 -
.../boot/dts/sophgo/sg2002-licheerv-nano-b.dts | 53 ++++++++++++++++++++++
arch/riscv/boot/dts/sophgo/sg2002.dtsi | 34 ++++++++++++++
8 files changed, 99 insertions(+), 1 deletion(-)
---
base-commit: 83a7eefedc9b56fe7bfeff13b6c7356688ffa670
change-id: 20240515-sg2002-93dce1d263be

Best regards,
--
Thomas Bonnefille <[email protected]>

2024-06-12 08:16:18

by Thomas Bonnefille

Subject: [PATCH v2 1/6] riscv: dts: sophgo: Put sdhci compatible in dt of specific SoC

Remove SDHCI compatible for CV1800b from common dtsi file to put it in
the specific dtsi file of the CV1800b.
This commits aims at following the same guidelines as in the other nodes
of the CV18XX family.

Signed-off-by: Thomas Bonnefille <[email protected]>
---
arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++++
arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 1 -
2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index ec9530972ae2..b9cd51457b4c 100644
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -25,3 +25,7 @@ &clint {
&clk {
compatible = "sophgo,cv1800-clk";
};
+
+&sdhci0 {
+ compatible = "sophgo,cv1800b-dwcmshc";
+};
diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f..7247c7c3013c 100644
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -288,7 +288,6 @@ uart4: serial@41c0000 {
};

sdhci0: mmc@4310000 {
- compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4310000 0x1000>;
interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD0>,

--
2.45.2

2024-06-12 10:48:30

by Inochi Amaoto

Subject: Re: [PATCH v2 1/6] riscv: dts: sophgo: Put sdhci compatible in dt of specific SoC

On Wed, Jun 12, 2024 at 10:02:31AM GMT, Thomas Bonnefille wrote:
> Remove SDHCI compatible for CV1800b from common dtsi file to put it in
> the specific dtsi file of the CV1800b.
> This commits aims at following the same guidelines as in the other nodes
> of the CV18XX family.
>
> Signed-off-by: Thomas Bonnefille <[email protected]>
> ---
> arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 4 ++++
> arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 1 -
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> index ec9530972ae2..b9cd51457b4c 100644
> --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> @@ -25,3 +25,7 @@ &clint {
> &clk {
> compatible = "sophgo,cv1800-clk";
> };
> +
> +&sdhci0 {
> + compatible = "sophgo,cv1800b-dwcmshc";
> +};
> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> index 891932ae470f..7247c7c3013c 100644
> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
> @@ -288,7 +288,6 @@ uart4: serial@41c0000 {
> };
>
> sdhci0: mmc@4310000 {
> - compatible = "sophgo,cv1800b-dwcmshc";
> reg = <0x4310000 0x1000>;
> interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk CLK_AXI4_SD0>,
>
> --
> 2.45.2
>

Hi, Jisheng,

Is this change necessary? IIRC, the sdhci is the same across
the whole series.

Regards,
Inochi