Changes in V3:
- fixed the build errors reported by 'kernel test robot'.
- Only perform clock pause in RGMII fixed-link usecase.
Changes in V2:
- Call fix_mac_speed() with new mode parameter added.
- reorg the function of imx_dwmac_fix_speed_mx93 by using the
mode parameter.
Shenwei Wang (2):
net: stmmac: add new mode parameter for fix_mac_speed
net: stmmac: dwmac-imx: pause the TXC clock in fixed-link
.../stmicro/stmmac/dwmac-dwc-qos-eth.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac-imx.c | 44 ++++++++++++++++++-
.../stmicro/stmmac/dwmac-intel-plat.c | 4 +-
.../ethernet/stmicro/stmmac/dwmac-ipq806x.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac-meson.c | 2 +-
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac-rk.c | 2 +-
.../ethernet/stmicro/stmmac/dwmac-socfpga.c | 2 +-
.../ethernet/stmicro/stmmac/dwmac-starfive.c | 2 +-
.../net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 2 +-
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 2 +-
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
include/linux/stmmac.h | 2 +-
13 files changed, 56 insertions(+), 14 deletions(-)
--
2.34.1
When using a fixed-link setup, certain devices like the SJA1105 require a
small pause in the TXC clock line to enable their internal tunable
delay line (TDL).
To satisfy this requirement, this patch temporarily disables the TX clock,
and restarts it after a required period. This provides the required
silent interval on the clock line for SJA1105 to complete the frequency
transition and enable the internal TDLs.
So far we have only enabled this feature on the i.MX93 platform.
Signed-off-by: Shenwei Wang <[email protected]>
Reviewed-by: Frank Li <[email protected]>
---
.../net/ethernet/stmicro/stmmac/dwmac-imx.c | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
index 53ee5a42c071..2e4173d099f3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
@@ -32,6 +32,7 @@
#define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
#define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
+#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
#define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
#define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
#define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
@@ -40,6 +41,7 @@
#define DMA_BUS_MODE 0x00001000
#define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
#define RMII_RESET_SPEED (0x3 << 14)
+#define CTRL_SPEED_MASK GENMASK(15, 14)
struct imx_dwmac_ops {
u32 addr_width;
@@ -56,6 +58,7 @@ struct imx_priv_data {
struct regmap *intf_regmap;
u32 intf_reg_off;
bool rmii_refclk_ext;
+ void __iomem *base_addr;
const struct imx_dwmac_ops *ops;
struct plat_stmmacenet_data *plat_dat;
@@ -212,6 +215,42 @@ static void imx_dwmac_fix_speed(void *priv, uint speed, uint mode)
dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
}
+static void imx_dwmac_fix_speed_mx93(void *priv, uint speed, uint mode)
+{
+ struct imx_priv_data *dwmac = priv;
+ int ctrl, old_ctrl, iface;
+
+ imx_dwmac_fix_speed(priv, speed, mode);
+
+ if (!dwmac || mode != MLO_AN_FIXED)
+ return;
+
+ if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
+ return;
+
+ iface &= MX93_GPR_ENET_QOS_INTF_MASK;
+ if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
+ return;
+
+ old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
+ ctrl = old_ctrl & ~CTRL_SPEED_MASK;
+ regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
+ MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
+ writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
+
+ /* Ensure the settings for CTRL are applied and avoid CPU/Compiler
+ * reordering.
+ */
+ wmb();
+
+ usleep_range(10, 20);
+ iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
+ regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
+ MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
+
+ writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG);
+}
+
static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
{
struct plat_stmmacenet_data *plat_dat = priv;
@@ -317,8 +356,11 @@ static int imx_dwmac_probe(struct platform_device *pdev)
plat_dat->exit = imx_dwmac_exit;
plat_dat->clks_config = imx_dwmac_clks_config;
plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
+ if (of_machine_is_compatible("fsl,imx93"))
+ plat_dat->fix_mac_speed = imx_dwmac_fix_speed_mx93;
plat_dat->bsp_priv = dwmac;
dwmac->plat_dat = plat_dat;
+ dwmac->base_addr = stmmac_res.addr;
ret = imx_dwmac_clks_config(dwmac, true);
if (ret)
--
2.34.1
On 31.07.2023 11:19:29, Shenwei Wang wrote:
> When using a fixed-link setup, certain devices like the SJA1105 require a
> small pause in the TXC clock line to enable their internal tunable
> delay line (TDL).
>
> To satisfy this requirement, this patch temporarily disables the TX clock,
> and restarts it after a required period. This provides the required
> silent interval on the clock line for SJA1105 to complete the frequency
> transition and enable the internal TDLs.
>
> So far we have only enabled this feature on the i.MX93 platform.
>
> Signed-off-by: Shenwei Wang <[email protected]>
> Reviewed-by: Frank Li <[email protected]>
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 42 +++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> index 53ee5a42c071..2e4173d099f3 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> @@ -32,6 +32,7 @@
> #define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
>
> #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
> +#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
> #define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
> #define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
> #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
> @@ -40,6 +41,7 @@
> #define DMA_BUS_MODE 0x00001000
> #define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
> #define RMII_RESET_SPEED (0x3 << 14)
> +#define CTRL_SPEED_MASK GENMASK(15, 14)
>
> struct imx_dwmac_ops {
> u32 addr_width;
> @@ -56,6 +58,7 @@ struct imx_priv_data {
> struct regmap *intf_regmap;
> u32 intf_reg_off;
> bool rmii_refclk_ext;
> + void __iomem *base_addr;
>
> const struct imx_dwmac_ops *ops;
> struct plat_stmmacenet_data *plat_dat;
> @@ -212,6 +215,42 @@ static void imx_dwmac_fix_speed(void *priv, uint speed, uint mode)
> dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
> }
>
> +static void imx_dwmac_fix_speed_mx93(void *priv, uint speed, uint mode)
> +{
> + struct imx_priv_data *dwmac = priv;
> + int ctrl, old_ctrl, iface;
regmap_read() wants a pointer to an "unsigned int".
> +
> + imx_dwmac_fix_speed(priv, speed, mode);
> +
> + if (!dwmac || mode != MLO_AN_FIXED)
> + return;
> +
> + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
> + return;
> +
> + iface &= MX93_GPR_ENET_QOS_INTF_MASK;
> + if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
> + return;
> +
> + old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
> + ctrl = old_ctrl & ~CTRL_SPEED_MASK;
> + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
> + MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
> + writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
> +
> + /* Ensure the settings for CTRL are applied and avoid CPU/Compiler
> + * reordering.
> + */
> + wmb();
> +
> + usleep_range(10, 20);
> + iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
> + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
> + MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
> +
> + writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG);
> +}
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung Nürnberg | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
On Tue, Aug 01, 2023 at 02:47:46PM +0200, Johannes Zink wrote:
> Hi Shenwei,
>
> thanks for your patch.
>
> On 7/31/23 18:19, Shenwei Wang wrote:
> > When using a fixed-link setup, certain devices like the SJA1105 require a
> > small pause in the TXC clock line to enable their internal tunable
> > delay line (TDL).
>
> If this is only required for some devices, is it safe to enforce this
> behaviour unconditionally for any kind of fixed link devices connected to
> the MX93 EQOS or could this possibly break for other devices?
This same point has been raised by Andrew Halaney in message-id
<4govb566nypifbtqp5lcbsjhvoyble5luww3onaa2liinboguf@4kgihys6vhrg>
and Fabio Estevam in message-id
<CAOMZO5ANQmVbk_jy7qdVtzs3716FisT2c72W+3WZyu7FoAochw@mail.gmail.com>
but we don't seem to have any answer for it.
Also, the patch still uses wmb() between the write and the delay, and as
Will Deacon pointed out in his message, message-id
<20230728153611.GH21718@willie-the-truck>
this is not safe, yet still a new version was sent.
It seems the author of these patches is pretty resistant to comments,
and has shown that when I was requesting changes - it was an awful
struggle to get changes made. I'm now of the opinion that I really
can't be bothered to review these patches, precisely because feedback
is clearly not welcome or if welcome, apparently acted upon.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
Hi Shenwei,
thanks for your patch.
On 7/31/23 18:19, Shenwei Wang wrote:
> When using a fixed-link setup, certain devices like the SJA1105 require a
> small pause in the TXC clock line to enable their internal tunable
> delay line (TDL).
If this is only required for some devices, is it safe to enforce this behaviour
unconditionally for any kind of fixed link devices connected to the MX93 EQOS
or could this possibly break for other devices?
Best regards
Johannes
>
> To satisfy this requirement, this patch temporarily disables the TX clock,
> and restarts it after a required period. This provides the required
> silent interval on the clock line for SJA1105 to complete the frequency
> transition and enable the internal TDLs.
>
> So far we have only enabled this feature on the i.MX93 platform.
>
> Signed-off-by: Shenwei Wang <[email protected]>
> Reviewed-by: Frank Li <[email protected]>
> ---
> .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 42 +++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> index 53ee5a42c071..2e4173d099f3 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> @@ -32,6 +32,7 @@
> #define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
>
> #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
> +#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
> #define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
> #define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
> #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
> @@ -40,6 +41,7 @@
> #define DMA_BUS_MODE 0x00001000
> #define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
> #define RMII_RESET_SPEED (0x3 << 14)
> +#define CTRL_SPEED_MASK GENMASK(15, 14)
>
> struct imx_dwmac_ops {
> u32 addr_width;
> @@ -56,6 +58,7 @@ struct imx_priv_data {
> struct regmap *intf_regmap;
> u32 intf_reg_off;
> bool rmii_refclk_ext;
> + void __iomem *base_addr;
>
> const struct imx_dwmac_ops *ops;
> struct plat_stmmacenet_data *plat_dat;
> @@ -212,6 +215,42 @@ static void imx_dwmac_fix_speed(void *priv, uint speed, uint mode)
> dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
> }
>
> +static void imx_dwmac_fix_speed_mx93(void *priv, uint speed, uint mode)
> +{
> + struct imx_priv_data *dwmac = priv;
> + int ctrl, old_ctrl, iface;
> +
> + imx_dwmac_fix_speed(priv, speed, mode);
> +
> + if (!dwmac || mode != MLO_AN_FIXED)
> + return;
> +
> + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
> + return;
> +
> + iface &= MX93_GPR_ENET_QOS_INTF_MASK;
> + if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
> + return;
> +
> + old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
> + ctrl = old_ctrl & ~CTRL_SPEED_MASK;
> + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
> + MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
> + writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
> +
> + /* Ensure the settings for CTRL are applied and avoid CPU/Compiler
> + * reordering.
> + */
> + wmb();
> +
> + usleep_range(10, 20);
> + iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
> + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
> + MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
> +
> + writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG);
> +}
> +
> static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
> {
> struct plat_stmmacenet_data *plat_dat = priv;
> @@ -317,8 +356,11 @@ static int imx_dwmac_probe(struct platform_device *pdev)
> plat_dat->exit = imx_dwmac_exit;
> plat_dat->clks_config = imx_dwmac_clks_config;
> plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
> + if (of_machine_is_compatible("fsl,imx93"))
> + plat_dat->fix_mac_speed = imx_dwmac_fix_speed_mx93;
> plat_dat->bsp_priv = dwmac;
> dwmac->plat_dat = plat_dat;
> + dwmac->base_addr = stmmac_res.addr;
>
> ret = imx_dwmac_clks_config(dwmac, true);
> if (ret)
--
Pengutronix e.K. | Johannes Zink |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686| Fax: +49-5121-206917-5555 |
> -----Original Message-----
> From: Russell King <[email protected]>
> Sent: Tuesday, August 1, 2023 7:57 AM
> To: Johannes Zink <[email protected]>
> Cc: Shenwei Wang <[email protected]>; David S. Miller
> <[email protected]>; Eric Dumazet <[email protected]>; Jakub
> Kicinski <[email protected]>; Paolo Abeni <[email protected]>; Maxime
> Coquelin <[email protected]>; Shawn Guo <[email protected]>;
> Sascha Hauer <[email protected]>; Neil Armstrong
> <[email protected]>; Kevin Hilman <[email protected]>; Vinod
> Koul <[email protected]>; Chen-Yu Tsai <[email protected]>; Jernej Skrabec
> <[email protected]>; Samuel Holland <[email protected]>;
> Giuseppe Cavallaro <[email protected]>; Alexandre Torgue
> <[email protected]>; Jose Abreu <[email protected]>;
> Pengutronix Kernel Team <[email protected]>; Fabio Estevam
> <[email protected]>; dl-linux-imx <[email protected]>; Jerome Brunet
> <[email protected]>; Martin Blumenstingl
> <[email protected]>; Bhupesh Sharma
> <[email protected]>; Nobuhiro Iwamatsu
> <[email protected]>; Simon Horman
> <[email protected]>; Andrew Halaney <[email protected]>;
> Bartosz Golaszewski <[email protected]>; Wong Vee Khee
> <[email protected]>; Revanth Kumar Uppala <[email protected]>; Jochen
> Henneberg <[email protected]>; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Frank Li <[email protected]>
> Subject: [EXT] Re: [PATCH v3 net 2/2] net: stmmac: dwmac-imx: pause the TXC
> clock in fixed-link
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
>
>
> On Tue, Aug 01, 2023 at 02:47:46PM +0200, Johannes Zink wrote:
> > Hi Shenwei,
> >
> > thanks for your patch.
> >
> > On 7/31/23 18:19, Shenwei Wang wrote:
> > > When using a fixed-link setup, certain devices like the SJA1105
> > > require a small pause in the TXC clock line to enable their internal
> > > tunable delay line (TDL).
> >
> > If this is only required for some devices, is it safe to enforce this
> > behaviour unconditionally for any kind of fixed link devices connected
> > to the MX93 EQOS or could this possibly break for other devices?
>
> This same point has been raised by Andrew Halaney in message-id
> <4govb566nypifbtqp5lcbsjhvoyble5luww3onaa2liinboguf@4kgihys6vhrg>
> and Fabio Estevam in message-id
>
> <[email protected].
> com>
> but we don't seem to have any answer for it.
>
Hi Russell,
I hope you have thoroughly read all of my earlier responses, as I believe I already addressed this question.
I'm happy to clarify further, but kindly avoid unsubstantiated comments.
https://lore.kernel.org/imx/[email protected]/T/#m08da3797a056d4d8ea4c1d8956b445ae967e7cfa
" Yes, that's the purpose because it won't hurt even the other side is not SJA1105."
> Also, the patch still uses wmb() between the write and the delay, and as Will
> Deacon pointed out in his message, message-id
> <20230728153611.GH21718@willie-the-truck>
> this is not safe, yet still a new version was sent.
>
Can we conclude that even without the wmb() here, the desired delay time between
operations can still be ensured?
Thanks,
Shenwei
> It seems the author of these patches is pretty resistant to comments, and has
> shown that when I was requesting changes - it was an awful struggle to get
> changes made. I'm now of the opinion that I really can't be bothered to review
> these patches, precisely because feedback is clearly not welcome or if welcome,
> apparently acted upon.
>
> --
> RMK's Patch system:
> https://www.ar/
> mlinux.org.uk%2Fdeveloper%2Fpatches%2F&data=05%7C01%7Cshenwei.wang
> %40nxp.com%7Ce65ab380ff5b4748da5308db928ec751%7C686ea1d3bc2b4c6fa
> 92cd99c5c301635%7C0%7C0%7C638264914150592989%7CUnknown%7CTWFp
> bGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6
> Mn0%3D%7C3000%7C%7C%7C&sdata=%2FzSqRqJFRQljX6ky3XJvfkMH9PwgOstb
> w8HpEppYOIM%3D&reserved=0
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
> -----Original Message-----
> From: Johannes Zink <[email protected]>
> Sent: Tuesday, August 1, 2023 7:48 AM
> To: Shenwei Wang <[email protected]>; Russell King
> <[email protected]>; David S. Miller <[email protected]>; Eric
> Dumazet <[email protected]>; Jakub Kicinski <[email protected]>; Paolo
> Abeni <[email protected]>; Maxime Coquelin
> <[email protected]>; Shawn Guo <[email protected]>; Sascha
> Hauer <[email protected]>; Neil Armstrong <[email protected]>;
> Kevin Hilman <[email protected]>; Vinod Koul <[email protected]>; Chen-
> Yu Tsai <[email protected]>; Jernej Skrabec <[email protected]>; Samuel
> Holland <[email protected]>
> Cc: Giuseppe Cavallaro <[email protected]>; Alexandre Torgue
> <[email protected]>; Jose Abreu <[email protected]>;
> Pengutronix Kernel Team <[email protected]>; Fabio Estevam
> <[email protected]>; dl-linux-imx <[email protected]>; Jerome Brunet
> <[email protected]>; Martin Blumenstingl
> <[email protected]>; Bhupesh Sharma
> <[email protected]>; Nobuhiro Iwamatsu
> <[email protected]>; Simon Horman
> <[email protected]>; Andrew Halaney <[email protected]>;
> Bartosz Golaszewski <[email protected]>; Wong Vee Khee
> <[email protected]>; Revanth Kumar Uppala <[email protected]>; Jochen
> Henneberg <[email protected]>; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Frank Li <[email protected]>
> Subject: [EXT] Re: [PATCH v3 net 2/2] net: stmmac: dwmac-imx: pause the TXC
> clock in fixed-link
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
>
>
> Hi Shenwei,
>
> thanks for your patch.
>
> On 7/31/23 18:19, Shenwei Wang wrote:
> > When using a fixed-link setup, certain devices like the SJA1105
> > require a small pause in the TXC clock line to enable their internal
> > tunable delay line (TDL).
>
> If this is only required for some devices, is it safe to enforce this behaviour
> unconditionally for any kind of fixed link devices connected to the MX93 EQOS
> or could this possibly break for other devices?
>
It won't impact normal devices. The link layer hasn't built up yet.
Thanks,
Shenwei
> Best regards
> Johannes
>
> >
> > To satisfy this requirement, this patch temporarily disables the TX
> > clock, and restarts it after a required period. This provides the
> > required silent interval on the clock line for SJA1105 to complete the
> > frequency transition and enable the internal TDLs.
> >
> > So far we have only enabled this feature on the i.MX93 platform.
> >
> > Signed-off-by: Shenwei Wang <[email protected]>
> > Reviewed-by: Frank Li <[email protected]>
> > ---
> > .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 42 +++++++++++++++++++
> > 1 file changed, 42 insertions(+)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> > b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> > index 53ee5a42c071..2e4173d099f3 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> > @@ -32,6 +32,7 @@
> > #define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
> >
> > #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
> > +#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
> > #define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
> > #define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
> > #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
> > @@ -40,6 +41,7 @@
> > #define DMA_BUS_MODE 0x00001000
> > #define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
> > #define RMII_RESET_SPEED (0x3 << 14)
> > +#define CTRL_SPEED_MASK GENMASK(15, 14)
> >
> > struct imx_dwmac_ops {
> > u32 addr_width;
> > @@ -56,6 +58,7 @@ struct imx_priv_data {
> > struct regmap *intf_regmap;
> > u32 intf_reg_off;
> > bool rmii_refclk_ext;
> > + void __iomem *base_addr;
> >
> > const struct imx_dwmac_ops *ops;
> > struct plat_stmmacenet_data *plat_dat; @@ -212,6 +215,42 @@
> > static void imx_dwmac_fix_speed(void *priv, uint speed, uint mode)
> > dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
> > }
> >
> > +static void imx_dwmac_fix_speed_mx93(void *priv, uint speed, uint
> > +mode) {
> > + struct imx_priv_data *dwmac = priv;
> > + int ctrl, old_ctrl, iface;
> > +
> > + imx_dwmac_fix_speed(priv, speed, mode);
> > +
> > + if (!dwmac || mode != MLO_AN_FIXED)
> > + return;
> > +
> > + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
> > + return;
> > +
> > + iface &= MX93_GPR_ENET_QOS_INTF_MASK;
> > + if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
> > + return;
> > +
> > + old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
> > + ctrl = old_ctrl & ~CTRL_SPEED_MASK;
> > + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
> > + MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
> > + writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
> > +
> > + /* Ensure the settings for CTRL are applied and avoid CPU/Compiler
> > + * reordering.
> > + */
> > + wmb();
> > +
> > + usleep_range(10, 20);
> > + iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
> > + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
> > + MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
> > +
> > + writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG); }
> > +
> > static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
> > {
> > struct plat_stmmacenet_data *plat_dat = priv; @@ -317,8 +356,11
> > @@ static int imx_dwmac_probe(struct platform_device *pdev)
> > plat_dat->exit = imx_dwmac_exit;
> > plat_dat->clks_config = imx_dwmac_clks_config;
> > plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
> > + if (of_machine_is_compatible("fsl,imx93"))
> > + plat_dat->fix_mac_speed = imx_dwmac_fix_speed_mx93;
> > plat_dat->bsp_priv = dwmac;
> > dwmac->plat_dat = plat_dat;
> > + dwmac->base_addr = stmmac_res.addr;
> >
> > ret = imx_dwmac_clks_config(dwmac, true);
> > if (ret)
>
> --
> Pengutronix e.K. | Johannes Zink |
> Steuerwalder Str. 21 |
> https://www.pe/
> ngutronix.de%2F&data=05%7C01%7Cshenwei.wang%40nxp.com%7C761fbb75c
> 1c24cfe091508db928d8ade%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
> 0%7C638264908852977732%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
> wMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%
> 7C&sdata=2l2zNfIaNnRJENmERehNae8g%2F%2BQqlxD2YRx7ksY2X%2BE%3D&r
> eserved=0 |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686| Fax: +49-5121-206917-5555 |
Hi Shenwei,
On 8/1/23 19:10, Shenwei Wang wrote:
>
>
>> -----Original Message-----
>> From: Johannes Zink <[email protected]>
>> Sent: Tuesday, August 1, 2023 7:48 AM
>> To: Shenwei Wang <[email protected]>; Russell King
>> <[email protected]>; David S. Miller <[email protected]>; Eric
>> Dumazet <[email protected]>; Jakub Kicinski <[email protected]>; Paolo
>> Abeni <[email protected]>; Maxime Coquelin
>> <[email protected]>; Shawn Guo <[email protected]>; Sascha
>> Hauer <[email protected]>; Neil Armstrong <[email protected]>;
>> Kevin Hilman <[email protected]>; Vinod Koul <[email protected]>; Chen-
>> Yu Tsai <[email protected]>; Jernej Skrabec <[email protected]>; Samuel
>> Holland <[email protected]>
>> Cc: Giuseppe Cavallaro <[email protected]>; Alexandre Torgue
>> <[email protected]>; Jose Abreu <[email protected]>;
>> Pengutronix Kernel Team <[email protected]>; Fabio Estevam
>> <[email protected]>; dl-linux-imx <[email protected]>; Jerome Brunet
>> <[email protected]>; Martin Blumenstingl
>> <[email protected]>; Bhupesh Sharma
>> <[email protected]>; Nobuhiro Iwamatsu
>> <[email protected]>; Simon Horman
>> <[email protected]>; Andrew Halaney <[email protected]>;
>> Bartosz Golaszewski <[email protected]>; Wong Vee Khee
>> <[email protected]>; Revanth Kumar Uppala <[email protected]>; Jochen
>> Henneberg <[email protected]>; [email protected]; linux-
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; Frank Li <[email protected]>
>> Subject: [EXT] Re: [PATCH v3 net 2/2] net: stmmac: dwmac-imx: pause the TXC
>> clock in fixed-link
>>
>> Caution: This is an external email. Please take care when clicking links or
>> opening attachments. When in doubt, report the message using the 'Report this
>> email' button
>>
>>
>> Hi Shenwei,
>>
>> thanks for your patch.
>>
>> On 7/31/23 18:19, Shenwei Wang wrote:
>>> When using a fixed-link setup, certain devices like the SJA1105
>>> require a small pause in the TXC clock line to enable their internal
>>> tunable delay line (TDL).
>>
>> If this is only required for some devices, is it safe to enforce this behaviour
>> unconditionally for any kind of fixed link devices connected to the MX93 EQOS
>> or could this possibly break for other devices?
>>
>
> It won't impact normal devices. The link layer hasn't built up yet.
>
As Russel suggested in [1] - maybe you could rephrase your commit message for
your v4 to point this out to future reviewers (apparently multiple people have
had questions about this...) and have this fact also recorded in the git log
later on.
Also: does this only apply to i.MX93, or would we have to test and enable it on
e.g. i.MX8MP as well?
Thanks
Johannes
[1] ZMk/[email protected]
> Thanks,
> Shenwei
>
>> Best regards
>> Johannes
>>
>>>
>>> To satisfy this requirement, this patch temporarily disables the TX
>>> clock, and restarts it after a required period. This provides the
>>> required silent interval on the clock line for SJA1105 to complete the
>>> frequency transition and enable the internal TDLs.
>>>
>>> So far we have only enabled this feature on the i.MX93 platform.
>>>
>>> Signed-off-by: Shenwei Wang <[email protected]>
>>> Reviewed-by: Frank Li <[email protected]>
>>> ---
>>> .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 42 +++++++++++++++++++
>>> 1 file changed, 42 insertions(+)
>>>
>>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
>>> b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
>>> index 53ee5a42c071..2e4173d099f3 100644
>>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
>>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
>>> @@ -32,6 +32,7 @@
>>> #define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
>>>
>>> #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
>>> +#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
>>> #define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
>>> #define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
>>> #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
>>> @@ -40,6 +41,7 @@
>>> #define DMA_BUS_MODE 0x00001000
>>> #define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
>>> #define RMII_RESET_SPEED (0x3 << 14)
>>> +#define CTRL_SPEED_MASK GENMASK(15, 14)
>>>
>>> struct imx_dwmac_ops {
>>> u32 addr_width;
>>> @@ -56,6 +58,7 @@ struct imx_priv_data {
>>> struct regmap *intf_regmap;
>>> u32 intf_reg_off;
>>> bool rmii_refclk_ext;
>>> + void __iomem *base_addr;
>>>
>>> const struct imx_dwmac_ops *ops;
>>> struct plat_stmmacenet_data *plat_dat; @@ -212,6 +215,42 @@
>>> static void imx_dwmac_fix_speed(void *priv, uint speed, uint mode)
>>> dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
>>> }
>>>
>>> +static void imx_dwmac_fix_speed_mx93(void *priv, uint speed, uint
>>> +mode) {
>>> + struct imx_priv_data *dwmac = priv;
>>> + int ctrl, old_ctrl, iface;
>>> +
>>> + imx_dwmac_fix_speed(priv, speed, mode);
>>> +
>>> + if (!dwmac || mode != MLO_AN_FIXED)
>>> + return;
>>> +
>>> + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
>>> + return;
>>> +
>>> + iface &= MX93_GPR_ENET_QOS_INTF_MASK;
>>> + if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
>>> + return;
>>> +
>>> + old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
>>> + ctrl = old_ctrl & ~CTRL_SPEED_MASK;
>>> + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
>>> + MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
>>> + writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
>>> +
>>> + /* Ensure the settings for CTRL are applied and avoid CPU/Compiler
>>> + * reordering.
>>> + */
>>> + wmb();
>>> +
>>> + usleep_range(10, 20);
>>> + iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
>>> + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
>>> + MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
>>> +
>>> + writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG); }
>>> +
>>> static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
>>> {
>>> struct plat_stmmacenet_data *plat_dat = priv; @@ -317,8 +356,11
>>> @@ static int imx_dwmac_probe(struct platform_device *pdev)
>>> plat_dat->exit = imx_dwmac_exit;
>>> plat_dat->clks_config = imx_dwmac_clks_config;
>>> plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
>>> + if (of_machine_is_compatible("fsl,imx93"))
>>> + plat_dat->fix_mac_speed = imx_dwmac_fix_speed_mx93;
>>> plat_dat->bsp_priv = dwmac;
>>> dwmac->plat_dat = plat_dat;
>>> + dwmac->base_addr = stmmac_res.addr;
>>>
>>> ret = imx_dwmac_clks_config(dwmac, true);
>>> if (ret)
>>
>> --
>> Pengutronix e.K. | Johannes Zink |
>> Steuerwalder Str. 21 |
>> https://www.pe/
>> ngutronix.de%2F&data=05%7C01%7Cshenwei.wang%40nxp.com%7C761fbb75c
>> 1c24cfe091508db928d8ade%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C
>> 0%7C638264908852977732%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA
>> wMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%
>> 7C&sdata=2l2zNfIaNnRJENmERehNae8g%2F%2BQqlxD2YRx7ksY2X%2BE%3D&r
>> eserved=0 |
>> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
>> Amtsgericht Hildesheim, HRA 2686| Fax: +49-5121-206917-5555 |
>
>
--
Pengutronix e.K. | Johannes Zink |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686| Fax: +49-5121-206917-5555 |
> -----Original Message-----
> From: Johannes Zink <[email protected]>
> Sent: Wednesday, August 2, 2023 1:26 AM
> To: Shenwei Wang <[email protected]>; Russell King
> <[email protected]>; David S. Miller <[email protected]>; Eric
> Dumazet <[email protected]>; Jakub Kicinski <[email protected]>; Paolo
> Abeni <[email protected]>; Maxime Coquelin
> <[email protected]>; Shawn Guo <[email protected]>; Sascha
> Hauer <[email protected]>; Neil Armstrong <[email protected]>;
> Kevin Hilman <[email protected]>; Vinod Koul <[email protected]>; Chen-
> Yu Tsai <[email protected]>; Jernej Skrabec <[email protected]>; Samuel
> Holland <[email protected]>
> Cc: Giuseppe Cavallaro <[email protected]>; Alexandre Torgue
> <[email protected]>; Jose Abreu <[email protected]>;
> Pengutronix Kernel Team <[email protected]>; Fabio Estevam
> <[email protected]>; dl-linux-imx <[email protected]>; Jerome Brunet
> <[email protected]>; Martin Blumenstingl
> <[email protected]>; Bhupesh Sharma
> <[email protected]>; Nobuhiro Iwamatsu
> <[email protected]>; Simon Horman
> <[email protected]>; Andrew Halaney <[email protected]>;
> Bartosz Golaszewski <[email protected]>; Wong Vee Khee
> <[email protected]>; Revanth Kumar Uppala <[email protected]>; Jochen
> Henneberg <[email protected]>; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Frank Li <[email protected]>
> Subject: Re: [EXT] Re: [PATCH v3 net 2/2] net: stmmac: dwmac-imx: pause the
> TXC clock in fixed-link
>
> Caution: This is an external email. Please take care when clicking links or
> opening attachments. When in doubt, report the message using the 'Report this
> email' button
>
>
> Hi Shenwei,
>
> On 8/1/23 19:10, Shenwei Wang wrote:
> >
> >
> >> -----Original Message-----
> >> From: Johannes Zink <[email protected]>
> >> Sent: Tuesday, August 1, 2023 7:48 AM
> >> To: Shenwei Wang <[email protected]>; Russell King
> >> <[email protected]>; David S. Miller <[email protected]>; Eric
> >> Dumazet <[email protected]>; Jakub Kicinski <[email protected]>;
> >> Paolo Abeni <[email protected]>; Maxime Coquelin
> >> <[email protected]>; Shawn Guo <[email protected]>;
> Sascha
> >> Hauer <[email protected]>; Neil Armstrong
> >> <[email protected]>; Kevin Hilman <[email protected]>;
> >> Vinod Koul <[email protected]>; Chen- Yu Tsai <[email protected]>; Jernej
> >> Skrabec <[email protected]>; Samuel Holland
> >> <[email protected]>
> >> Cc: Giuseppe Cavallaro <[email protected]>; Alexandre Torgue
> >> <[email protected]>; Jose Abreu <[email protected]>;
> >> Pengutronix Kernel Team <[email protected]>; Fabio Estevam
> >> <[email protected]>; dl-linux-imx <[email protected]>; Jerome Brunet
> >> <[email protected]>; Martin Blumenstingl
> >> <[email protected]>; Bhupesh Sharma
> >> <[email protected]>; Nobuhiro Iwamatsu
> >> <[email protected]>; Simon Horman
> >> <[email protected]>; Andrew Halaney <[email protected]>;
> >> Bartosz Golaszewski <[email protected]>; Wong Vee Khee
> >> <[email protected]>; Revanth Kumar Uppala <[email protected]>;
> >> Jochen Henneberg <[email protected]>;
> >> [email protected]; linux- [email protected];
> >> [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; Frank Li <[email protected]>
> >> Subject: [EXT] Re: [PATCH v3 net 2/2] net: stmmac: dwmac-imx: pause
> >> the TXC clock in fixed-link
> >>
> >> Caution: This is an external email. Please take care when clicking
> >> links or opening attachments. When in doubt, report the message using
> >> the 'Report this email' button
> >>
> >>
> >> Hi Shenwei,
> >>
> >> thanks for your patch.
> >>
> >> On 7/31/23 18:19, Shenwei Wang wrote:
> >>> When using a fixed-link setup, certain devices like the SJA1105
> >>> require a small pause in the TXC clock line to enable their internal
> >>> tunable delay line (TDL).
> >>
> >> If this is only required for some devices, is it safe to enforce this
> >> behaviour unconditionally for any kind of fixed link devices
> >> connected to the MX93 EQOS or could this possibly break for other devices?
> >>
> >
> > It won't impact normal devices. The link layer hasn't built up yet.
> >
>
> As Russel suggested in [1] - maybe you could rephrase your commit message for
> your v4 to point this out to future reviewers (apparently multiple people have
> had questions about this...) and have this fact also recorded in the git log later
> on.
>
Okay.
> Also: does this only apply to i.MX93, or would we have to test and enable it on
> e.g. i.MX8MP as well?
>
Yes, it is required when the EQOS MAC is selected. However, this patch just enables
The feature on i.MX93.
Thanks,
Shenwei
> Thanks
> Johannes
>
> [1] ZMk/[email protected]
>
>
> > Thanks,
> > Shenwei
> >
> >> Best regards
> >> Johannes
> >>
> >>>
> >>> To satisfy this requirement, this patch temporarily disables the TX
> >>> clock, and restarts it after a required period. This provides the
> >>> required silent interval on the clock line for SJA1105 to complete
> >>> the frequency transition and enable the internal TDLs.
> >>>
> >>> So far we have only enabled this feature on the i.MX93 platform.
> >>>
> >>> Signed-off-by: Shenwei Wang <[email protected]>
> >>> Reviewed-by: Frank Li <[email protected]>
> >>> ---
> >>> .../net/ethernet/stmicro/stmmac/dwmac-imx.c | 42
> +++++++++++++++++++
> >>> 1 file changed, 42 insertions(+)
> >>>
> >>> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> >>> b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> >>> index 53ee5a42c071..2e4173d099f3 100644
> >>> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> >>> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-imx.c
> >>> @@ -32,6 +32,7 @@
> >>> #define GPR_ENET_QOS_RGMII_EN (0x1 << 21)
> >>>
> >>> #define MX93_GPR_ENET_QOS_INTF_MODE_MASK GENMASK(3, 0)
> >>> +#define MX93_GPR_ENET_QOS_INTF_MASK GENMASK(3, 1)
> >>> #define MX93_GPR_ENET_QOS_INTF_SEL_MII (0x0 << 1)
> >>> #define MX93_GPR_ENET_QOS_INTF_SEL_RMII (0x4 << 1)
> >>> #define MX93_GPR_ENET_QOS_INTF_SEL_RGMII (0x1 << 1)
> >>> @@ -40,6 +41,7 @@
> >>> #define DMA_BUS_MODE 0x00001000
> >>> #define DMA_BUS_MODE_SFT_RESET (0x1 << 0)
> >>> #define RMII_RESET_SPEED (0x3 << 14)
> >>> +#define CTRL_SPEED_MASK GENMASK(15, 14)
> >>>
> >>> struct imx_dwmac_ops {
> >>> u32 addr_width;
> >>> @@ -56,6 +58,7 @@ struct imx_priv_data {
> >>> struct regmap *intf_regmap;
> >>> u32 intf_reg_off;
> >>> bool rmii_refclk_ext;
> >>> + void __iomem *base_addr;
> >>>
> >>> const struct imx_dwmac_ops *ops;
> >>> struct plat_stmmacenet_data *plat_dat; @@ -212,6 +215,42 @@
> >>> static void imx_dwmac_fix_speed(void *priv, uint speed, uint mode)
> >>> dev_err(dwmac->dev, "failed to set tx rate %lu\n", rate);
> >>> }
> >>>
> >>> +static void imx_dwmac_fix_speed_mx93(void *priv, uint speed, uint
> >>> +mode) {
> >>> + struct imx_priv_data *dwmac = priv;
> >>> + int ctrl, old_ctrl, iface;
> >>> +
> >>> + imx_dwmac_fix_speed(priv, speed, mode);
> >>> +
> >>> + if (!dwmac || mode != MLO_AN_FIXED)
> >>> + return;
> >>> +
> >>> + if (regmap_read(dwmac->intf_regmap, dwmac->intf_reg_off, &iface))
> >>> + return;
> >>> +
> >>> + iface &= MX93_GPR_ENET_QOS_INTF_MASK;
> >>> + if (iface != MX93_GPR_ENET_QOS_INTF_SEL_RGMII)
> >>> + return;
> >>> +
> >>> + old_ctrl = readl(dwmac->base_addr + MAC_CTRL_REG);
> >>> + ctrl = old_ctrl & ~CTRL_SPEED_MASK;
> >>> + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
> >>> + MX93_GPR_ENET_QOS_INTF_MODE_MASK, 0);
> >>> + writel(ctrl, dwmac->base_addr + MAC_CTRL_REG);
> >>> +
> >>> + /* Ensure the settings for CTRL are applied and avoid CPU/Compiler
> >>> + * reordering.
> >>> + */
> >>> + wmb();
> >>> +
> >>> + usleep_range(10, 20);
> >>> + iface |= MX93_GPR_ENET_QOS_CLK_GEN_EN;
> >>> + regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off,
> >>> + MX93_GPR_ENET_QOS_INTF_MODE_MASK, iface);
> >>> +
> >>> + writel(old_ctrl, dwmac->base_addr + MAC_CTRL_REG); }
> >>> +
> >>> static int imx_dwmac_mx93_reset(void *priv, void __iomem *ioaddr)
> >>> {
> >>> struct plat_stmmacenet_data *plat_dat = priv; @@ -317,8
> >>> +356,11 @@ static int imx_dwmac_probe(struct platform_device *pdev)
> >>> plat_dat->exit = imx_dwmac_exit;
> >>> plat_dat->clks_config = imx_dwmac_clks_config;
> >>> plat_dat->fix_mac_speed = imx_dwmac_fix_speed;
> >>> + if (of_machine_is_compatible("fsl,imx93"))
> >>> + plat_dat->fix_mac_speed = imx_dwmac_fix_speed_mx93;
> >>> plat_dat->bsp_priv = dwmac;
> >>> dwmac->plat_dat = plat_dat;
> >>> + dwmac->base_addr = stmmac_res.addr;
> >>>
> >>> ret = imx_dwmac_clks_config(dwmac, true);
> >>> if (ret)
> >>
> >> --
> >> Pengutronix e.K. | Johannes Zink |
> >> Steuerwalder Str. 21 |
> >> https://www/
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> >> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> >> Amtsgericht Hildesheim, HRA 2686| Fax: +49-5121-206917-5555 |
> >
> >
>
> --
> Pengutronix e.K. | Johannes Zink |
> Steuerwalder Str. 21 |
> https://www.pe/
> ngutronix.de%2F&data=05%7C01%7Cshenwei.wang%40nxp.com%7Ccfd142f0d
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> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686| Fax: +49-5121-206917-5555 |