I've been poring over the x86 boot code for a while now and I've been
considering writing a FAQ on the boot process (mostly for my own use,
but maybe others will be interested). This would include all relevant
information on setting up the x86 hardware for a boot (timers, PIC, A20,
protected mode, GDT, initial page tables, initial TSS, etc).
The motivation behind this is that I would like to use the Linux boot
system as a boilerplate booter for some experimental code. It's probably
much cleaner and more robust than any boot loader I might come up with.
Does there exist an outline (detailed or not) of the boot process from
the point of BIOS bootsector load to when the kernel proper begins
execution? If not would anyone be willing to help me understand
bootsect.S and setup.S enough so that I might write such an outline?
If no one can help me, would you consider it appropriate for me to send
email to the people listed in bootsect.S and setup.S asking for
assistance?
Thanks,
Scott
Scott Long wrote:
> Does there exist an outline (detailed or not) of the boot process from
> the point of BIOS bootsector load to when the kernel proper begins
> execution? If not would anyone be willing to help me understand
> bootsect.S and setup.S enough so that I might write such an outline?
I have been over it, and would be willing to help. You should first read all
of the LILO documentation, and check out some of the LinuxBIOS
project at http://www.linuxbios.org.
Have you seen Janet_Reno?
ftp://linux01.gwdg.de/pub/cLIeNUX/interim/Janet_Reno.tgz IIRC.
Janet is an x86 bootsector that gets into protected mode and can
use the AT BIOS in pmode interrupts. It's written with a bunch of
m4 macros I call asmacs that I'm currently basing an assembler in
Bash on. That's shasm in the same directory as Janet.
Rick Hohensee
http://www.cLIeNUX.com
On Sun, 18 Feb 2001, Scott Long wrote:
> Does there exist an outline (detailed or not) of the boot process from
> the point of BIOS bootsector load to when the kernel proper begins
> execution? If not would anyone be willing to help me understand
> bootsect.S and setup.S enough so that I might write such an outline?
It might be a little fundamental but there is *a* boot loading process
documented here: http://www.eecs.wsu.edu/~cs460/
Look over all the lecture notes and lab assignments up to the booter lab.
I'd offer up my own explanation, but I'm just starting to learn this
stuff.
-karl
> I've been poring over the x86 boot code for a while now and I've been
> considering writing a FAQ on the boot process (mostly for my own use,
> but maybe others will be interested). This would include all relevant
> information on setting up the x86 hardware for a boot (timers, PIC, A20,
> protected mode, GDT, initial page tables, initial TSS, etc).
It would certainly be a valuable piece for the kernel Documentation dir.
Paticularly as people with embedded x86 grow keener and keener to boot
biosless to save money and flash.
Scott Long wrote:
>
> I've been poring over the x86 boot code for a while now and I've been
> considering writing a FAQ on the boot process (mostly for my own use,
[...]
> Does there exist an outline (detailed or not) of the boot process from
> the point of BIOS bootsector load to when the kernel proper begins
IIRC, there is some useful info contained within loadlin. Also, I
found a doc by hpa called "THE LINUX/I386 BOOT PROTOCOL" in my local
archive of cruft - I just assumed it was in Documentation/ but
apparently it never made it there (yet).
Paul.
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Alan Cox <[email protected]> writes:
> > I've been poring over the x86 boot code for a while now and I've been
> > considering writing a FAQ on the boot process (mostly for my own use,
> > but maybe others will be interested). This would include all relevant
> > information on setting up the x86 hardware for a boot (timers, PIC, A20,
> > protected mode, GDT, initial page tables, initial TSS, etc).
>
> It would certainly be a valuable piece for the kernel Documentation dir.
> Paticularly as people with embedded x86 grow keener and keener to boot
> biosless to save money and flash.
Actually biosless is nice. You don't actually need to do things like enable
a20 as there isn't a BIOS to disable it...
As for working code see the linuxBIOS project. http://www.linuxbios.org
There aren't a lot of chipsets supported yet but progress is being made.
And you do need something like a BIOS to enable memory and cache
before you jump to the linux kernel.
Alan working on all booting x86 biosless, keeps making me chuckle over
your hatred towards BIOSes, it is absolutely amazing what linux
assumes the BIOS will setup correctly. With linux-2.4 able to do a
complete PCI bus setup it isn't as bad it used to be, but it's still
pretty significant.
You wouldn't happen to know a good place to put drivers for superio
chips, and pci-isa bridges with the superio functions integrated?
I should have a proposal written up (and the code to implement it) in
the next month, on how to change the boot process to be more friendly
to BIOS less situations. What we do with the ``empty_zero_page'' is
nasty, and it isn't even the empty_zero_page.
And if anyone has any questions on how the boot process works,
I'd be glad to answer specific questions. As I've traced it fairly
thoroughly.
Eric
Paul Gortmaker wrote:
>
> Scott Long wrote:
> >
> > I've been poring over the x86 boot code for a while now and I've been
> > considering writing a FAQ on the boot process (mostly for my own use,
>
> [...]
>
> > Does there exist an outline (detailed or not) of the boot process from
> > the point of BIOS bootsector load to when the kernel proper begins
>
> IIRC, there is some useful info contained within loadlin. Also, I
> found a doc by hpa called "THE LINUX/I386 BOOT PROTOCOL" in my local
> archive of cruft - I just assumed it was in Documentation/ but
> apparently it never made it there (yet).
>
It's in there (Documentation/i386/boot.txt).
-hpa
--
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"Unix gives you enough rope to shoot yourself in the foot."
http://www.zytor.com/~hpa/puzzle.txt
On Mon, Feb 19, 2001 at 03:07:33AM -0700, Eric W. Biederman wrote:
> With linux-2.4 able to do a complete PCI bus setup it isn't as bad it used
> to be, but it's still pretty significant.
For an incomplete subset of chipsets. Serverworks doesn't work correctly for
a start (see the threads relating to having to kill the Serverworks fixup code
and rely on the BIOS to see all the PCI busses on larger systems). Of course,
this is due to Serverworks refusal to release documentation (yes, I've heard
the excuses regarding protection of IP), and it's a worrisome. What else are
we potentially failing to setup on this chipset ?
Tim
--
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IBM Linux Technology Center, Beaverton, Oregon
Interested in Linux scalability ? Look at http://lse.sourceforge.net/
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