> Allen, is there a possibility to get a clarification from
> Nvidia on that?
> Specifically, assuming both an 8254 and an I/O APIC core are
> integrated
> into the chip, whether OUT0 of the 8254 is unconditionally routed to
> INTIN0 of the I/O APIC or is it configurable somehow.
The 8254 PIT is hardwared to IRQ0 on all nForce chipsets, it can't be routed.
-Allen
On Thu, 22 Apr 2004, Allen Martin wrote:
> The 8254 PIT is hardwared to IRQ0 on all nForce chipsets, it can't be routed.
Thanks for this info. Thus the workaround can be unconditional.
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: [email protected], PGP key available +